[LinuxBIOS] epia, rom_cc and locking code
Ok first off the issue with ROM_CC and #if - #else - #endif not compiling properly. After some testing I have at least found the problem and it only ever happens if you put a C++ style comment on the same line as the #if or #else so in the following example static void test_ifdef(void) { #if TEST_IFDEF // blows up outb(50,100); outb(51,100); outb(52,100); #else /* ok */ outb(60,100); outb(61,100); outb(62,100); #endif } Of course no comment works fine as well. Also putting a blank line after the comment produces the correct code. I can't say for the rest of the linuxbios code, but the via/epia code seems to have a good mixture of both types of comments. Perhaps as the code is not strictly C++ you should stick to using standard C style comments. Ok now to my problems with the EPIA board. I think in general it is working ok, but I still have some problems.
From a cold boot and also at other times, it will just hang. I am having problems tracking down just where it hangs.
At first sight it appears to happen inside the SMBus read function, but that is a guess from the debug output. The problem I get is if I try and add any debug output inside SMBus read it gets worse and locks more frequently. If I have the memory test enabled it can also lock up when doing the verify. So I guess I can think of 3 reason for it to lock. 1. Some enabled, but not handled interrupt is happening. (I would assume that all interrupts are disabled at powerup but hardware so this is probably not it) 2. Southbridge is not configured properly. (would be very bad chip design if the SMBus part of the southbridge interferred with the rest of the functionality) 3. It is actually running, but serial output has stopped. ( don't think this is the case as it never boots up) I guess I need to look for loops that can become locked, probably withing the serial output code. Can anyone think of some other reason for it to lock up ?
* Ben Hewson <ben@hewson-venieri.com> [061021 12:18]:
Ok first off the issue with ROM_CC and #if - #else - #endif not compiling properly.
After some testing I have at least found the problem and it only ever happens if you put a C++ style comment on the same line as the #if or #else
Ok now to my problems with the EPIA board. I think in general it is working ok, but I still have some problems. From a cold boot and also at other times, it will just hang. I am having problems tracking down just where it hangs.
Does it work since the above problem was fixed? Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info@coresystems.de • http://www.coresystems.de/
Stefan Reinauer wrote:
* Ben Hewson <ben@hewson-venieri.com> [061021 12:18]:
Ok first off the issue with ROM_CC and #if - #else - #endif not compiling properly.
After some testing I have at least found the problem and it only ever happens if you put a C++ style comment on the same line as the #if or #else
Ok now to my problems with the EPIA board. I think in general it is working ok, but I still have some problems. From a cold boot and also at other times, it will just hang. I am having problems tracking down just where it hangs.
Does it work since the above problem was fixed?
Stefan
Yes rom_cc is fine, but I have a problem where changes to the code base seem to have caused ide problems with Filo(it cant see the ide drive). I haven't spent much time investigating this lately, been busy with other things. Ben
* Ben Hewson <ben@hewson-venieri.com> [070113 19:38]:
Stefan Reinauer wrote: Yes rom_cc is fine, but I have a problem where changes to the code base seem to have caused ide problems with Filo(it cant see the ide drive).
- what IDE drive? - what FILO? (svn rev?) - Did you change the filo config? - Do you have a log file? -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info@coresystems.de • http://www.coresystems.de/
Stefan Reinauer wrote:
* Ben Hewson <ben@hewson-venieri.com> [070113 19:38]:
Stefan Reinauer wrote: Yes rom_cc is fine, but I have a problem where changes to the code base seem to have caused ide problems with Filo(it cant see the ide drive).
- what IDE drive? - what FILO? (svn rev?) - Did you change the filo config? - Do you have a log file?
there are some posts on the mailing list I made, but basically my older version of linuxbios using filo boots, but a later version after the rom_cc patch doesn't boot any more. exactly the same hardware and filo image (v 0.5 ). I get the following error from filo using the later version. Detected floating bus No drive detected on IDE channel 0 The older version I have works just fine though. Have attached the log files from both working and non working versions. If you compare the two you will see that the pci enumeration/allocation of resources if different, although it only appears to be so with respect to the ide controller. I have been comparing both sets of files to find any differences. The biggest change I can see is the change to the pci read/write functions, where the 'where' parameter changed from 8 to 16 bits but I dont think that is the problem. Ben Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-2.0.0.0Normal Mon Dec 4 20:57:05 GMT 2006 booting... Enumerating buses... scan_static_bus for Root Device Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [1106/0601] ops PCI: 00:00.0 [1106/0601] enabled malloc Enter, size 668, free_mem_ptr 00018000 malloc 0x00018000 Capability: 0x07 @ 0x80 Capability: 0x08 @ 0x80 Capability: 0x10 @ 0x80 PCI: 00:01.0 [1106/8601] enabled PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: 00:11.0 [1106/8231] bus ops PCI: 00:11.0 [1106/8231] enabled PCI: 00:11.1 [1106/0571] ops PCI: 00:11.1 [1106/0571] enabled PCI: 00:11.2 [1106/3038] disabled PCI: 00:11.3 [1106/3038] disabled PCI: 00:11.4 [1106/8235] ops PCI: 00:11.4 [1106/8235] disabled PCI: 00:11.5 [1106/3058] disabled PCI: 00:11.6 [1106/3068] enabled PCI: devfn 0x8f, bad id 0xffffffff PCI: 00:12.0 [1106/3065] ops PCI: 00:12.0 [1106/3065] enabled PCI: devfn 0x98, bad id 0xffffffff malloc Enter, size 668, free_mem_ptr 0001829c malloc 0x0001829c PCI: 00:14.0 [1814/0301] enabled PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 PCI: devfn 0x0, bad id 0xffffffff PCI: devfn 0x8, bad id 0xffffffff PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: devfn 0x88, bad id 0xffffffff PCI: devfn 0x90, bad id 0xffffffff PCI: devfn 0x98, bad id 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:11.0 PNP: 002e.0 enabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 disabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled PNP: 002e.b enabled scan_static_bus for PCI: 00:11.0 done PCI: pci_scan_bus returning with max=001 scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:01.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 done PCI: 00:01.0 compute_allocate_io: base: 0000f000 size: 00000000 align: 12 gran: 12 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_io: base: 0000f000 size: 00000000 align: 12 gran: 12 done PCI: 00:01.0 1c <- [0x000000f000 - 0x000000efff] bus 01 io PCI: 00:01.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:01.0 compute_allocate_prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:01.0 24 <- [0x00fff00000 - 0x00ffefffff] bus 01 prefmem PCI: 00:01.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:01.0 compute_allocate_mem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_mem: base: fff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:01.0 20 <- [0x00fff00000 - 0x00ffefffff] bus 01 mem PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done PCI: 00:11.6 10 * [0x00000400 - 0x000004ff] io PCI: 00:12.0 10 * [0x00000800 - 0x000008ff] io PCI: 00:11.1 20 * [0x00000c00 - 0x00000c0f] io PCI: 00:11.1 10 * [0x00000c10 - 0x00000c17] io PCI: 00:11.1 18 * [0x00000c20 - 0x00000c27] io PCI: 00:11.1 14 * [0x00000c30 - 0x00000c33] io PCI: 00:11.1 1c * [0x00000c40 - 0x00000c43] io Root Device compute_allocate_io: base: 00000c44 size: 00000844 align: 8 gran: 0 done Root Device compute_allocate_mem: base: 00000000 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:14.0 10 * [0x00000000 - 0x00007fff] mem PCI: 00:12.0 14 * [0x00008000 - 0x000080ff] mem Root Device compute_allocate_mem: base: 00008100 size: 00008100 align: 15 gran: 0 done Done reading resources. Setting resources... Root Device compute_allocate_io: base: 00001000 size: 00000844 align: 8 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:11.6 10 * [0x00001000 - 0x000010ff] io PCI: 00:12.0 10 * [0x00001400 - 0x000014ff] io PCI: 00:11.1 20 * [0x00001800 - 0x0000180f] io PCI: 00:11.1 10 * [0x00001810 - 0x00001817] io PCI: 00:11.1 18 * [0x00001820 - 0x00001827] io PCI: 00:11.1 14 * [0x00001830 - 0x00001833] io PCI: 00:11.1 1c * [0x00001840 - 0x00001843] io Root Device compute_allocate_io: base: 00001844 size: 00000844 align: 8 gran: 0 done Root Device compute_allocate_mem: base: febf0000 size: 00008100 align: 15 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:14.0 10 * [0xfebf0000 - 0xfebf7fff] mem PCI: 00:12.0 14 * [0xfebf8000 - 0xfebf80ff] mem Root Device compute_allocate_mem: base: febf8100 size: 00008100 align: 15 gran: 0 done Root Device assign_resources, bus 0 link: 0 I would set ram size to 0x40000 Kbytes PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:11.1 10 <- [0x0000001810 - 0x0000001817] io PCI: 00:11.1 14 <- [0x0000001830 - 0x0000001833] io PCI: 00:11.1 18 <- [0x0000001820 - 0x0000001827] io PCI: 00:11.1 1c <- [0x0000001840 - 0x0000001843] io PCI: 00:11.1 20 <- [0x0000001800 - 0x000000180f] io PCI: 00:11.6 10 <- [0x0000001000 - 0x00000010ff] io PCI: 00:12.0 10 <- [0x0000001400 - 0x00000014ff] io PCI: 00:12.0 14 <- [0x00febf8000 - 0x00febf80ff] mem PCI: 00:14.0 10 <- [0x00febf0000 - 0x00febf7fff] mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Done allocating resources. Enabling resources... PCI: 00:00.0 cmd <- 146 PCI: 00:01.0 bridge ctrl <- 0003 PCI: 00:01.0 cmd <- 147 PCI: 00:11.0 cmd <- 1c7 PCI: 00:11.1 cmd <- 1c1 PCI: 00:11.6 subsystem <- 00/00 PCI: 00:11.6 cmd <- 141 PCI: 00:12.0 cmd <- 1c3 PCI: 00:14.0 cmd <- 142 done. Initializing devices... Root Device init PCI: 00:00.0 init VT8601 random fixup ... PCI: 00:11.0 init vt8231 init IDE enable in reg. 50 is 0x7 set IDE reg. 50 to 0x7 IRQs in reg. 4c are 0x4 setting reg. 4c to 0x4 RTC Init Invalid CMOS LB checksum pci_routing_fixup: dev is 0000f840 setting southbridge Assigning IRQ 12 to 0:11.2 Readback = 12 pci_level_irq: current ints are 0x0 pci_level_irq: try to set ints 0x1000 Assigning IRQ 12 to 0:11.3 Readback = 12 pci_level_irq: current ints are 0x1000 pci_level_irq: try to set ints 0x1000 Assigning IRQ 10 to 0:11.5 Readback = 10 pci_level_irq: current ints are 0x1000 pci_level_irq: try to set ints 0x1400 Assigning IRQ 10 to 0:11.6 Readback = 10 pci_level_irq: current ints are 0x1400 pci_level_irq: try to set ints 0x1400 setting ethernet Assigning IRQ 11 to 0:12.0 Readback = 11 pci_level_irq: current ints are 0x1400 pci_level_irq: try to set ints 0x1c00 setting pci slot Assigning IRQ 5 to 0:14.0 Readback = 5 pci_level_irq: current ints are 0x1c00 pci_level_irq: try to set ints 0x1c20 pci_routing_fixup: DONE PNP: 002e.0 init PNP: 002e.2 init PNP: 002e.5 init PNP: 002e.b init PCI: 00:11.1 init ide_init: enabling compatibility IDE addresses enables in reg 0x42 0xc9 enables in reg 0x42 read back as 0x9 enables in reg 0x40 0x8 enables in reg 0x40 read back as 0xb enables in reg 0x9 0x8f enables in reg 0x9 read back as 0x8a command in reg 0x4 0x81 command in reg 0x4 reads back as 0x7 PCI: 00:11.6 init PCI: 00:12.0 init Configuring VIA LAN APIC_CLUSTER: 0 init malloc Enter, size 668, free_mem_ptr 00018538 malloc 0x00018538 Initializing CPU #0 CPU: vendor Centaur device 673 CPU: family 06, model 07, stepping 03 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-88) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xf DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling local apic...done. CPU #0 Initialized PCI: 00:14.0 init Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 done. Moving GDT to 0x500...ok Wrote linuxbios table at: 00000530 - 00000b4c checksum 6adf Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 rom_stream: 0xfffc0000 - 0xfffcffff Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 malloc Enter, size 32, free_mem_ptr 000187d4 malloc 0x000187d4 New segment addr 0x100000 size 0x20100 offset 0xe0 filesize 0x6168 (cleaned up) New segment addr 0x100000 size 0x20100 offset 0xe0 filesize 0x6168 lb: [0x0000000000004000, 0x000000000001c000) malloc Enter, size 32, free_mem_ptr 000187f4 malloc 0x000187f4 New segment addr 0x120100 size 0x48 offset 0x6260 filesize 0x48 (cleaned up) New segment addr 0x120100 size 0x48 offset 0x6260 filesize 0x48 lb: [0x0000000000004000, 0x000000000001c000) Dropping non PT_LOAD segment Dropping non PT_LOAD segment Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000020100 filesz: 0x0000000000006168 [ 0x0000000000100000, 0000000000106168, 0x0000000000120100) <- 00000000000000e0 Clearing Segment: addr: 0x0000000000106168 memsz: 0x0000000000019f98 Loading Segment: addr: 0x0000000000120100 memsz: 0x0000000000000048 filesz: 0x0000000000000048 [ 0x0000000000120100, 0000000000120148, 0x0000000000120148) <- 0000000000006260 Loaded segments verified segments closed down stream Jumping to boot code at 0x1041d8 entry = 0x001041d8 lb_start = 0x00004000 lb_size = 0x00018000 adjust = 0x0ffe4000 buffer = 0x0ffd0000 elf_boot_notes = 0x00013000 adjusted_boot_notes = 0x0fff7000 FILO version 0.5 (root@localhost) Sun Nov 12 17:35:53 GMT 2006 boot: hda1:/kern root=/dev/hda3 console=ttyS0,115200 Detected floating bus No drive detected on IDE channel 0 boot: hda1:/kern root=/dev/hda3 console=ttyS0,115200 Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-2.0.0.0Normal Fri Nov 10 18:45:42 GMT 2006 booting... Enumerating buses... scan_static_bus for Root Device Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [1106/0601] ops PCI: 00:00.0 [1106/0601] enabled malloc Enter, size 668, free_mem_ptr 00018000 malloc 0x00018000 Capability: 0x07 @ 0x80 Capability: 0x08 @ 0x80 Capability: 0x10 @ 0x80 PCI: 00:01.0 [1106/8601] enabled PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: 00:11.0 [1106/8231] bus ops PCI: 00:11.0 [1106/8231] enabled PCI: 00:11.1 [1106/0571] ops PCI: 00:11.1 [1106/0571] enabled PCI: 00:11.2 [1106/3038] disabled PCI: 00:11.3 [1106/3038] disabled PCI: 00:11.4 [1106/8235] ops PCI: 00:11.4 [1106/8235] disabled PCI: 00:11.5 [1106/3058] disabled PCI: 00:11.6 [1106/3068] enabled PCI: devfn 0x8f, bad id 0xffffffff PCI: 00:12.0 [1106/3065] ops PCI: 00:12.0 [1106/3065] enabled PCI: devfn 0x98, bad id 0xffffffff malloc Enter, size 668, free_mem_ptr 0001829c malloc 0x0001829c PCI: 00:14.0 [1814/0301] enabled PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 1 PCI: devfn 0x0, bad id 0xffffffff PCI: devfn 0x8, bad id 0xffffffff PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: devfn 0x88, bad id 0xffffffff PCI: devfn 0x90, bad id 0xffffffff PCI: devfn 0x98, bad id 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus returning with max=01 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:11.0 PNP: 002e.0 enabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 disabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled PNP: 002e.b enabled scan_static_bus for PCI: 00:11.0 done PCI: pci_scan_bus returning with max=01 scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:01.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 done PCI: 00:01.0 compute_allocate_io: base: 0000f000 size: 00000000 align: 12 gran: 12 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_io: base: 0000f000 size: 00000000 align: 12 gran: 12 done PCI: 00:01.0 1c <- [0x000000f000 - 0x000000efff] bus 1 io PCI: 00:01.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:01.0 compute_allocate_prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:01.0 24 <- [0x00fff00000 - 0x00ffefffff] bus 1 prefmem PCI: 00:01.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:01.0 compute_allocate_mem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_mem: base: fff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:01.0 20 <- [0x00fff00000 - 0x00ffefffff] bus 1 mem PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done PCI: 00:11.6 10 * [0x00000400 - 0x000004ff] io PCI: 00:12.0 10 * [0x00000800 - 0x000008ff] io PCI: 00:11.1 20 * [0x00000c00 - 0x00000c0f] io Root Device compute_allocate_io: base: 00000c10 size: 00000810 align: 8 gran: 0 done Root Device compute_allocate_mem: base: 00000000 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:14.0 10 * [0x00000000 - 0x00007fff] mem PCI: 00:12.0 14 * [0x00008000 - 0x000080ff] mem Root Device compute_allocate_mem: base: 00008100 size: 00008100 align: 15 gran: 0 done Done reading resources. Setting resources... Root Device compute_allocate_io: base: 00001000 size: 00000810 align: 8 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:11.6 10 * [0x00001000 - 0x000010ff] io PCI: 00:12.0 10 * [0x00001400 - 0x000014ff] io PCI: 00:11.1 20 * [0x00001800 - 0x0000180f] io Root Device compute_allocate_io: base: 00001810 size: 00000810 align: 8 gran: 0 done Root Device compute_allocate_mem: base: febf0000 size: 00008100 align: 15 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:14.0 10 * [0xfebf0000 - 0xfebf7fff] mem PCI: 00:12.0 14 * [0xfebf8000 - 0xfebf80ff] mem Root Device compute_allocate_mem: base: febf8100 size: 00008100 align: 15 gran: 0 done Root Device assign_resources, bus 0 link: 0 I would set ram size to 0x40000 Kbytes PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:11.1 20 <- [0x0000001800 - 0x000000180f] io PCI: 00:11.6 10 <- [0x0000001000 - 0x00000010ff] io PCI: 00:12.0 10 <- [0x0000001400 - 0x00000014ff] io PCI: 00:12.0 14 <- [0x00febf8000 - 0x00febf80ff] mem PCI: 00:14.0 10 <- [0x00febf0000 - 0x00febf7fff] mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Done allocating resources. Enabling resources... PCI: 00:00.0 cmd <- 146 PCI: 00:01.0 bridge ctrl <- 0003 PCI: 00:01.0 cmd <- 147 PCI: 00:11.0 cmd <- 1c7 PCI: 00:11.1 cmd <- 1c1 PCI: 00:11.6 subsystem <- 00/00 PCI: 00:11.6 cmd <- 141 PCI: 00:12.0 cmd <- 1c3 PCI: 00:14.0 cmd <- 142 done. Initializing devices... Root Device init PCI: 00:00.0 init VT8601 random fixup ... PCI: 00:11.0 init vt8231 init IDE enable in reg. 50 is 0x7 set IDE reg. 50 to 0x7 IRQs in reg. 4c are 0x4 setting reg. 4c to 0x4 RTC Init RTC: Checksum invalid zeroing cmos Invalid CMOS LB checksum pci_routing_fixup: dev is 0000f720 setting southbridge Assigning IRQ 12 to 0:11.2 Readback = 12 pci_level_irq: current ints are 0x0 pci_level_irq: try to set ints 0x1000 pci_level_irq: lower order bits are wrong: want 0x0, got 0x10 Assigning IRQ 12 to 0:11.3 Readback = 12 pci_level_irq: current ints are 0x1000 pci_level_irq: try to set ints 0x1000 pci_level_irq: lower order bits are wrong: want 0x0, got 0x10 Assigning IRQ 10 to 0:11.5 Readback = 10 pci_level_irq: current ints are 0x1000 pci_level_irq: try to set ints 0x1400 pci_level_irq: lower order bits are wrong: want 0x4, got 0x14 Assigning IRQ 10 to 0:11.6 Readback = 10 pci_level_irq: current ints are 0x1400 pci_level_irq: try to set ints 0x1400 pci_level_irq: lower order bits are wrong: want 0x4, got 0x14 setting ethernet Assigning IRQ 11 to 0:12.0 Readback = 11 pci_level_irq: current ints are 0x1400 pci_level_irq: try to set ints 0x1c00 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c setting pci slot Assigning IRQ 5 to 0:14.0 Readback = 5 pci_level_irq: current ints are 0x1c00 pci_level_irq: try to set ints 0x1c20 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c pci_routing_fixup: DONE PNP: 002e.0 init PNP: 002e.2 init PNP: 002e.5 init PNP: 002e.b init PCI: 00:11.1 init ide_init: enabling compatibility IDE addresses enables in reg 0x42 0x0 enables in reg 0x42 read back as 0x0 enables in reg 0x40 0x8 enables in reg 0x40 read back as 0xb enables in reg 0x9 0x8f enables in reg 0x9 read back as 0x8a command in reg 0x4 0x81 command in reg 0x4 reads back as 0x7 PCI: 00:11.6 init PCI: 00:12.0 init Configuring VIA LAN APIC_CLUSTER: 0 init malloc Enter, size 668, free_mem_ptr 00018538 malloc 0x00018538 Initializing CPU #0 CPU: vendor Centaur device 673 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-88) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xf DONE variable MTRRs Clear out the extra MTRR's ADDRESS_MASK_HIGH=0xf ADDRESS_MASK_HIGH=0xf ADDRESS_MASK_HIGH=0xf ADDRESS_MASK_HIGH=0xf ADDRESS_MASK_HIGH=0xf ADDRESS_MASK_HIGH=0xf ADDRESS_MASK_HIGH=0xf call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling local apic...done. CPU #0 Initialized PCI: 00:14.0 init Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 done. Moving GDT to 0x500...ok Wrote linuxbios table at: 00000530 - 00000b4c checksum ced0 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 rom_stream: 0xfffc0000 - 0xfffcffff Found ELF candiate at offset 0 header_offset is 0 Try to load at offset 0x0 malloc Enter, size 32, free_mem_ptr 000187d4 malloc 0x000187d4 New segment addr 0x100000 size 0x20100 offset 0xe0 filesize 0x6168 (cleaned up) New segment addr 0x100000 size 0x20100 offset 0xe0 filesize 0x6168 lb: [0x0000000000004000, 0x000000000001c000) malloc Enter, size 32, free_mem_ptr 000187f4 malloc 0x000187f4 New segment addr 0x120100 size 0x48 offset 0x6260 filesize 0x48 (cleaned up) New segment addr 0x120100 size 0x48 offset 0x6260 filesize 0x48 lb: [0x0000000000004000, 0x000000000001c000) Dropping non PT_LOAD segment Dropping non PT_LOAD segment Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000020100 filesz: 0x0000000000006168 [ 0x0000000000100000, 0000000000106168, 0x0000000000120100) <- 00000000000000e0 Clearing Segment: addr: 0x0000000000106168 memsz: 0x0000000000019f98 Loading Segment: addr: 0x0000000000120100 memsz: 0x0000000000000048 filesz: 0x0000000000000048 [ 0x0000000000120100, 0000000000120148, 0x0000000000120148) <- 0000000000006260 Loaded segments verified segments closed down stream Jumping to boot code at 0x1041d8 entry = 0x001041d8 lb_start = 0x00004000 lb_size = 0x00018000 adjust = 0x0ffe4000 buffer = 0x0ffd0000 elf_boot_notes = 0x00012ee0 adjusted_boot_notes = 0x0fff6ee0 FILO version 0.5 (root@localhost) Thu Oct 5 20:44:46 BST 2006 boot: hda1:/kern root=/dev/hda3 console=ttyS0,115200 hda: LBA48 80GB: ST380011A Mounted ext2fs Found Linux version 2.6.15.1 (root@musicbox) #8 PREEMPT Fri Jun 30 20:04:19 BST 2006 bzImage. Loading kernel...
On 1/14/07, Ben Hewson <ben@hewson-venieri.com> wrote:
there are some posts on the mailing list I made, but basically my older version of linuxbios using filo boots, but a later version after the rom_cc patch doesn't boot any more.
exactly the same hardware and filo image (v 0.5 ).
can you get us a source-level diff? ron
ron minnich wrote:
On 1/14/07, Ben Hewson <ben@hewson-venieri.com> wrote:
there are some posts on the mailing list I made, but basically my older version of linuxbios using filo boots, but a later version after the rom_cc patch doesn't boot any more.
exactly the same hardware and filo image (v 0.5 ).
can you get us a source-level diff?
ron
as I have been putting in some extra debug to see if I could locate the problem, I updated to the latest version. just to check the problem is still there I have tried to build, and it does build ok but it won't load the filo payload. I am guessing this is to do with the new CONFIG_ROM_PAYLOAD_START setting. When I boot I get the following Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 rom_stream: 0xfffc0000 - 0xfffcffff NO header at 0 NO header at 16 NO header at 32 NO header at 48 : : NO header at 8096 header_offset is -1 Cannot Load ELF Image I assume this is to do with CONFIG_ROM_PAYLOAD_START. Do you have any advice at what I need to set it to ? anyway assuming the problem still exists I have attached the output from diff. As I havent really used diff very much, let me know if you need something more/different. Ben diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/i386/boot/acpi.c LinuxBIOSv2/src/arch/i386/boot/acpi.c 205a206,230
void acpi_create_slit(acpi_slit_t *slit) {
acpi_header_t *header=&(slit->header); unsigned long current=(unsigned long)slit+sizeof(acpi_slit_t);
memset((void *)slit, 0, sizeof(acpi_slit_t));
/* fill out header fields */ memcpy(header->signature, SLIT_NAME, 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, SLIT_TABLE, 8); memcpy(header->asl_compiler_id, ASLC, 4);
header->length = sizeof(acpi_slit_t); header->revision = 1;
// current = acpi_fill_slit(current);
/* recalculate length */ header->length= current - (unsigned long)slit;
header->checksum = acpi_checksum((void *)slit, header->length); }
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/i386/Config.lb LinuxBIOSv2/src/arch/i386/Config.lb 1a2
uses CONFIG_PRECOMPRESSED_PAYLOAD 2a4,6 uses HAVE_FAILOVER_BOOT uses USE_FAILOVER_IMAGE uses USE_FALLBACK_IMAGE 5c9,22 < ldscript init/ldscript.lb
if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE ldscript init/ldscript_failover.lb else ldscript init/ldscript.lb end else if USE_FALLBACK_IMAGE ldscript init/ldscript_fallback.lb else ldscript init/ldscript.lb end end
23c40 < action "cp -f $< $@" ---
action "cp $< $@" 30a48,60 # unlike nrv2b, lzma is a huge build mess. If they want lzma, they have to have built it makerule payload.lzma depends "$(PAYLOAD) " action "lzma e $(PAYLOAD) $@" end
# this one example shows the mess that has occurred. People are now mixing # conditional if in the make style with if in the config language style. # The -1 is linux standard. # I don't much like it but it is the mode nowadays. So linuxbios will change # what a mess. -- RGM # catch the case where there is no compression 32d61 < makedefine PAYLOAD-$(CONFIG_COMPRESSED_ROM_STREAM):=payload.nrv2b 34c63,81 < makerule linuxbios.rom
# match the case where a compression type is specified. makedefine PAYLOAD-$(CONFIG_COMPRESSED_PAYLOAD_NRV2B):=payload.nrv2b makedefine PAYLOAD-$(CONFIG_COMPRESSED_PAYLOAD_LZMA):=payload.lzma
# catch the case where there is precompression. Yes, this bites. if CONFIG_PRECOMPRESSED_PAYLOAD makedefine PAYLOAD-1:=payload end
if USE_FAILOVER_IMAGE makedefine LINUXBIOS_APC:= makedefine LINUXBIOS_RAM_ROM:=
makerule linuxbios.rom depends "linuxbios.strip" action "cp $< $@" end else makerule linuxbios.rom 36a84 end 54c102 < depends "crt0.o init.o linuxbios_ram.rom ldscript.ld"
depends "crt0.o init.o $(LINUXBIOS_APC) $(LINUXBIOS_RAM_ROM) ldscript.ld"
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/i386/include/arch/acpi.h LinuxBIOSv2/src/arch/i386/include/arch/acpi.h 9c9,10 < * ACPI FADT & FACS added by Nick Barker <nick.barker9@btinternet.com> ---
*/ /* ACPI FADT & FACS added by Nick Barker <nick.barker9@btinternet.com> 11,14d11 < * < * ACPI SRAT support added in 2005.9 by yhlu < * Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. < * 34a32 #define SLIT_NAME "SLIT" 39a38 #define SLIT_TABLE "SLIT " 52c51 < u32 length; /* total length of RSDP (incl. extended part) */
u32 length; /* total length of RSDP (including extended part) */ 87c86 < u32 entry[5+ACPI_SSDTX_NUM]; /* HPET, FADT, SRAT, MADT(APIC), SSDT, SSDTX */
u32 entry[6+ACPI_SSDTX_NUM]; /* HPET, FADT, SRAT, SLIT, MADT(APIC), SSDT, SSDTX*/ 93c92 < u64 entry[5+ACPI_SSDTX_NUM];
u64 entry[6+ACPI_SSDTX_NUM]; 140a139,143 /* SLIT */ typedef struct acpi_slit { struct acpi_table_header header; /* followed by static resource allocation 8+byte[num*num]*/ } __attribute__ ((packed)) acpi_slit_t; diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/i386/include/arch/cpu.h LinuxBIOSv2/src/arch/i386/include/arch/cpu.h 143a144,162
struct cpuinfo_x86 { uint8_t x86; /* CPU family */ uint8_t x86_vendor; /* CPU vendor */ uint8_t x86_model; uint8_t x86_mask; };
static void inline get_fms(struct cpuinfo_x86 *c, uint32_t tfms) { c->x86 = (tfms >> 8) & 0xf; c->x86_model = (tfms >> 4) & 0xf; c->x86_mask = tfms & 0xf; if (c->x86 == 0xf) c->x86 += (tfms >> 20) & 0xff; if (c->x86 >= 0x6) c->x86_model += ((tfms >> 16) & 0xF) << 4;
} Only in LinuxBIOSv2/src/arch/i386/include/arch: mmio_conf.h diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/i386/include/arch/pciconf.h LinuxBIOSv2/src/arch/i386/include/arch/pciconf.h 6a7,8
#if PCI_IO_CFG_EXT == 0 7a10,12 #else #define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where & 0xff) | ((where & 0xf00)<<16) ) #endif diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/i386/include/arch/pci_ops.h LinuxBIOSv2/src/arch/i386/include/arch/pci_ops.h 6a7,10 #if MMCONF_SUPPORT==1 const struct pci_bus_operations pci_ops_mmconf; #endif
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/i386/include/arch/romcc_io.h LinuxBIOSv2/src/arch/i386/include/arch/romcc_io.h 7c7 < static inline uint8_t read8(unsigned long addr) ---
static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr) 12c12 < static inline uint16_t read16(unsigned long addr)
static inline __attribute__((always_inline)) uint16_t read16(unsigned long addr) 17c17 < static inline uint32_t read32(unsigned long addr)
static inline __attribute__((always_inline)) uint32_t read32(unsigned long addr) 22c22 < static inline void write8(unsigned long addr, uint8_t value)
static inline __attribute__((always_inline)) void write8(unsigned long addr, uint8_t value) 27c27 < static inline void write16(unsigned long addr, uint16_t value)
static inline __attribute__((always_inline)) void write16(unsigned long addr, uint16_t value) 32c32 < static inline void write32(unsigned long addr, uint32_t value)
static inline __attribute__((always_inline)) void write32(unsigned long addr, uint32_t value) 36,40d35 < #if 0 < typedef __builtin_div_t div_t; < typedef __builtin_ldiv_t ldiv_t; < typedef __builtin_udiv_t udiv_t; < typedef __builtin_uldiv_t uldiv_t; 42,45c37 < static inline div_t div(int numer, int denom) < { < return __builtin_div(numer, denom); < }
#if MMCONF_SUPPORT 47,55c39 < static inline ldiv_t ldiv(long numer, long denom) < { < return __builtin_ldiv(numer, denom); < } < < static inline udiv_t udiv(unsigned numer, unsigned denom) < { < return __builtin_udiv(numer, denom); < }
#include <arch/mmio_conf.h> 57,73d40 < static inline uldiv_t uldiv(unsigned long numer, unsigned long denom) < { < return __builtin_uldiv(numer, denom); < } < < < < inline int log2(int value) < { < /* __builtin_bsr is a exactly equivalent to the x86 machine < * instruction with the exception that it returns -1 < * when the value presented to it is zero. < * Otherwise __builtin_bsr returns the zero based index of < * the highest bit set. < */ < return __builtin_bsr(value); < } 101,110c68,77 < #define PCI_ADDR(BUS, DEV, FN, WHERE) ( \ < (((BUS) & 0xFF) << 16) | \ < (((DEV) & 0x1f) << 11) | \ < (((FN) & 0x07) << 8) | \ < ((WHERE) & 0xFF)) < < #define PCI_DEV(BUS, DEV, FN) ( \ < (((BUS) & 0xFF) << 16) | \ < (((DEV) & 0x1f) << 11) | \ < (((FN) & 0x7) << 8))
#define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \ (((SEGBUS) & 0xFFF) << 20) | \ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x07) << 12) | \ ((WHERE) & 0xFFF))
#define PCI_DEV(SEGBUS, DEV, FN) ( \ (((SEGBUS) & 0xFFF) << 20) | \ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x07) << 12)) 118c85 < typedef unsigned device_t;
typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */ 120c87,92 < static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where)
/* FIXME: We need to make the LinuxBIOS to run at 64bit mode, So when read/write memory above 4G, * We don't need to set %fs, and %gs anymore * Before that We need to use %gs, and leave %fs to other RAM access */
static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where) 123c95,99 < addr = dev | where;
#if PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; #else addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0 #endif 128c104,105 < static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where)
#if MMCONF_SUPPORT static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where) 131a109,128 return read8x(addr); } #endif static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where) { #if MMCONF_SUPPORT return pci_mmio_read_config8(dev, where); #else return pci_io_read_config8(dev, where); #endif }
static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where) { unsigned addr; #if PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; #else addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); #endif 136c133,134 < static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where)
#if MMCONF_SUPPORT static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where) 139a138,159 return read16x(addr); } #endif
static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where) { #if MMCONF_SUPPORT return pci_mmio_read_config16(dev, where); #else return pci_io_read_config16(dev, where); #endif }
static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where) { unsigned addr; #if PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; #else addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); #endif 144c164,165 < static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value)
#if MMCONF_SUPPORT static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where) 147a169,189 return read32x(addr); } #endif
static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where) { #if MMCONF_SUPPORT return pci_mmio_read_config32(dev, where); #else return pci_io_read_config32(dev, where); #endif }
static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) { unsigned addr; #if PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; #else addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); #endif 152c194,195 < static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value)
#if MMCONF_SUPPORT static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value) 155a199,220 write8x(addr, value); } #endif
static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value) { #if MMCONF_SUPPORT pci_mmio_write_config8(dev, where, value); #else pci_io_write_config8(dev, where, value); #endif }
static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) { unsigned addr; #if PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; #else addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); #endif 160c225,226 < static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value)
#if MMCONF_SUPPORT static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value) 163a230,251 write16x(addr, value); } #endif
static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value) { #if MMCONF_SUPPORT pci_mmio_write_config16(dev, where, value); #else pci_io_write_config16(dev, where, value); #endif }
static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value) { unsigned addr; #if PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; #else addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); #endif 167a256,273 #if MMCONF_SUPPORT static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value) { unsigned addr; addr = dev | where; write32x(addr, value); } #endif
static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value) { #if MMCONF_SUPPORT pci_mmio_write_config32(dev, where, value); #else pci_io_write_config32(dev, where, value); #endif }
168a275,286
static device_t pci_io_locate_device(unsigned pci_id, device_t dev) { for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { unsigned int id; id = pci_io_read_config32(dev, 0); if (id == pci_id) { return dev; } } return PCI_DEV_INVALID; }
171c289 < for(; dev <= PCI_DEV(CONFIG_MAX_PCI_BUSES, 31, 7); dev += PCI_DEV(0,0,1)) { ---
for(; dev <= PCI_DEV(255|(((1<<PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) { Only in LinuxBIOSv2/src/arch/i386/init: ldscript_apc.lb Only in LinuxBIOSv2/src/arch/i386/init: ldscript_failover.lb Only in LinuxBIOSv2/src/arch/i386/init: ldscript_fallback.lb diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/i386/init/ldscript.lb LinuxBIOSv2/src/arch/i386/init/ldscript.lb 46,48d45 < _x = .; < . = (_x < (_ROMBASE - 0x10000 + ROM_IMAGE_SIZE)) ? (_ROMBASE - 0x10000 + ROM_IMAGE_SIZE) : _x; < diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/i386/lib/Config.lb LinuxBIOSv2/src/arch/i386/lib/Config.lb 1a2 uses CONFIG_USE_PRINTK_IN_CAR 6a8 object pci_ops_mmconf.c 10a13 if CONFIG_USE_PRINTK_IN_CAR 11a15 end diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/i386/lib/console.c LinuxBIOSv2/src/arch/i386/lib/console.c 3c3 < #if CONFIG_USE_INIT == 0
#if CONFIG_USE_PRINTK_IN_CAR == 0 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/i386/lib/cpu.c LinuxBIOSv2/src/arch/i386/lib/cpu.c 224a225,226 struct cpuinfo_x86 c;
248a251,255
get_fms(&c, cpu->device);
printk_debug("CPU: family %02x, model %02x, stepping %02x\n", c.x86, c.x86_model, c.x86_mask);
Only in LinuxBIOSv2/src/arch/i386/lib: failover_failover.lds diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/i386/lib/failover.lds LinuxBIOSv2/src/arch/i386/lib/failover.lds 1c1 < __normal_image = (CONFIG_ROM_STREAM_START & 0xfffffff0) - 8; ---
__normal_image = (CONFIG_ROM_PAYLOAD_START & 0xfffffff0) - 8; diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/i386/lib/pci_ops_conf1.c LinuxBIOSv2/src/arch/i386/lib/pci_ops_conf1.c 10a11 #if PCI_IO_CFG_EXT == 0 11a13,15 #else #define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | ((where & 0xff) & ~3) | ((where & 0xf00)<<16) ) #endif 13c17 < static uint8_t pci_conf1_read_config8(struct bus *pbus, unsigned char bus, int devfn, int where)
static uint8_t pci_conf1_read_config8(struct bus *pbus, int bus, int devfn, int where) 15,16d18 < uint8_t t; < 18,22c20 < t = inb(0xCFC + (where & 3)); < < printk_spew("[rc8 %lx %x]\r\n",CONFIG_CMD(bus, devfn, where),t); < < return t;
return inb(0xCFC + (where & 3));
25c23 < static uint16_t pci_conf1_read_config16(struct bus *pbus, unsigned char bus, int devfn, int where) ---
static uint16_t pci_conf1_read_config16(struct bus *pbus, int bus, int devfn, int where) 27d24 < uint16_t t; 29,33c26 < t = inw(0xCFC + (where & 2)); < < printk_spew("[rc16 %lx %x]\r\n",CONFIG_CMD(bus, devfn, where),t); < < return t;
return inw(0xCFC + (where & 2));
36c29 < static uint32_t pci_conf1_read_config32(struct bus *pbus, unsigned char bus, int devfn, int where) ---
static uint32_t pci_conf1_read_config32(struct bus *pbus, int bus, int devfn, int where) 38,39d30 < uint32_t t; < 41,45c32 < t = inl(0xCFC); < < printk_spew("[rc32 %lx %lx]\r\n",CONFIG_CMD(bus, devfn, where),t); < < return t;
return inl(0xCFC);
48c35 < static void pci_conf1_write_config8(struct bus *pbus, unsigned char bus, int devfn, int where, uint8_t value) ---
static void pci_conf1_write_config8(struct bus *pbus, int bus, int devfn, int where, uint8_t value) 52,53d38 < < printk_spew("[wc8 %lx %x]\r\n",CONFIG_CMD(bus, devfn, where),value); 56c41 < static void pci_conf1_write_config16(struct bus *pbus, unsigned char bus, int devfn, int where, uint16_t value)
static void pci_conf1_write_config16(struct bus *pbus, int bus, int devfn, int where, uint16_t value) 60,61d44 < < printk_spew("[wc16 %lx %x]\r\n",CONFIG_CMD(bus, devfn, where),value); 64c47 < static void pci_conf1_write_config32(struct bus *pbus, unsigned char bus, int devfn, int where, uint32_t value)
static void pci_conf1_write_config32(struct bus *pbus, int bus, int devfn, int where, uint32_t value) 68,69d50 < < printk_spew("[wc32 %lx %lx]\r\n",CONFIG_CMD(bus, devfn, where),value); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/i386/lib/pci_ops_conf2.c LinuxBIOSv2/src/arch/i386/lib/pci_ops_conf2.c 15c15 < static uint8_t pci_conf2_read_config8(struct bus *pbus, unsigned char bus, int devfn, int where)
static uint8_t pci_conf2_read_config8(struct bus *pbus, int bus, int devfn, int where) 24c24 < static uint16_t pci_conf2_read_config16(struct bus *pbus, unsigned char bus, int devfn, int where)
static uint16_t pci_conf2_read_config16(struct bus *pbus, int bus, int devfn, int where) 33c33 < static uint32_t pci_conf2_read_config32(struct bus *pbus, unsigned char bus, int devfn, int where)
static uint32_t pci_conf2_read_config32(struct bus *pbus, int bus, int devfn, int where) 42c42 < static void pci_conf2_write_config8(struct bus *pbus, unsigned char bus, int devfn, int where, uint8_t value)
static void pci_conf2_write_config8(struct bus *pbus, int bus, int devfn, int where, uint8_t value) 49c49 < static void pci_conf2_write_config16(struct bus *pbus, unsigned char bus, int devfn, int where, uint16_t value)
static void pci_conf2_write_config16(struct bus *pbus, int bus, int devfn, int where, uint16_t value) 56c56 < static void pci_conf2_write_config32(struct bus *pbus, unsigned char bus, int devfn, int where, uint32_t value)
static void pci_conf2_write_config32(struct bus *pbus, int bus, int devfn, int where, uint32_t value) Only in LinuxBIOSv2/src/arch/i386/lib: pci_ops_mmconf.c diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/ppc/include/ppc.h LinuxBIOSv2/src/arch/ppc/include/ppc.h 1,2c1,18 < /* Copyright 2000 AG Electronics Ltd. */ < /* This code is distributed without warranty under the GPL v2 (see COPYING) */
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 2000 AG Electronics Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/ppc/include/ppcreg.h LinuxBIOSv2/src/arch/ppc/include/ppcreg.h 1,2c1,18 < /* Copyright 2000 AG Electronics Ltd. */ < /* This code is distributed without warranty under the GPL v2 (see COPYING) */
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 2000 AG Electronics Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/ppc/include/timer.h LinuxBIOSv2/src/arch/ppc/include/timer.h 1,2c1,18 < /* Copyright 2000 AG Electronics Ltd. */ < /* This code is distributed without warranty under the GPL v2 (see COPYING) */
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 2000 AG Electronics Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/ppc/lib/cpuid.c LinuxBIOSv2/src/arch/ppc/lib/cpuid.c 1,2c1,18 < /* Copyright 2000 AG Electronics Ltd. */ < /* This code is distributed without warranty under the GPL v2 (see COPYING) */
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 2000 AG Electronics Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/ppc/lib/c_start.S LinuxBIOSv2/src/arch/ppc/lib/c_start.S 1,2c1,18 < /* Copyright 2000 AG Electronics Ltd. */ < /* This code is distributed without warranty under the GPL v2 (see COPYING) */
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 2000 AG Electronics Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/ppc/lib/floats.inc LinuxBIOSv2/src/arch/ppc/lib/floats.inc 1,2c1,18 < /* Copyright 1999-2000 AG Electronics Ltd. */ < /* This code is distributed without warranty under the GPL v2 (see COPYING) */
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 1999-2000 AG Electronics Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/ppc/lib/floats.S LinuxBIOSv2/src/arch/ppc/lib/floats.S 1,2c1,18 < /* Copyright 1999-2000 AG Electronics Ltd. */ < /* This code is distributed without warranty under the GPL v2 (see COPYING) */
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 1999-2000 AG Electronics Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/ppc/lib/ppc.c LinuxBIOSv2/src/arch/ppc/lib/ppc.c 1,2c1,18 < /* Copyright 2000 AG Electronics Ltd. */ < /* This code is distributed without warranty under the GPL v2 (see COPYING) */
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 2000 AG Electronics Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/arch/ppc/lib/timer.c LinuxBIOSv2/src/arch/ppc/lib/timer.c 1,2c1,18 < /* Copyright 2000 AG Electronics Ltd. */ < /* This code is distributed without warranty under the GPL v2 (see COPYING) */
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 2000 AG Electronics Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/boot/Config.lb LinuxBIOSv2/src/boot/Config.lb 3c3 < if CONFIG_FS_STREAM
if CONFIG_FS_PAYLOAD diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/boot/elfboot.c LinuxBIOSv2/src/boot/elfboot.c 633c633 < printk_debug("Found ELF candiate at offset %d\n", i);
printk_debug("Found ELF candidate at offset %d\n", i);
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/boot/hardwaremain.c LinuxBIOSv2/src/boot/hardwaremain.c 91c91 < #if CONFIG_FS_STREAM == 1 ---
#if CONFIG_FS_PAYLOAD == 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/config/Config.lb LinuxBIOSv2/src/config/Config.lb 3a4 uses CONFIG_AP_CODE_IN_CAR 33a35,40 makerule linuxbios.a depends "$(OBJECTS)" action "rm -f linuxbios.a" action "ar cr linuxbios.a $(OBJECTS)" end
65a73,121
makedefine LINUXBIOS_APC:=
if CONFIG_AP_CODE_IN_CAR #for ap code in cache
makerule linuxbios_apc.a depends "apc_auto.o" action "rm -f linuxbios_apc.a" action "ar cr linuxbios_apc.a apc_auto.o" end
makerule linuxbios_apc.o depends "linuxbios_apc.a c_start.o $(LIBGCC_FILE_NAME)" action "$(CC) -nostdlib -r -o $@ c_start.o linuxbios_apc.a $(LIBGCC_FILE_NAME)" end
makerule linuxbios_apc depends "linuxbios_apc.o $(TOP)/src/config/linuxbios_apc.ld ldoptions" action "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_apc.ld linuxbios_apc.o" action "$(CROSS_COMPILE)nm -n linuxbios_apc | sort > linuxbios_apc.map" end
## ## By default compress the part of linuxbios that runs from cache as ram ## makedefine LINUXBIOS_APC-$(CONFIG_COMPRESS):=linuxbios_apc.nrv2b makedefine LINUXBIOS_APC-$(CONFIG_UNCOMPRESSED):=linuxbios_apc.bin
makerule linuxbios_apc.bin depends "linuxbios_apc" action "$(OBJCOPY) -O binary $< $@" end
makerule linuxbios_apc.nrv2b depends "linuxbios_apc.bin nrv2b" action "./nrv2b e $< $@" end
makerule linuxbios_apc.rom depends "$(LINUXBIOS_APC-1)" action "cp $(LINUXBIOS_APC-1) linuxbios_apc.rom" end
makedefine LINUXBIOS_APC:=linuxbios_apc.rom
end
makedefine LINUXBIOS_RAM_ROM:=linuxbios_ram.rom
67c123 < depends "crt0.o $(INIT-OBJECTS) linuxbios_ram.rom ldscript.ld" ---
depends "crt0.o $(INIT-OBJECTS) $(LINUXBIOS_APC) $(LINUXBIOS_RAM_ROM) ldscript.ld" 72,77d127 < makerule linuxbios.a < depends "$(OBJECTS)" < action "rm -f linuxbios.a" < action "ar cr linuxbios.a $(OBJECTS)" < end < 162c212 < action "rm -f docipl buildrom* chips.c *chip.c linuxbios_ram* linuxbios_pay*"
action "rm -f docipl buildrom* chips.c *chip.c linuxbios_apc* linuxbios_ram* linuxbios_pay*" Only in LinuxBIOSv2/src/config: linuxbios_apc.ld diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/config/linuxbios_ram.ld LinuxBIOSv2/src/config/linuxbios_ram.ld 112c112 < _bogus = ASSERT( ((_eram_seg>>10)<CONFIG_LB_MEM_TOPK) , "please increase CONFIG_LB_MEM_TOPK");
_bogus = ASSERT( ( (_eram_seg>>10) < (CONFIG_LB_MEM_TOPK)) , "please increase CONFIG_LB_MEM_TOPK"); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/config/Options.lb LinuxBIOSv2/src/config/Options.lb 180a181,186 define HAVE_FAILOVER_BOOT format "%d" default 0 export always comment "Set if failover booting required" end 186a193,198 define USE_FAILOVER_IMAGE format "%d" default 0 export used comment "Set to build a failover image" end 192a205,210 define FAILOVER_SIZE default 0 format "0x%x" export used comment "Default failover image size" end 277c295 < default none
default 0xc0000 279c297 < export used
export always 293a312,326 define CONFIG_AP_CODE_IN_CAR default 0 export always comment "will copy linuxbios_apc to AP cache ane execute in AP" end define MEM_TRAIN_SEQ default 0 export always comment "0: three for in bsp, 1: on every core0, 2: one for on bsp" end define WAIT_BEFORE_CPUS_INIT default 0 export always comment "execute cpus_ready_for_init if it is set to 1" end 455a489,495 define CONFIG_USE_PRINTK_IN_CAR default 0 export always comment "use printk instead of print in CAR stage code" end
556c596 < define CONFIG_IDE_STREAM ---
define CONFIG_IDE_PAYLOAD 561c601 < define CONFIG_ROM_STREAM
define CONFIG_ROM_PAYLOAD 566c606 < define CONFIG_ROM_STREAM_START
define CONFIG_ROM_PAYLOAD_START 572c612 < define CONFIG_COMPRESSED_ROM_STREAM
define CONFIG_COMPRESSED_PAYLOAD_NRV2B 575c615 < comment "compressed boot image is located in ROM"
comment "NRV2B compressed boot image is located in ROM" 577c617,622 < define CONFIG_PRECOMPRESSED_ROM_STREAM
define CONFIG_COMPRESSED_PAYLOAD_LZMA default 0 export always comment "LZMA compressed boot image is located in ROM" end define CONFIG_PRECOMPRESSED_PAYLOAD 582c627,632 < define CONFIG_FS_STREAM
define CONFIG_SERIAL_PAYLOAD default 0 export always comment "Download boot image from serial port" end define CONFIG_FS_PAYLOAD 703a754,759 define PCI_IO_CFG_EXT default 0 export always comment "allow 4K register space via io CFG port" end
846c902 < comment "first hypertransport device's unitid base. if southbridge ht chain only has one ht device, it could be 0" ---
comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0" 861c917,929 < define K8_SB_HT_CHAIN_ON_BUS0
define SB_HT_CHAIN_ON_BUS0 default 0 export always comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0" end
define PCI_BUS_SEGN_BITS default 0 export always comment "It could be 0, 1, 2, 3 and 4 only" end
define MMCONF_SUPPORT 864c932 < comment "this will make SB hypertransport chain sit on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
comment "enable mmconfig for pci conf" 867c935 < define K8_HW_MEM_HOLE_SIZEK
define HW_MEM_HOLE_SIZEK 873c941 < define K8_HW_MEM_HOLE_SIZE_AUTO_INC
define HW_MEM_HOLE_SIZE_AUTO_INC 884a953,989 define K8_REV_F_SUPPORT default 0 export always comment "Opteron Rev F (DDR2) support" end
define CBB default 0 export always comment "Opteron cpu bus num base" end
define CDB default 0x18 export always comment "Opteron cpu device num base" end
define DIMM_SUPPORT default 0x0108 format "0x%x" export always comment "DIMM support: bit 0 - sdram, bit 1: ddr1, bit 2: ddr2, bit 3: ddr3, bit 4: fbdimm, bit 8: reg" end
define CPU_SOCKET_TYPE default 0x10 export always comment "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3" end
define CPU_ADDR_BITS default 36 export always comment "CPU hardware address lines num, for AMD K8 could be 40, and GH could be 48" end
896a1002,1008
define CONFIG_VIDEO_MB default none export used comment "Integrated graphics with UMA has dynamic setup" end
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/console/Config.lb LinuxBIOSv2/src/console/Config.lb 5a6
uses CONFIG_USE_PRINTK_IN_CAR 26a28 # if CONFIG_USE_PRINTK_IN_CAR 27a30 # end diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/car/cache_as_ram.inc LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 20c20 < #if USE_FALLBACK_IMAGE == 1
#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE==1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE==1)) 59c59 < #else
#endif 61c61,66 < #if CacheSize == 0x8000
#if CacheSize == 0xc000 /* enable caching for 16K using fixed mtrr */ movl $0x268, %ecx /* fix4k_c4000*/ movl $0x06060606, %edx /* WB IO type */ xorl %eax, %eax wrmsr 67d71 < #else 68a73,84 #endif
#if CacheSize == 0x8000 /* enable caching for 32K using fixed mtrr */ movl $0x269, %ecx /* fix4k_c8000*/ movl $0x06060606, %eax /* WB IO type */ movl %eax, %edx wrmsr #endif
#if CacheSize < 0x8000 82,83d97 < #endif < 91c105,106 < #endif /* USE_FALLBACK_IMAGE == 1*/
#endif /* USE_FAILOVER_IMAGE == 1*/
93c108 < #if USE_FALLBACK_IMAGE == 0 ---
#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 0)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE==0)) 111c126 < movl $0x0000000f, %edx /* AMD 40 bit */
movl $((1<<(CPU_ADDR_BITS-32))-1), %edx /* AMD 40 bit */
116c131 < #if USE_FALLBACK_IMAGE == 1 ---
#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE==1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE==1)) 136c151 < #if USE_FALLBACK_IMAGE == 1
#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE==1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE==1)) 142c157,158 < rep lodsl
rep lodsl
147c163,164 < rep stosl ---
rep stosl
149c166 < #endif /*USE_FALLBACK_IMAGE == 1*/ ---
#endif /*USE_FAILOVER_IMAGE == 1*/ 152c169 < movl $(CacheBase+CacheSize - 4 - GlobalVarSize), %eax
movl $(CacheBase+CacheSize - GlobalVarSize), %eax diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/car/copy_and_run.c LinuxBIOSv2/src/cpu/amd/car/copy_and_run.c 8c7 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 49c48,52 < olen = unrv2b(src, dst);
// dump_mem(src, src+0x100);
olen = unrv2b(src, dst, &ilen); print_debug_cp_run("linxbios_ram.nrv2b length = ", ilen);
50a54
// dump_mem(dst, dst+0x100); 63a68,119
#if CONFIG_AP_CODE_IN_CAR == 1
static void copy_and_run_ap_code_in_car(unsigned ret_addr) { uint8_t *src, *dst; unsigned long ilen, olen;
// print_debug("Copying LinuxBIOS AP code to CAR.\r\n");
#if !CONFIG_COMPRESS __asm__ volatile ( "leal _liseg_apc, %0\n\t" "leal _iseg_apc, %1\n\t" "leal _eiseg_apc, %2\n\t" "subl %1, %2\n\t" : "=a" (src), "=b" (dst), "=c" (olen) ); memcpy(dst, src, olen); #else
__asm__ volatile ( "leal _liseg_apc, %0\n\t" "leal _iseg_apc, %1\n\t" : "=a" (src) , "=b" (dst) );
// print_debug_cp_run("src=",(uint32_t)src); // print_debug_cp_run("dst=",(uint32_t)dst);
// dump_mem(src, src+0x100);
olen = unrv2b(src, dst, &ilen); // print_debug_cp_run("linxbios_apc.nrv2b length = ", ilen);
#endif // dump_mem(dst, dst+0x100);
// print_debug_cp_run("linxbios_apc.bin length = ", olen);
// print_debug("Jumping to LinuxBIOS AP code in CAR.\r\n");
__asm__ volatile ( "movl %0, %%ebp\n\t" /* cpu_reset for hardwaremain dummy */ "cli\n\t" "leal _iseg_apc, %%edi\n\t" "jmp *%%edi\n\t" :: "a"(ret_addr) );
} #endif diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/car/disable_cache_as_ram.c LinuxBIOSv2/src/cpu/amd/car/disable_cache_as_ram.c 46d46 < /* be warned, this file will be used core 0 / node 0 and ram stack is ready*/ 51,52c51 < < "pushl %ecx\n\t"
// "pushl %eax\n\t" 54,55c53 < "pushl %eax\n\t" <
"pushl %ecx\n\t"
61,63d57 < < "popl %eax\n\t" < "popl %edx\n\t" 65c59,60 < ---
"popl %edx\n\t" // "popl %eax\n\t"
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/car/post_cache_as_ram.c LinuxBIOSv2/src/cpu/amd/car/post_cache_as_ram.c 10c10 < #if CONFIG_USE_INIT ---
#if CONFIG_USE_PRINTK_IN_CAR 21c21 < "rep movsl\n\t"
"rep; movsl\n\t"
52c53 < set_init_ram_access(); ---
set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_LB_MEM_TOPK) */ 53a55 // dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x8000, DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x7c00); 56a59 #if 0 60c63,67 < memcopy((CONFIG_LB_MEM_TOPK<<10)-DCACHE_RAM_SIZE, DCACHE_RAM_BASE, DCACHE_RAM_SIZE); //inline
#endif
memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-DCACHE_RAM_SIZE), (void *)DCACHE_RAM_BASE, DCACHE_RAM_SIZE); //inline // dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
66a74
#if 0 69a78,80 #endif
80c91 < clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10)), that is used as stack in ram ---
clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10))
82a94,106
// dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
#ifndef MEM_TRAIN_SEQ #define MEM_TRAIN_SEQ 0 #endif set_sysinfo_in_ram(1); // So other core0 could start to train mem
#if MEM_TRAIN_SEQ == 1 // struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
// wait for ap memory to trained // wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c #endif diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/dualcore/amd_sibling.c LinuxBIOSv2/src/cpu/amd/dualcore/amd_sibling.c 13a14 #include <cpu/amd/amdk8_sysconf.h> 170a172,180 if(id.nodeid == 0) { // need some special processing, because may the bsp is not lifted, but the core1 is lifted //defined in northbridge.c if(sysconf.enabled_apic_ext_id && (!sysconf.lift_bsp_apicid)) { cpu->path.u.apic.apic_id += sysconf.apicid_offset; }
}
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/dualcore/dualcore.c LinuxBIOSv2/src/cpu/amd/dualcore/dualcore.c 21a22
#if K8_REV_F_SUPPORT == 0 22a24 #endif diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/dualcore/dualcore_id.c LinuxBIOSv2/src/cpu/amd/dualcore/dualcore_id.c 22a23,24 #define CORE_ID_BIT 1 #define NODE_ID_BIT 3 30,31c32,33 < id.nodeid = (id.coreid>>1); < id.coreid &= 1;
id.nodeid = (id.coreid>>CORE_ID_BIT); id.coreid &= ((1<<CORE_ID_BIT)-1);
37,38c39,40 < id.coreid = (id.nodeid>>3); < id.nodeid &= 7; ---
id.coreid = (id.nodeid>>NODE_ID_BIT); id.nodeid &= ((1<<NODE_ID_BIT)-1);
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/model_fxx/Config.lb LinuxBIOSv2/src/cpu/amd/model_fxx/Config.lb 2a3,4
uses CPU_ADDR_BITS
4a7
default CPU_ADDR_BITS=40 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/model_fxx/fidvid.c LinuxBIOSv2/src/cpu/amd/model_fxx/fidvid.c 4a5,6 #define K8_SET_FIDVID_ONE_BY_ONE 1
6a9,14
#ifndef SB_VFSMAF #define SB_VFSMAF 1 #endif
#define FX_SUPPORT 1
10c18 < #if CONFIG_USE_INIT==1 ---
#if CONFIG_USE_PRINTK_IN_CAR 21c29 < #if CONFIG_USE_INIT==1
#if CONFIG_USE_PRINTK_IN_CAR 32c40 < #if CONFIG_USE_INIT==1
#if CONFIG_USE_PRINTK_IN_CAR 62c70 < dword = 0x23070000; //enable FID/VID change
dword = 0x23070700; //enable FID/VID change
71a80,98
#if K8_SET_FIDVID_ONE_BY_ONE == 0 static unsigned set_fidvid_without_init(unsigned fidvid) {
msr_t msr; uint32_t vid; uint32_t fid;
fid = (fidvid >> 8) & 0x3f; vid = (fidvid >> 16) & 0x3f;
// set new FID/VID msr.hi = 1; msr.lo = (vid<<8) | fid; wrmsr(0xc0010041, msr); return fidvid; } #endif
106c133 < #if CONFIG_USE_INIT == 1 ---
#if CONFIG_USE_PRINTK_IN_CAR 125c152,160 < fid_max = (msr.lo>>16) & 0x3f;
fid_max = ((msr.lo>>16) & 0x3f); //max fid #if FX_SUPPORT if(fid_max>=((25-4)*2)) { // FX max fid is 5G fid_max = ((msr.lo>>8) & 0x3f) + 5*2; // max FID is min fid + 1G if(fid_max >= ((25-4)*2)) { fid_max = (10-4)*2; // hard set to 2G } } #endif
129a165
#if SB_VFSMAF == 1 130a167 #endif 131a169,172 #if SB_VFSMAF == 0 ldtstop_sb(); #endif
161a203
#if SB_VFSMAF == 1 162a205 #endif 163a207,209 #if SB_VFSMAF == 0 ldtstop_sb(); #endif 188a235 #if SB_VFSMAF == 1 189a237 #endif 190a239,241 #if SB_VFSMAF == 0 ldtstop_sb(); #endif 201,202c252,256 < if((fid!=fid_cur) || (vid!=vid_cur)) { < print_err("set fidvid failed\r\n");
if(vid!=vid_cur) { print_err("set vid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n"); } if(fid!=fid_cur) { print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n");
214c268,269 < uint32_t readback; ---
uint32_t readback = 0; unsigned timeout = 1;
217a273
uint32_t fid_max; 221c277,287 < send = ((msr.lo>>16) & 0x3f) << 8; //max fid
fid_max = ((msr.lo>>16) & 0x3f); //max fid #if FX_SUPPORT if(fid_max>=((25-4)*2)) { // FX max fid is 5G fid_max = ((msr.lo>>8) & 0x3f) + 5*2; // max FID is min fid + 1G if(fid_max >= ((25-4)*2)) { fid_max = (10-4)*2; // hard set to 2G } } #endif send = fid_max<<8;
224a291
#if K8_SET_FIDVID_ONE_BY_ONE == 1 231a299 #endif 233c301,304 < wait_cpu_state(bsp_apicid, 1);
timeout = wait_cpu_state(bsp_apicid, 1); if(timeout) { print_initcpu8("fidvid_ap_stage1: time out while reading from BSP on ", apicid); } 238c309 < loop = 100000;
loop = 1000000; 245a317 #if K8_SET_FIDVID_ONE_BY_ONE == 1 246a319,321 #else readback = set_fidvid_without_init(readback & 0xffff00); // this AP #endif 248a324,325 } else { print_initcpu8("fidvid_ap_stage2: time out while reading from BSP on ", apicid); 253c330,333 < wait_cpu_state(bsp_apicid, 3);
timeout = wait_cpu_state(bsp_apicid, 3); if(timeout) { print_initcpu8("fidvid_ap_stage3: time out while reading from BSP on ", apicid); } 273c353,354 < unsigned readback;
unsigned readback = 0; unsigned timeout = 1;
280c361 < loop = 100000; ---
loop = 1000000;
283c364,371 < if((readback & 0xff) == 1) break; //target ap is in stage 1 ---
if((readback & 0xff) == 1) { timeout = 0; break; //target ap is in stage 1 } } if(timeout) { print_initcpu8("fidvid_bsp_stage1: time out while reading from ap ", ap_apicid); return;
295c383,384 < unsigned readback; ---
unsigned readback = 0; unsigned timeout = 1;
304c393 < loop = 100000; ---
loop = 1000000;
307c396,404 < if((readback & 0xff) == 2) break; // target ap is stage 2, and it'd FID has beed set ---
if((readback & 0xff) == 2) { timeout = 0; break; // target ap is stage 2, and it'd FID has beed set } }
if(timeout) { print_initcpu8("fidvid_bsp_stage2: time out while reading from ap ", ap_apicid); return;
344a442,449
#if FX_SUPPORT == 1 if(fid_max>=((25-4)*2)) { // FX max fid is 5G fid_max = ((msr.lo>>8) & 0x3f) + 5*2; // max FID is min fid + 1G if(fid_max >= ((25-4)*2)) { fid_max = (10-4)*2; // hard set to 2G } } #endif 368a474,497 #if 0 unsigned fid, vid; // Can we use max only? So we can only set fid in one around, otherwise we need to set that to max after raminit // set fid vid to DQS training required fid = (fv.common_fidvid >> 8) & 0x3f; vid = (fv.common_fidvid >> 16) & 0x3f;
if(fid>(10-4)*2) { fid = (10-4)*2; //x10 }
if(vid>=0x1f) { vid+= 4; //unit is 12.5mV } else { vid+= 2; //unit is 25mV }
fv.common_fidvid = (fid<<8) | (vid<<16);
print_debug_fv("common_fidvid=", fv.common_fidvid);
#endif
#if K8_SET_FIDVID_ONE_BY_ONE == 1 373a503 #endif 389a520,527 #if K8_SET_FIDVID_ONE_BY_ONE == 0 // set BSP fid and vid print_debug_fv("bsp apicid=", bsp_apicid); fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1); print_debug_fv("common_fidvid=", fv.common_fidvid);
#endif
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/model_fxx/init_cpus.c LinuxBIOSv2/src/cpu/amd/model_fxx/init_cpus.c 2a3
#if K8_REV_F_SUPPORT == 0 3a5,9 #else // for rev F, need to set FID to max #define K8_SET_FIDVID 1 #endif
10a17,53
static inline void print_initcpu8 (const char *strval, unsigned val) { #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%02x\r\n", strval, val); #else print_debug(strval); print_debug_hex8(val); print_debug("\r\n"); #endif }
static inline void print_initcpu8_nocr (const char *strval, unsigned val) { #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%02x", strval, val); #else print_debug(strval); print_debug_hex8(val); #endif }
static inline void print_initcpu16 (const char *strval, unsigned val) { #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%04x\r\n", strval, val); #else print_debug(strval); print_debug_hex16(val); print_debug("\r\n"); #endif }
static inline void print_initcpu(const char *strval, unsigned val) { #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%08x\r\n", strval, val); #else print_debug(strval); print_debug_hex32(val); print_debug("\r\n"); #endif }
46a90
#if K8_REV_F_SUPPORT == 0
47a92,94
#else e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 #endif
59a107,109
else { jstart = 0; }
124c174,176 < #if CONFIG_USE_INIT == 0 ---
#if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\r\n", str, apicid, id.nodeid, id.coreid); #else 129,130d180 < #else < printk_debug("%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\r\n", str, apicid, id.nodeid, id.coreid); 135c185 < static void wait_cpu_state(unsigned apicid, unsigned state)
static unsigned wait_cpu_state(unsigned apicid, unsigned state) 137,138c187,189 < unsigned readback; < int loop =100000;
unsigned readback = 0; unsigned timeout = 1; int loop = 2000000;
141c192,200 < if((readback & 0xff) == state) break; //target cpu is in stage started ---
if((readback & 0xff) == state) { timeout = 0; break; //target cpu is in stage started } } if(timeout) { if(readback) { timeout = readback; }
143d201 < } 144a203,204
return timeout; } 147c207,215 < wait_cpu_state(ap_apicid, 0x33); // started
unsigned timeout; timeout = wait_cpu_state(ap_apicid, 0x33); // started if(timeout) { print_initcpu8_nocr("*", ap_apicid); print_initcpu("*", timeout); } else { print_initcpu8_nocr(" ", ap_apicid); } 155c223 < static void wait_all_other_cores_started(unsigned bsp_apicid)
static void wait_all_other_cores_started(unsigned bsp_apicid) // all aps other than core0 156a225 print_debug("started ap apicid: "); 157a227 print_debug("\r\n"); 164a235,248 static void STOP_CAR_AND_CPU(void) { disable_cache_as_ram(); // inline stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp .... }
#ifndef MEM_TRAIN_SEQ #define MEM_TRAIN_SEQ 0 #endif
#if MEM_TRAIN_SEQ == 1 static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall); #endif 246a331,332 unsigned timeout=1; unsigned loop = 100; 255c341,346 < wait_cpu_state(bsp_apicid, 0x44);
while(timeout && (loop-->0)) { timeout = wait_cpu_state(bsp_apicid, 0x44); } if(timeout) { print_initcpu8("while waiting for BSP signal to STOP, timeout in ap ", apicid); }
259,260c349,353 < disable_cache_as_ram(); // inline < stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp .... ---
#if MEM_TRAIN_SEQ == 1 train_ram_on_node(id.nodeid, id.coreid, sysinfo, STOP_CAR_AND_CPU); #endif
STOP_CAR_AND_CPU(); 283a377 print_debug("core0 started: "); 285a380 print_initcpu8_nocr(" ", i); 286a382,383 print_debug("\r\n");
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/model_fxx/model_fxx_init.c LinuxBIOSv2/src/cpu/amd/model_fxx/model_fxx_init.c 15a16
#include <cpu/x86/msr.h> 31a33,43 void cpus_ready_for_init(void) { #if MEM_TRAIN_SEQ == 1 struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // wait for ap memory to trained wait_all_core0_mem_trained(sysinfox); #endif }
#if K8_REV_F_SUPPORT == 0 55a68,79 #endif
#if K8_REV_F_SUPPORT == 1 int is_cpu_f0_in_bsp(int nodeid) { uint32_t dword; device_t dev; dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 3)); dword = pci_read_config32(dev, 0xfc); return (dword & 0xfff00) == 0x40f00; } #endif 268c292,293 < #if K8_HW_MEM_HOLE_SIZEK != 0
#if HW_MEM_HOLE_SIZEK != 0 #if K8_REV_F_SUPPORT == 0 270a296 #endif 276a303 #if K8_REV_F_SUPPORT == 0 277a305 #endif 297c325 < #if K8_HW_MEM_HOLE_SIZEK != 0
#if HW_MEM_HOLE_SIZEK != 0 341a371 #if K8_REV_F_SUPPORT == 0 408a439 #endif 409a441 #if K8_REV_F_SUPPORT == 0 410a443 #endif 422a456,462 #if K8_REV_F_SUPPORT == 1 /* Erratum 131... */ msr = rdmsr(NB_CFG_MSR); msr.lo |= 1 << 20; wrmsr(NB_CFG_MSR, msr); #endif
424a465,544
#if K8_REV_F_SUPPORT == 1 static void amd_set_name_string_f(device_t dev) { unsigned socket; unsigned cmpCap; unsigned pwrLmt; unsigned brandId; unsigned brandTableIndex; unsigned nN; unsigned unknown = 1;
uint8_t str[48]; uint32_t *p;
msr_t msr; unsigned i;
brandId = cpuid_ebx(0x80000001) & 0xffff;
printk_debug("brandId=%04x\n", brandId); pwrLmt = ((brandId>>14) & 1) | ((brandId>>5) & 0x0e); brandTableIndex = (brandId>>9) & 0x1f; nN = (brandId & 0x3f) | ((brandId>>(15-6)) &(1<<6));
socket = (dev->device >> 4) & 0x3;
cmpCap = cpuid_ecx(0x80000008) & 0xff;
if((brandTableIndex == 0) && (pwrLmt == 0)) { memset(str, 0, 48); sprintf(str, "AMD Engineering Sample"); unknown = 0; } else {
memset(str, 0, 48); sprintf(str, "AMD Processor model unknown");
#if CPU_SOCKET_TYPE == 0x10 if(socket == 0x01) { // socket F if ((cmpCap == 1) && ((brandTableIndex==0) ||(brandTableIndex ==1) ||(brandTableIndex == 4)) ) { uint8_t pc[2]; unknown = 0; switch (pwrLmt) { case 2: pc[0]= 'E'; pc[1] = 'E'; break; case 6: pc[0]= 'H'; pc[1] = 'E'; break; case 0xa: pc[0]= ' '; pc[1] = ' '; break; case 0xc: pc[0]= 'S'; pc[1] = 'E'; break; default: unknown = 1;
} if(!unknown) { memset(str, 0, 48); sprintf(str, "Dual-Core AMD Opteron(tm) Processor %1d2%2d %c%c", brandTableIndex<<1, (nN-1)&0x3f, pc[0], pc[1]); } } } #else #if CPU_SOCKET_TYPE == 0x11 if(socket == 0x00) { // socket AM2 if(cmpCap == 0) { sprintf(str, "Athlon 64"); } else { sprintf(str, "Athlon 64 Dual Core"); }
} #endif #endif }
p = str; for(i=0;i<6;i++) { msr.lo = *p; p++; msr.hi = *p; p++; wrmsr(0xc0010030+i, msr); }
} #endif 437a558,567 #if K8_REV_F_SUPPORT == 1 struct cpuinfo_x86 c;
get_fms(&c, dev->device);
if((c.x86_model & 0xf0) == 0x40) { amd_set_name_string_f(dev); } #endif
506a637
#if K8_REV_F_SUPPORT == 0 542a674,695 #endif
#if K8_REV_F_SUPPORT == 1 //AMD_F0_SUPPORT { X86_VENDOR_AMD, 0x40f50 }, /* SH-F0 Socket F (1207): Opteron */ { X86_VENDOR_AMD, 0x40f70 }, /* AM2: Athlon64/Athlon64 FX */ { X86_VENDOR_AMD, 0x40f40 }, /* S1g1: Mobile Athlon64 */ { X86_VENDOR_AMD, 0x40f11 }, /* JH-F1 Socket F (1207): Opteron Dual Core */ { X86_VENDOR_AMD, 0x40f31 }, /* AM2: Athlon64 x2/Athlon64 FX Dual Core */ { X86_VENDOR_AMD, 0x40f01 }, /* S1g1: Mobile Athlon64 */ { X86_VENDOR_AMD, 0x40f12 }, /* JH-F2 Socket F (1207): Opteron Dual Core */ { X86_VENDOR_AMD, 0x40f32 }, /* AM2 : Opteron Dual Core/Athlon64 x2/ Athlon64 FX Dual Core */ { X86_VENDOR_AMD, 0x40fb2 }, /* BH-F2 Socket AM2:Athlon64 x2/ Mobile Athlon64 x2 */ { X86_VENDOR_AMD, 0x40f82 }, /* S1g1:Turion64 x2 */ { X86_VENDOR_AMD, 0x40ff2 }, /* DH-F2 Socket AM2: Athlon64 */ { X86_VENDOR_AMD, 0x50ff2 }, /* DH-F2 Socket AM2: Athlon64 */ { X86_VENDOR_AMD, 0x40fc2 }, /* S1g1:Turion64 */ { X86_VENDOR_AMD, 0x40f13 }, /* JH-F3 Socket F (1207): Opteron Dual Core */ { X86_VENDOR_AMD, 0x40f33 }, /* AM2 : Opteron Dual Core/Athlon64 x2/ Athlon64 FX Dual Core */ { X86_VENDOR_AMD, 0xc0f13 }, /* AM2 : Athlon64 FX*/ { X86_VENDOR_AMD, 0x50ff3 }, /* DH-F3 Socket AM2: Athlon64 */ #endif diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/model_fxx/model_fxx_update_microcode.c LinuxBIOSv2/src/cpu/amd/model_fxx/model_fxx_update_microcode.c 55,58c55,63 < #include "microcode_rev_c.h" < #include "microcode_rev_d.h" < #include "microcode_rev_e.h" <
#if K8_REV_F_SUPPORT == 0 #include "microcode_rev_c.h" #include "microcode_rev_d.h" #include "microcode_rev_e.h" #endif
#if K8_REV_F_SUPPORT == 1 // #include "microcode_rev_f.h" #endif 67a73 #if K8_REV_F_SUPPORT == 0 87a94,98 #endif
#if K8_REV_F_SUPPORT == 1
#endif diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/model_gx2/vsmsetup.c LinuxBIOSv2/src/cpu/amd/model_gx2/vsmsetup.c 256a257 unsigned long ilen, olen; 276c277,278 < unrv2b((uint8_t *)rom, buf);
olen = unrv2b((uint8_t *)rom, buf, &ilen); printk_debug("buf ilen %d olen%d\n", ilen, olen); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/model_lx/cpubug.c LinuxBIOSv2/src/cpu/amd/model_lx/cpubug.c 351a352 #if 0 //GX3: any CPU bugs to fix here? :) 354c355 < #if 0 //GX3
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/model_lx/model_lx_init.c LinuxBIOSv2/src/cpu/amd/model_lx/model_lx_init.c 7a8
#include <arch/io.h> 29a31 // do VSA late init 31a34,38 // Set gate A20 (legacy vsm disables it in late init) printk_debug("A20 (0x92): %d\n",inb(0x92)); outb(0x02,0x92); printk_debug("A20 (0x92): %d\n",inb(0x92));
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/model_lx/vsmsetup.c LinuxBIOSv2/src/cpu/amd/model_lx/vsmsetup.c 8a9
#include <cpu/amd/vr.h> 10,13c11 < /* what a mess this uncompress thing is. I am not at all happy about how this < * was done, but can't fix it yet. RGM < */ < #warning "Fix the uncompress once linuxbios knows how to do it"
// andrei: use the /lib copy of nrv2b 15a14,16 #define VSA2_BUFFER 0x60000 #define VSA2_ENTRY_POINT 0x60020
70c71 < * $Id: Exp $ ---
* $Id: vsmsetup.c,v 1.8 2006/09/08 12:47:57 andrei Exp $ 139a141,143 uint16_t entryHi = (VSA2_ENTRY_POINT & 0xffff0000) >> 4; uint16_t entryLo = (VSA2_ENTRY_POINT & 0xffff);
145c149 < " mov %esp, __stack \n" ---
" mov %%esp, __stack \n"
149,150c153,154 < /* get devfn into %ecx */ < " movl %esp, %ebp \n" ---
/* get devfn into %%ecx */ " movl %%esp, %%ebp \n"
155,156c159,160 < " movl 8(%ebp), %ecx \n" < " movl 12(%ebp), %edx \n" ---
" movl 8(%%ebp), %%ecx \n" " movl 12(%%ebp), %%edx \n"
158,159c162,163 < " movl $0x10000026, %ecx \n" < " movl $0x10000028, %edx \n" ---
" movl %0, %%ecx \n" " movl %1, %%edx \n"
162c166 < " lgdt %cs:__mygdtaddr \n" ---
" lgdt %%cs:__mygdtaddr \n"
173,178c177,182 < " mov $0x30, %ax \n" < " mov %ax, %ds \n" < " mov %ax, %es \n" < " mov %ax, %fs \n" < " mov %ax, %gs \n" < " mov %ax, %ss \n" ---
" mov $0x30, %%ax \n" " mov %%ax, %%ds \n" " mov %%ax, %%es \n" " mov %%ax, %%fs \n" " mov %%ax, %%gs \n" " mov %%ax, %%ss \n"
181,183c185,187 < " movl %cr0, %eax \n" < " andl $0xFFFFFFFE, %eax \n" < " movl %eax, %cr0 \n" ---
" movl %%cr0, %%eax \n" " andl $0xFFFFFFFE, %%eax \n" " movl %%eax, %%cr0 \n"
193,196c197,200 < " mov $0x0, %ax \n" < " mov %ax, %ss \n" < " movl $0x1000, %eax \n" < " movl %eax, %esp \n" ---
" mov $0x0, %%ax \n" " mov %%ax, %%ss \n" " movl $0x1000, %%eax \n" " movl %%eax, %%esp \n"
199,200c203,204 < " xor %ax, %ax \n" < " mov %ax, %ds \n" ---
" xor %%ax, %%ax \n" " mov %%ax, %%ds \n"
204c208 < " mov %ax, %es \n" ---
" mov %%ax, %%es \n"
206,212c210,216 < " mov %ax, %fs \n" < " mov %ax, %gs \n" < " mov $0x40, %ax \n" < " mov %ax, %ds \n" < //" mov %cx, %ax \n" < " movl $0x10000026, %ecx \n" < " movl $0x10000028, %edx \n" ---
" mov %%ax, %%fs \n" " mov %%ax, %%gs \n" " mov $0x40, %%ax \n" " mov %%ax, %%ds \n" //" mov %%cx, %%ax \n" " movl %0, %%ecx \n" " movl %1, %%edx \n"
214,215c218,219 < /* run VGA BIOS at 0x6000:0020 */ < " lcall $0x6000, $0x0020\n" ---
/* call the VSA2 entry point address */ " lcall %2, %3\n"
219,221c223,225 < " movl %cr0, %eax \n" < " orl $0x0000001, %eax\n" /* PE = 1 */ < " movl %eax, %cr0 \n" ---
" movl %%cr0, %%eax \n" " orl $0x0000001, %%eax\n" /* PE = 1 */ " movl %%eax, %%cr0 \n"
227,232c231,236 < " movw $0x18, %ax \n" < " mov %ax, %ds \n" < " mov %ax, %es \n" < " mov %ax, %fs \n" < " mov %ax, %gs \n" < " mov %ax, %ss \n" ---
" movw $0x18, %%ax \n" " mov %%ax, %%ds \n" " mov %%ax, %%es \n" " mov %%ax, %%fs \n" " mov %%ax, %%gs \n" " mov %%ax, %%ss \n"
235c239 < " lgdt %cs:gdtarg \n" ---
" lgdt %%cs:gdtarg \n"
240c244 < " mov __stack, %esp \n" ---
" mov __stack, %%esp \n"
242c246 < ); ---
:: "g" (smm), "g" (sysm), "g" (entryHi), "g" (entryLo));
247a252,288
// andrei: some VSA virtual register helpers: raw read and MSR read
uint32_t VSA_vrRead(uint16_t classIndex) { unsigned eax, ebx, ecx, edx; asm volatile(
"movw $0x0AC1C, %%dx \n" "orl $0x0FC530000, %%eax \n" "outl %%eax, %%dx \n" "addb $2, %%dl \n" "inw %%dx, %%ax \n"
: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) : "a" (classIndex) );
return eax; }
uint32_t VSA_msrRead(uint32_t msrAddr) { unsigned eax, ebx, ecx, edx; asm volatile(
"movw $0x0AC1C, %%dx \n" "movl $0x0FC530007, %%eax \n" "outl %%eax, %%dx \n" "addb $2, %%dl \n" "inw %%dx, %%ax \n"
: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) : "c" (msrAddr) );
return eax; } 256a298 unsigned long ilen, olen; 275c317 < rom = 0xfffc0000;
rom = 0xfffc8000; 277,278c319,321 < buf = (unsigned char *) 0x60000; < unrv2b((uint8_t *)rom, buf);
buf = (unsigned char *) VSA2_BUFFER; olen = unrv2b((uint8_t *)rom, buf, &ilen); printk_debug("buf ilen %d olen%d\n", ilen, olen); 291c334 < //memcpy((void *) 0x60000, buf, size);
//memcpy((void *) VSA2_BUFFER, buf, size); 298c341 < real_mode_switch_call_vsm(0x10000026, 0x10000028);
real_mode_switch_call_vsm(MSR_GLIU0_SMM, MSR_GLIU0_SYSMEM); 302a346,350
// check that VSA is running OK if(VSA_vrRead(SIGNATURE) == VSA2_SIGNATURE) printk_debug("do_vsmbios: VSA2 VR signature verified\n"); else printk_err("do_vsmbios: VSA2 VR signature not valid, install failed!\n"); 523c571 < eax = 64 * 1024;
eax = 128 * 1024;
565c613 < codeptr = (char*) 4096 + i * codesize; ---
codeptr = (unsigned char*) 4096 + i * codesize;
578c626 < codeptr = (char*) 0xff065; ---
codeptr = (unsigned char*) 0xff065; 587c635 < memcpy(16384, &debughandle, &end_debughandle - &debughandle);
memcpy((void*)16384, &debughandle, &end_debughandle - &debughandle); 764c812 < *eax=33;
*eax=66;
767c815 < *eax=333; ---
*eax=500;
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/mtrr/amd_earlymtrr.c LinuxBIOSv2/src/cpu/amd/mtrr/amd_earlymtrr.c 18d17 < unsigned long cr0; diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/mtrr/amd_mtrr.c LinuxBIOSv2/src/cpu/amd/mtrr/amd_mtrr.c 152c152 < if(state.tomk>(4*1024*1024)) { ---
if(state.tomk > (4*1024*1024)) { 183c183 < address_bits = 40;
address_bits = CPU_ADDR_BITS; //K8 could be 40, and GH could be 48 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/sc520/sc520.c LinuxBIOSv2/src/cpu/amd/sc520/sc520.c 268c268 < CHIP_NAME("AMD SC520")
CHIP_NAME("AMD Elan SC520 CPU") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/socket_754/socket_754.c LinuxBIOSv2/src/cpu/amd/socket_754/socket_754.c 6c6 < CHIP_NAME("socket 754")
CHIP_NAME("Socket 754 CPU") Only in LinuxBIOSv2/src/cpu/amd: socket_939 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/amd/socket_940/socket_940.c LinuxBIOSv2/src/cpu/amd/socket_940/socket_940.c 5c5 < CHIP_NAME("socket 940")
CHIP_NAME("Socket 940 CPU") Only in LinuxBIOSv2/src/cpu/amd: socket_AM2 Only in LinuxBIOSv2/src/cpu/amd: socket_F diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/emulation/qemu-i386/northbridge.c LinuxBIOSv2/src/cpu/emulation/qemu-i386/northbridge.c 69a70,72 static const uint8_t ramregs[] = { 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 }; 72d74 < uint32_t idx; 78,79c80,103 < /* Hard code the Top of memory for now */ < tomk = 65536;
unsigned char rambits; int i, idx;
for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) { unsigned char reg; reg = pci_read_config8(mc_dev, ramregs[i]); /* these are ENDING addresses, not sizes. * if there is memory in this slot, then reg will be > rambits. * So we just take the max, that gives us total. * We take the highest one to cover for once and future linuxbios * bugs. We warn about bugs. */ if (reg > rambits) rambits = reg; if (reg < rambits) printk_err("ERROR! register 0x%x is not set!\n", ramregs[i]); } if (rambits == 0) { printk_err("RAM size config registers are empty; defaulting to 64 MBytes\n"); rambits = 8; } printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024); tomk = rambits*8*1024;
90,94c113 < ram_resource(dev, idx++, 0, 640); < ram_resource(dev, idx++, 768, tolmk - 768); < if (tomk > 4*1024*1024) { < ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024); < } ---
ram_resource(dev, idx++, 0, tolmk);
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/intel/model_69x/model_69x_init.c LinuxBIOSv2/src/cpu/intel/model_69x/model_69x_init.c 26a27
x86_setup_mtrrs(36); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/intel/model_6dx/model_6dx_init.c LinuxBIOSv2/src/cpu/intel/model_6dx/model_6dx_init.c 26a27 x86_setup_mtrrs(36); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/intel/model_6xx/model_6xx_init.c LinuxBIOSv2/src/cpu/intel/model_6xx/model_6xx_init.c 32a33 x86_setup_mtrrs(36); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/intel/slot_2/slot_2.c LinuxBIOSv2/src/cpu/intel/slot_2/slot_2.c 6c6 < CHIP_NAME("slot 2")
CHIP_NAME("Slot 2 CPU") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/intel/socket_mPGA479M/socket_mPGA479M.c LinuxBIOSv2/src/cpu/intel/socket_mPGA479M/socket_mPGA479M.c 6c6 < CHIP_NAME("socket mPGA479M")
CHIP_NAME("Socket mPGA479M CPU") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c LinuxBIOSv2/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c 6c6 < CHIP_NAME("socket mPGA603_400Mhz")
CHIP_NAME("Socket mPGA603 400Mhz CPU") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/intel/socket_mPGA604_533Mhz/socket_mPGA604_533Mhz.c LinuxBIOSv2/src/cpu/intel/socket_mPGA604_533Mhz/socket_mPGA604_533Mhz.c 6c6 < CHIP_NAME("socket mPGA604_533Mhz")
CHIP_NAME("Socket mPGA604 533Mhz CPU") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/intel/socket_mPGA604_800Mhz/socket_mPGA604_800Mhz.c LinuxBIOSv2/src/cpu/intel/socket_mPGA604_800Mhz/socket_mPGA604_800Mhz.c 6c6 < CHIP_NAME("socket mPGA604_800Mhz")
CHIP_NAME("Socket mPGA604 800Mhz CPU") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/intel/socket_PGA370/socket_PGA370.c LinuxBIOSv2/src/cpu/intel/socket_PGA370/socket_PGA370.c 6c6 < CHIP_NAME("socket PGA370")
CHIP_NAME("Socket PGA370 CPU") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/ppc/mpc74xx/mpc74xx.inc LinuxBIOSv2/src/cpu/ppc/mpc74xx/mpc74xx.inc 1,2c1,18 < /* Copyright 2000 AG Electronics Ltd. */ < /* This code is distributed without warranty under the GPL v2 (see COPYING) */
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 2000 AG Electronics Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/ppc/ppc7xx/ppc7xx.inc LinuxBIOSv2/src/cpu/ppc/ppc7xx/ppc7xx.inc 1,2c1,18 < /* Copyright 2000 AG Electronics Ltd. */ < /* This code is distributed without warranty under the GPL v2 (see COPYING) */
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 2000 AG Electronics Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/x86/car/copy_and_run.c LinuxBIOSv2/src/cpu/x86/car/copy_and_run.c 47c47 < olen=unrv2b(src, dst);
olen = unrv2b(src, dst, &ilen); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/x86/lapic/lapic.c LinuxBIOSv2/src/cpu/x86/lapic/lapic.c 58c58 < printk_debug(" apic_id: %d ", lapicid());
printk_debug(" apic_id: 0x%02x ", lapicid()); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/x86/lapic/lapic_cpu_init.c LinuxBIOSv2/src/cpu/x86/lapic/lapic_cpu_init.c 325c325 < printk_err("CPU %u would not start!\n",
printk_err("CPU 0x%02x would not start!\n",
357c357 < printk_err("CPU %u did not initialize!\n", ---
printk_err("CPU 0x%02x did not initialize!\n",
368a369,372
#if WAIT_BEFORE_CPUS_INIT==0 #define cpus_ready_for_init() do {} while(0) #endif
396a401,402
cpus_ready_for_init();
410d415 < /* start all aps */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/x86/mtrr/earlymtrr.c LinuxBIOSv2/src/cpu/x86/mtrr/earlymtrr.c 50c50,69 < maskm.hi = 0x0f; ---
maskm.hi = (1<<(CPU_ADDR_BITS-32))-1; wrmsr(MTRRphysMask_MSR(reg), maskm); }
static void set_var_mtrr_x( unsigned reg, uint32_t base_lo, uint32_t base_hi, uint32_t size_lo, uint32_t size_hi, unsigned type)
{ /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ msr_t basem, maskm; basem.lo = (base_lo & 0xfffff000) | type; basem.hi = base_hi & ((1<<(CPU_ADDR_BITS-32))-1); wrmsr(MTRRphysBase_MSR(reg), basem); maskm.hi = (1<<(CPU_ADDR_BITS-32))-1; if(size_lo) { maskm.lo = ~(size_lo - 1) | 0x800; } else { maskm.lo = 0x800; maskm.hi &= ~(size_hi - 1); } 73d91 < unsigned long cr0; diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/cpu/x86/mtrr/mtrr.c LinuxBIOSv2/src/cpu/x86/mtrr/mtrr.c 72a73,91 if (reg >= 8) return;
// it is recommended that we disable and enable cache when we // do this. if (sizek == 0) { disable_cache();
msr_t zero; zero.lo = zero.hi = 0; /* The invalid bit is kept in the mask, so we simply clear the relevant mask register to disable a range. */ wrmsr (MTRRphysMask_MSR(reg), zero);
enable_cache(); return; }
89,91d107 < if (reg >= 8) < return; < 95,101c111 < if (sizek == 0) { < msr_t zero; < zero.lo = zero.hi = 0; < /* The invalid bit is kept in the mask, so we simply clear the < relevant mask register to disable a range. */ < wrmsr (MTRRphysMask_MSR(reg), zero); < } else { ---
107c117 < } ---
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/devices/device_util.c LinuxBIOSv2/src/devices/device_util.c 141a142,146
#if PCI_BUS_SEGN_BITS sprintf(buffer, "PCI: %04x:%02x:%02x.%01x", dev->bus->secondary>>8, dev->bus->secondary & 0xff, PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn)); #else 144a150 #endif 433c439,443 < sprintf(buf, "bus %d ", dev->link[0].secondary);
#if PCI_BUS_SEGN_BITS sprintf(buf, "bus %04x:%02x ", dev->bus->secondary>>8, dev->link[0].secondary & 0xff); #else sprintf(buf, "bus %02x ", dev->link[0].secondary); #endif diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/devices/emulator/biosemu.c LinuxBIOSv2/src/devices/emulator/biosemu.c 124a125 ret = 1; diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/devices/hypertransport.c LinuxBIOSv2/src/devices/hypertransport.c 80a80 #if K8_REV_F_SUPPORT == 0 83a84 #endif 562a563,570 unsigned int hypertransport_scan_chain_x(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max) { unsigned ht_unitid_base[4]; unsigned offset_unitid = 1; return hypertransport_scan_chain(bus, min_devfn, max_devfn, max, ht_unitid_base, offset_unitid); }
565c573 < return do_pci_scan_bridge(dev, max, hypertransport_scan_chain); ---
return do_pci_scan_bridge(dev, max, hypertransport_scan_chain_x); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/devices/pci_device.c LinuxBIOSv2/src/devices/pci_device.c 1005c1005,1009 < printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary);
#if PCI_BUS_SEGN_BITS printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n", bus->secondary >> 8, bus->secondary & 0xff); #else printk_debug("PCI: pci_scan_bus for bus %02x\n", bus->secondary); #endif 1063c1067 < printk_debug("PCI: pci_scan_bus returning with max=%02x\n", max);
printk_debug("PCI: pci_scan_bus returning with max=%03x\n", max); 1179c1183 < if (inb(0x4d0) != (intBits & 0xf)) {
if (inb(0x4d0) != (intBits & 0xff)) { 1181c1185 < __func__, intBits &0xf, inb(0x4d0));
__func__, intBits &0xff, inb(0x4d0));
1183c1187 < if (inb(0x4d1) != ((intBits >> 8) & 0xf)) { ---
if (inb(0x4d1) != ((intBits >> 8) & 0xff)) { 1185c1189 < __func__, (intBits>>8) &0xf, inb(0x4d1));
__func__, (intBits>>8) &0xff, inb(0x4d1));
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/drivers/i2c/adm1027/adm1027.c LinuxBIOSv2/src/drivers/i2c/adm1027/adm1027.c 38a39
printk_debug("ADM1027: monitoring enabled\r\n"); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/drivers/i2c/lm63/lm63.c LinuxBIOSv2/src/drivers/i2c/lm63/lm63.c 44c44 < CHIP_NAME("lm63")
CHIP_NAME("National Semiconductor LM63") Only in LinuxBIOSv2/src/include/cpu/amd: amdk8_sysconf.h diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/include/cpu/amd/lxdef.h LinuxBIOSv2/src/include/cpu/amd/lxdef.h 223a224,225 /* ----- GX3 OK ---- */
229a232,236
#define CPU_DM_CONFIG1 0x1801
#define CPU_DM_PFLOCK 0x1804
239d245 < /* ----- GX3 OK ---- */ 424,437c430,447 < #define GLPCI_ARB_UPPER_BM1_SET (1<<17) < #define GLPCI_ARB_UPPER_BM0_SET (1<<16) < #define GLPCI_ARB_UPPER_CPRE_SET (1<<15) < #define GLPCI_ARB_UPPER_PRE2_SET (1<<10) < #define GLPCI_ARB_UPPER_PRE1_SET (1<<9) < #define GLPCI_ARB_UPPER_PRE0_SET (1<<8) < #define GLPCI_ARB_UPPER_CRME_SET (1<<7) < #define GLPCI_ARB_UPPER_RME2_SET (1<<2) < #define GLPCI_ARB_UPPER_RME1_SET (1<<1) < #define GLPCI_ARB_UPPER_RME0_SET (1<<0) < #define GLPCI_ARB_LOWER_PRCM_SHIFT 24 < #define GLPCI_ARB_LOWER_FPVEC_SHIFT 16 < #define GLPCI_ARB_LOWER_RMT_SHIFT 6 < #define GLPCI_ARB_LOWER_IIE_SET (1<<8) ---
#define GLPCI_ARB_UPPER_CR_SHIFT (28) #define GLPCI_ARB_UPPER_R2_SHIFT (24) #define GLPCI_ARB_UPPER_R1_SHIFT (20) #define GLPCI_ARB_UPPER_R0_SHIFT (16) #define GLPCI_ARB_UPPER_CH_SHIFT (12) #define GLPCI_ARB_UPPER_H2_SHIFT (8) #define GLPCI_ARB_UPPER_H1_SHIFT (4) #define GLPCI_ARB_UPPER_H0_SHIFT (0) #define GLPCI_ARB_LOWER_COV_SET (1<<23) #define GLPCI_ARB_LOWER_MSK2_SET (1<<18) #define GLPCI_ARB_LOWER_MSK1_SET (1<<17) #define GLPCI_ARB_LOWER_MSK0_SET (1<<16) #define GLPCI_ARB_LOWER_CPRE_SET (1<<11) #define GLPCI_ARB_LOWER_PRE2_SET (1<<10) #define GLPCI_ARB_LOWER_PRE1_SET (1<<9) #define GLPCI_ARB_LOWER_PRE0_SET (1<<8) #define GLPCI_ARB_LOWER_BM1_SET (1<<7) #define GLPCI_ARB_LOWER_BM0_SET (1<<6) 509a520,521
/* ---------- GX3 OK -------------- */ 511a524,541 #define MSR_GLIU0_BASE3 (MSR_GLIU0 + 0x22) /* BM*/ #define MSR_GLIU0_BASE4 (MSR_GLIU0 + 0x23) /* BM*/ #define MSR_GLIU0_BASE5 (MSR_GLIU0 + 0x24) /* BM*/ #define MSR_GLIU0_BASE6 (MSR_GLIU0 + 0x25) /* BM*/
#define GLIU0_P2D_BMO_0 (MSR_GLIU0 + 0x26) #define GLIU0_P2D_BMO_1 (MSR_GLIU0 + 0x27)
#define MSR_GLIU0_SMM (GLIU0_P2D_BMO_0) #define MSR_GLIU0_DMM (GLIU0_P2D_BMO_1)
#define GLIU0_P2D_R (MSR_GLIU0 + 0x28) #define MSR_GLIU0_SYSMEM (GLIU0_P2D_R)
#define GLIU0_P2D_RO_0 (MSR_GLIU0 + 0x29) #define GLIU0_P2D_RO_1 (MSR_GLIU0 + 0x2A) #define GLIU0_P2D_RO_2 (MSR_GLIU0 + 0x2B)
513,515c543,554 < #define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R*/ < #define MSR_GLIU0_SMM (MSR_GLIU0 + 0x26) /* BMO*/ < #define MSR_GLIU0_DMM (MSR_GLIU0 + 0x27) /* BMO*/ ---
#define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0) #define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1) #define GLIU0_IOD_BM_2 (MSR_GLIU0 + 0xE2)
#define GLIU0_IOD_SC_0 (MSR_GLIU0 + 0xE3) #define GLIU0_IOD_SC_1 (MSR_GLIU0 + 0xE4) #define GLIU0_IOD_SC_2 (MSR_GLIU0 + 0xE5) #define GLIU0_IOD_SC_3 (MSR_GLIU0 + 0xE6) #define GLIU0_IOD_SC_4 (MSR_GLIU0 + 0xE7) #define GLIU0_IOD_SC_5 (MSR_GLIU0 + 0xE8)
519,523c558,592 < #define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2E) /* SCO should only be SC*/ // GX3 0x2D -> 0x2E < #define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x2A) /* RO should only be R*/ // GX3 0x29 -> 0x2A < #define MSR_GLIU1_SMM (MSR_GLIU1 + 0x23) /* BM*/ < #define MSR_GLIU1_DMM (MSR_GLIU1 + 0x24) /* BM*/ < #define MSR_GLIU1_FPU_TRAP (MSR_GLIU1 + 0x0E3) /* FooGlue F0 for FPU*/ ---
#define MSR_GLIU1_BASE3 (MSR_GLIU1 + 0x22) /* BM*/ #define MSR_GLIU1_BASE4 (MSR_GLIU1 + 0x23) /* BM*/ #define MSR_GLIU1_BASE5 (MSR_GLIU1 + 0x24) /* BM*/ #define MSR_GLIU1_BASE6 (MSR_GLIU1 + 0x25) /* BM*/ #define MSR_GLIU1_BASE7 (MSR_GLIU1 + 0x26) /* BM*/ #define MSR_GLIU1_BASE8 (MSR_GLIU1 + 0x27) /* BM*/ #define MSR_GLIU1_BASE9 (MSR_GLIU1 + 0x28) /* BM*/ #define MSR_GLIU1_BASE10 (MSR_GLIU1 + 0x29) /* BM*/
#define GLIU1_P2D_R_0 (MSR_GLIU1 + 0x2A) #define GLIU1_P2D_R_1 (MSR_GLIU1 + 0x2B) #define GLIU1_P2D_R_2 (MSR_GLIU1 + 0x2C) #define GLIU1_P2D_R_3 (MSR_GLIU1 + 0x2D)
#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2E)
#define MSR_GLIU1_SYSMEM (GLIU1_P2D_R_0)
#define MSR_GLIU1_SMM (MSR_GLIU1_BASE4) /* BM*/ #define MSR_GLIU1_DMM (MSR_GLIU1_BASE5) /* BM*/
#define GLIU1_IOD_BM_0 (MSR_GLIU1 + 0xE0) #define GLIU1_IOD_BM_1 (MSR_GLIU1 + 0xE1) #define GLIU1_IOD_BM_2 (MSR_GLIU1 + 0xE2)
#define GLIU1_IOD_SC_0 (MSR_GLIU1 + 0xE3) #define GLIU1_IOD_SC_1 (MSR_GLIU1 + 0xE4) #define GLIU1_IOD_SC_2 (MSR_GLIU1 + 0xE5) #define GLIU1_IOD_SC_3 (MSR_GLIU1 + 0xE6)
/* ------------------------ */
#define MSR_GLIU1_FPU_TRAP (GLIU1_IOD_SC_0) /* FooGlue F0 for FPU*/
527c596 < #define SMM_SIZE (128) /* changed SMM_SIZE from 256 KB to 128 KB */ ---
#define SMM_SIZE (256) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/include/cpu/amd/model_fxx_rev.h LinuxBIOSv2/src/include/cpu/amd/model_fxx_rev.h 2a3 #if K8_REV_F_SUPPORT == 0 76a78,85 #endif
#if K8_REV_F_SUPPORT == 1 //AMD_F0_SUPPORT static inline int is_cpu_pre_f0(void) { return (cpuid_eax(1) & 0xfff0f) < 0x40f00; } 77a87,119 static inline int is_cpu_f0(void) { return (cpuid_eax(1) & 0xfff00) == 0x40f00; }
static inline int is_cpu_pre_f2(void) { return (cpuid_eax(1) & 0xfff0f) < 0x40f02; }
#ifdef __ROMCC__ //AMD_F0_SUPPORT static int is_cpu_f0_in_bsp(int nodeid) { uint32_t dword; device_t dev; dev = PCI_DEV(0, 0x18+nodeid, 3); dword = pci_read_config32(dev, 0xfc); return (dword & 0xfff00) == 0x40f00; } static int is_cpu_pre_f2_in_bsp(int nodeid) { uint32_t dword; device_t dev; dev = PCI_DEV(0, 0x18+nodeid, 3); dword = pci_read_config32(dev, 0xfc); return (dword & 0xfff0f) < 0x40f02; } #else int is_cpu_f0_in_bsp(int nodeid); // defined in model_fxx_init.c #endif
#endif diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/include/cpu/x86/mem.h LinuxBIOSv2/src/include/cpu/x86/mem.h 9c9 < "rep stosl\n\t"
"rep; stosl\n\t"
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/include/device/device.h LinuxBIOSv2/src/include/device/device.h 51,52c51,52 < unsigned char secondary; /* secondary bus number */ < unsigned char subordinate; /* max subordinate bus number */ ---
uint16_t secondary; /* secondary bus number */ uint16_t subordinate; /* max subordinate bus number */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/include/device/hypertransport_def.h LinuxBIOSv2/src/include/device/hypertransport_def.h 13a14,18 #define HT_FREQ_1800Mhz 10 #define HT_FREQ_2000Mhz 11 #define HT_FREQ_2200Mhz 12 #define HT_FREQ_2400Mhz 13 #define HT_FREQ_2600Mhz 14 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/include/device/pci_def.h LinuxBIOSv2/src/include/device/pci_def.h 203a204 #define PCI_HT_CAP_SLAVE_LINK_ENUM 0x14 /* Link Enumeration Scratchpad */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/include/device/pci.h LinuxBIOSv2/src/include/device/pci.h 32,37c32,37 < uint8_t (*read8) (struct bus *pbus, unsigned char bus, int devfn, int where); < uint16_t (*read16) (struct bus *pbus, unsigned char bus, int devfn, int where); < uint32_t (*read32) (struct bus *pbus, unsigned char bus, int devfn, int where); < void (*write8) (struct bus *pbus, unsigned char bus, int devfn, int where, uint8_t val); < void (*write16) (struct bus *pbus, unsigned char bus, int devfn, int where, uint16_t val); < void (*write32) (struct bus *pbus, unsigned char bus, int devfn, int where, uint32_t val);
uint8_t (*read8) (struct bus *pbus, int bus, int devfn, int where); uint16_t (*read16) (struct bus *pbus, int bus, int devfn, int where); uint32_t (*read32) (struct bus *pbus, int bus, int devfn, int where); void (*write8) (struct bus *pbus, int bus, int devfn, int where, uint8_t val); void (*write16) (struct bus *pbus, int bus, int devfn, int where, uint16_t val); void (*write32) (struct bus *pbus, int bus, int devfn, int where, uint32_t val); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/include/device/pci_ids.h LinuxBIOSv2/src/include/device/pci_ids.h 402a403 #define PCI_DEVICE_ID_AMD_LXBRIDGE 0x2080 451c452 <
#define PCI_DEVICE_ID_AMD_AES 0x2082 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/include/spd.h LinuxBIOSv2/src/include/spd.h 2,3c2 < * spd.h: Definitions for Serial Presence Detect (SPD) data < * stored on SDRAM modules
* This file is part of the LinuxBIOS project. 5a5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> 22,47c22,34 < #ifndef __SPD_H_DEFINED < #define __SPD_H_DEFINED < < // Byte numbers < #define SPD_MEMORY_TYPE 2 < #define SPD_NUM_ROWS 3 < #define SPD_NUM_COLUMNS 4 < #define SPD_NUM_DIMM_BANKS 5 < #define SPD_MODULE_DATA_WIDTH_LSB 6 < #define SPD_MODULE_DATA_WIDTH_MSB 7 < #define SPD_MODULE_VOLTAGE 8 < #define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9 < #define SPD_DIMM_CONFIG_TYPE 11 < #define SPD_REFRESH 12 < #define SPD_PRIMARY_DRAM_WIDTH 13 < #define SPD_SUPPORTED_BURST_LENGTHS 16 < #define SPD_NUM_BANKS_PER_DRAM 17 < #define SPD_ACCEPTABLE_CAS_LATENCIES 18 < #define SPD_MODULE_ATTRIBUTES 21 < #define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_05 23 < #define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_10 25 < #define SPD_MIN_ROW_PRECHARGE_TIME 27 < #define SPD_MIN_RAS_TO_CAS_DELAY 29 < #define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30 < #define SPD_ADDRESS_CMD_HOLD 33 <
/* * Serial Presence Detect (SPD) data stored on SDRAM modules. * * Datasheet: * - Name: PC SDRAM Serial Presence Detect (SPD) Specification * Revision 1.2A, December, 1997 * - PDF: http://www.intel.com/design/chipsets/memory/spdsd12a.pdf * * Datasheet (alternative): * - Name: SERIAL PRESENCE DETECT STANDARD, General Standard * JEDEC Standard No. 21-C * - PDF: http://www.jedec.org/download/search/4_01_02_00R9.PDF */ 49,50c36,37 < // SPD_MEMORY_TYPE values < #define MEMORY_TYPE_SDRAM_DDR 7
#ifndef _SPD_H_ #define _SPD_H_ 52,53c39,103 < // SPD_MODULE_VOLTAGE values < #define SPD_VOLTAGE_SSTL2 4
/* Byte numbers. */ #define SPD_NUM_MANUFACTURER_BYTES 0 /* Number of bytes used by module manufacturer */ #define SPD_TOTAL_SPD_MEMORY_SIZE 1 /* Total SPD memory size */ #define SPD_MEMORY_TYPE 2 /* (Fundamental) memory type */ #define SPD_NUM_ROWS 3 /* Number of row address bits */ #define SPD_NUM_COLUMNS 4 /* Number of column address bits */ #define SPD_NUM_DIMM_BANKS 5 /* Number of module rows (banks) */ #define SPD_MODULE_DATA_WIDTH_LSB 6 /* Module data width (LSB) */ #define SPD_MODULE_DATA_WIDTH_MSB 7 /* Module data width (MSB) */ #define SPD_MODULE_VOLTAGE 8 /* Module interface signal levels */ #define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9 /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */ #define SPD_ACCESS_TIME_FROM_CLOCK 10 /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */ #define SPD_DIMM_CONFIG_TYPE 11 /* Module configuration type */ #define SPD_REFRESH 12 /* Refresh rate/type */ #define SPD_PRIMARY_SDRAM_WIDTH 13 /* SDRAM width (primary SDRAM) */ #define SPD_ERROR_CHECKING_SDRAM_WIDTH 14 /* Error checking SDRAM (data) width */ #define SPD_MIN_CLOCK_DELAY_B2B_RAND_COLUMN 15 /* SDRAM device attributes, minimum clock delay for back to back random column */ #define SPD_SUPPORTED_BURST_LENGTHS 16 /* SDRAM device attributes, burst lengths supported */ #define SPD_NUM_BANKS_PER_SDRAM 17 /* SDRAM device attributes, number of banks on SDRAM device */ #define SPD_ACCEPTABLE_CAS_LATENCIES 18 /* SDRAM device attributes, CAS latency */ #define SPD_CS_LATENCY 19 /* SDRAM device attributes, CS latency */ #define SPD_WE_LATENCY 20 /* SDRAM device attributes, WE latency */ #define SPD_MODULE_ATTRIBUTES 21 /* SDRAM module attributes */ #define SPD_DEVICE_ATTRIBUTES_GENERAL 22 /* SDRAM device attributes, general */ #define SPD_SDRAM_CYCLE_TIME_2ND 23 /* SDRAM cycle time (2nd highest CAS latency) */ #define SPD_ACCESS_TIME_FROM_CLOCK_2ND 24 /* SDRAM access from clock (2nd highest CAS latency) */ #define SPD_SDRAM_CYCLE_TIME_3RD 25 /* SDRAM cycle time (3rd highest CAS latency) */ #define SPD_ACCESS_TIME_FROM_CLOCK_3RD 26 /* SDRAM access from clock (3rd highest CAS latency) */ #define SPD_MIN_ROW_PRECHARGE_TIME 27 /* Minimum row precharge time (Trp) */ #define SPD_MIN_ROWACTIVE_TO_ROWACTIVE 28 /* Minimum row active to row active (Trrd) */ #define SPD_MIN_RAS_TO_CAS_DELAY 29 /* Minimum RAS to CAS delay (Trcd) */ #define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30 /* Minimum RAS pulse width (Tras) */ #define SPD_DENSITY_OF_EACH_ROW_ON_MODULE 31 /* Density of each row on module */ #define SPD_CMD_SIGNAL_INPUT_SETUP_TIME 32 /* Command and address signal input setup time */ #define SPD_CMD_SIGNAL_INPUT_HOLD_TIME 33 /* Command and address signal input hold time */ #define SPD_DATA_SIGNAL_INPUT_SETUP_TIME 34 /* Data signal input setup time */ #define SPD_DATA_SIGNAL_INPUT_HOLD_TIME 35 /* Data signal input hold time */ #define SPD_SPD_DATA_REVISION_CODE 62 /* SPD data revision code */ #define SPD_CHECKSUM_FOR_BYTES_0_TO_62 63 /* Checksum for bytes 0-62 */ #define SPD_MANUFACTURER_JEDEC_ID_CODE 64 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */ #define SPD_MANUFACTURING_LOCATION 72 /* Manufacturing location */ #define SPD_MANUFACTURER_PART_NUMBER 73 /* Manufacturer's part number, in 6-bit ASCII (bytes 73-90) */ #define SPD_REVISION_CODE 91 /* Revision code (bytes 91-92) */ #define SPD_MANUFACTURING_DATE 93 /* Manufacturing date (byte 93: year, byte 94: week) */ #define SPD_ASSEMBLY_SERIAL_NUMBER 95 /* Assembly serial number (bytes 95-98) */ #define SPD_MANUFACTURER_SPECIFIC_DATA 99 /* Manufacturer specific data (bytes 99-125) */ #define SPD_INTEL_SPEC_FOR_FREQUENCY 126 /* Intel specification for frequency */ #define SPD_INTEL_SPEC_100_MHZ 127 /* Intel specification details for 100MHz support */
/* SPD_MEMORY_TYPE values. */ #define SPD_MEMORY_TYPE_FPM_DRAM 1 #define SPD_MEMORY_TYPE_EDO 2 #define SPD_MEMORY_TYPE_PIPELINED_NIBBLE 3 #define SPD_MEMORY_TYPE_SDRAM 4 #define SPD_MEMORY_TYPE_MULTIPLEXED_ROM 5 #define SPD_MEMORY_TYPE_SGRAM_DDR 6 #define SPD_MEMORY_TYPE_SDRAM_DDR 7 #define SPD_MEMORY_TYPE_SDRAM_DDR2 8
/* SPD_MODULE_VOLTAGE values. */ #define SPD_VOLTAGE_TTL 0 /* 5.0 Volt/TTL */ #define SPD_VOLTAGE_LVTTL 1 /* LVTTL */ #define SPD_VOLTAGE_HSTL 2 /* HSTL 1.5 */ #define SPD_VOLTAGE_SSTL3 3 /* SSTL 3.3 */ #define SPD_VOLTAGE_SSTL2 4 /* SSTL 2.5 */ 55c105 < // SPD_DIMM_CONFIG_TYPE values
/* SPD_DIMM_CONFIG_TYPE values. */ 60c110,111 < // SPD_ACCEPTABLE_CAS_LATENCIES values
/* SPD_ACCEPTABLE_CAS_LATENCIES values. */ // TODO: Check values. 69c120 < // SPD_SUPPORTED_BURST_LENGTHS values
/* SPD_SUPPORTED_BURST_LENGTHS values. */ 74,75c125 < #define SPD_BURST_LENGTH_PAGE (1<<7) <
#define SPD_BURST_LENGTH_PAGE (1 << 7) 77c127 < // SPD_MODULE_ATTRIBUTES values
/* SPD_MODULE_ATTRIBUTES values. */ 81c131,132 < #endif // __SPD_H_DEFINED
#endif /* _SPD_H_ */
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/lib/Config.lb LinuxBIOSv2/src/lib/Config.lb 2a3
uses CONFIG_USE_PRINTK_IN_CAR 18a20 # if CONFIG_USE_PRINTK_IN_CAR 19a22 # end Only in LinuxBIOSv2/src/lib: lzma.c Only in LinuxBIOSv2/src/lib: lzmadecode.c Only in LinuxBIOSv2/src/lib: lzmadecode.h diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/lib/nrv2b.c LinuxBIOSv2/src/lib/nrv2b.c 31,32c31 < < static unsigned long unrv2b(uint8_t * src, uint8_t * dst)
static unsigned long unrv2b(uint8_t * src, uint8_t * dst, unsigned long *ilen_p) 38d36 < unsigned long file_len = *(unsigned long *) src; 40,42d37 < // we only have printk_debug in copy_and_run.c if CONFIG_USE_INIT is < // not set, so comment it out. < // printk_debug("compressed file len is supposed to be %d bytes\n", file_len); 84,86c79,80 < // we only have printk_debug in copy_and_run.c if CONFIG_USE_INIT is < // not set, so comment it out. < //printk_debug("computed len is %d, file len is %d\n", olen, file_len);
*ilen_p = ilen;
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/lib/uart8250.c LinuxBIOSv2/src/lib/uart8250.c 42d41 < int loop; 45,53d43 < < /* < loop=90; < while(loop !=0) { < outb(0x80,0x80); < loop--; < } < */ < 76a67,68
/* assert DTR and RTS so the other end is happy */ outb(0x03, base_port + UART_MCR); Only in LinuxBIOSv2/src/lib: xmodem.c Only in LinuxBios_mine/src/mainboard: advantech diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/agami/aruma/cache_as_ram_auto.c LinuxBIOSv2/src/mainboard/agami/aruma/cache_as_ram_auto.c 11c11 < #define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/agami/aruma/Config.lb LinuxBIOSv2/src/mainboard/agami/aruma/Config.lb 18c18 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 54c54 < action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
action "iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
61c61 < action "/usr/sbin/iasl -tc $(MAINBOARD)/ssdt_lb_x.dsl" ---
action "iasl -tc $(MAINBOARD)/ssdt_lb_x.dsl"
70c70 < action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci2.asl" ---
action "iasl -tc $(MAINBOARD)/dx/pci2.asl"
77c77 < action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci3.asl" ---
action "iasl -tc $(MAINBOARD)/dx/pci3.asl"
84c84 < action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci4.asl" ---
action "iasl -tc $(MAINBOARD)/dx/pci4.asl"
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/agami/aruma/Options.lb LinuxBIOSv2/src/mainboard/agami/aruma/Options.lb 21,22c21,23 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START ---
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 141c142 < default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0 187c188 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/quartet/auto.c LinuxBIOSv2/src/mainboard/amd/quartet/auto.c 25c25 < #include "superio/NSC/pc87360/pc87360_early_serial.c"
#include "superio/nsc/pc87360/pc87360_early_serial.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/quartet/Config.lb LinuxBIOSv2/src/mainboard/amd/quartet/Config.lb 18c18 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 140c140 < chip superio/NSC/pc87360
chip superio/nsc/pc87360
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/quartet/mainboard.c LinuxBIOSv2/src/mainboard/amd/quartet/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 10c5 < CHIP_NAME("AMD Quartet mainboard ") ---
CHIP_NAME("AMD Quartet Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/quartet/Options.lb LinuxBIOSv2/src/mainboard/amd/quartet/Options.lb 18,19c18,20 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 147c148 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/rumba/Config.lb LinuxBIOSv2/src/mainboard/amd/rumba/Config.lb 17c17 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/rumba/mainboard.c LinuxBIOSv2/src/mainboard/amd/rumba/mainboard.c 40c40 < CHIP_NAME("AMD Rumba mainboard ")
CHIP_NAME("AMD Rumba Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/rumba/Options.lb LinuxBIOSv2/src/mainboard/amd/rumba/Options.lb 8c8 < uses CONFIG_ROM_STREAM
uses CONFIG_ROM_PAYLOAD 23,24c23,24 < uses CONFIG_ROM_STREAM_START < uses CONFIG_COMPRESSED_ROM_STREAM
uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 109c109 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/serenade/auto.c LinuxBIOSv2/src/mainboard/amd/serenade/auto.c 16d15 < #include "northbridge/amd/amdk8/incoherent_ht.c" 28d26 < #include "cpu/amd/dualcore/dualcore.c" 130a129 #include "northbridge/amd/amdk8/incoherent_ht.c" 132a132 #include "cpu/amd/dualcore/dualcore.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/serenade/Config.lb LinuxBIOSv2/src/mainboard/amd/serenade/Config.lb 18c18 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/serenade/mainboard.c LinuxBIOSv2/src/mainboard/amd/serenade/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 9c5 < CHIP_NAME("AMD Serenade mainboard ")
CHIP_NAME("AMD Serenade Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/serenade/Options.lb LinuxBIOSv2/src/mainboard/amd/serenade/Options.lb 18,19c18,20 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 146c147 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 Only in LinuxBIOSv2/src/mainboard/amd: serengeti_cheetah diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/serengeti_leopard/acpi_tables.c LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/acpi_tables.c 17a18 #include <cpu/amd/amdk8_sysconf.h> 19c20 < #define DUMP_ACPI_TABLES 1
#define DUMP_ACPI_TABLES 0 37d37 < #define HC_POSSIBLE_NUM 8 65,70d64 < extern unsigned pci1234[]; < extern unsigned hc_possible_num; < extern unsigned sblk; < extern unsigned sbdn; < extern unsigned hcdn[]; < 86c80 < dev = dev_find_slot(bus_8132_0, PCI_DEVFN((hcdn[0]&0xff), 1));
dev = dev_find_slot(bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1));
96c90 < dev = dev_find_slot(bus_8132_0, PCI_DEVFN((hcdn[0] & 0xff)+1, 1)); ---
dev = dev_find_slot(bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1));
123,131d116 < //FIXME: next could be moved to northbridge/amd/amdk8/amdk8_acpi.c or cpu/amd/k8/k8_acpi.c begin < static void int_to_stream(uint32_t val, uint8_t *dest) < { < int i; < for(i=0;i<4;i++) { < *(dest+i) = (val >> (8*i)) & 0xff; < } < } < 134,194c119 < static void update_ssdt(void *ssdt) < { < uint8_t *BUSN; < uint8_t *MMIO; < uint8_t *PCIO; < uint8_t *SBLK; < uint8_t *TOM1; < uint8_t *SBDN; < uint8_t *HCLK; < uint8_t *HCDN; < < int i; < device_t dev; < uint32_t dword; < msr_t msr; < < BUSN = ssdt+0x3a; //+5 will be next BUSN < MMIO = ssdt+0x57; //+5 will be next MMIO < PCIO = ssdt+0xaf; //+5 will be next PCIO < SBLK = ssdt+0xdc; // one byte < TOM1 = ssdt+0xe3; // < SBDN = ssdt+0xed;// < HCLK = ssdt+0xfa; //+5 will be next HCLK < HCDN = ssdt+0x12a; //+5 will be next HCDN < < < dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); < < for(i=0;i<4;i++) { < dword = pci_read_config32(dev, 0xe0+i*4); < int_to_stream(dword, BUSN+i*5); < } < < for(i=0;i<0x10;i++) { < dword = pci_read_config32(dev, 0x80+i*4); < int_to_stream(dword, MMIO+i*5); < } < < for(i=0;i<0x08;i++) { < dword = pci_read_config32(dev, 0xc0+i*4); < int_to_stream(dword, PCIO+i*5); < } < < *SBLK = (uint8_t)(sblk); < < msr = rdmsr(TOP_MEM); < int_to_stream(msr.lo, TOM1); < < for(i=0;i<hc_possible_num;i++) { < int_to_stream(pci1234[i], HCLK + i*5); < int_to_stream(hcdn[i], HCDN + i*5); < } < for(i=hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 < int_to_stream(0x00000000, HCLK + i*5); < int_to_stream(0x20202020, HCDN + i*5); < } < < int_to_stream(sbdn, SBDN); < < } < //end ---
extern void update_ssdt(void *ssdt); 282,283c207,208 < for(i=1;i<hc_possible_num;i++) { // 0: is hc sblink < if((pci1234[i] & 1) != 1 ) continue;
for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink if((sysconf.pci1234[i] & 1) != 1 ) continue; diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/serengeti_leopard/auto.c LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/auto.c 132c132 < #define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c 11c11 < #define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1 25a26,27
#if USE_FAILOVER_IMAGE==0 46,47d47 < #if CONFIG_USE_INIT == 0 < #include "lib/memcpy.c" 51a52,63
#if USE_FAILOVER_IMAGE==0
#if CONFIG_USE_INIT == 0 #include "lib/memcpy.c" #if CONFIG_USE_PRINTK_IN_CAR == 1 #include "lib/uart8250.c" #include "console/vtxprintf.c" #include "arch/i386/lib/printk_init.c" #endif #endif
140c152,154 < #if USE_FALLBACK_IMAGE == 1 ---
#endif
#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) 186a201,206 #if HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ ) #endif 195,196c214,215 < < #if USE_FALLBACK_IMAGE == 1
#if HAVE_FAILOVER_BOOT==1 #if USE_FAILOVER_IMAGE==1 198c217 < #endif
#else
200c219,225 < ---
#endif #else #if USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif
202a228,229
#if USE_FAILOVER_IMAGE==0
247a275,278
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ 289a321,322
#endif diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/serengeti_leopard/cmos.layout LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/cmos.layout 81,84c81,84 < 8 0 DDR400 < 8 1 DDR333 < 8 2 DDR266 < 8 3 DDR200
8 0 200Mhz 8 1 166Mhz 8 2 133Mhz 8 3 100Mhz diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/serengeti_leopard/Config.lb LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Config.lb 5,7c5,7 < if USE_FALLBACK_IMAGE < default ROM_SECTION_SIZE = FALLBACK_SIZE < default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
if USE_FAILOVER_IMAGE default ROM_SECTION_SIZE = FAILOVER_SIZE default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) 9c9,13 < default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) else default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
10a15
end
18c23 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) ---
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c28 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 33c38,47 < default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
if USE_FAILOVER_IMAGE default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) else if USE_FALLBACK_IMAGE default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) else default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) end end
59c73 < # if K8_SB_HT_CHAIN_ON_BUS0 ---
# if SB_HT_CHAIN_ON_BUS0 66c80 < # if K8_SB_HT_CHAIN_ON_BUS0
# if SB_HT_CHAIN_ON_BUS0 77,83d90 < if K8_SB_HT_CHAIN_ON_BUS0 < makerule dsdt.c < depends "$(MAINBOARD)/dx_bus0/dsdt_lb.dsl" < action "/usr/sbin/iasl -tc $(MAINBOARD)/dx_bus0/dsdt_lb.dsl" < action "mv dsdt_lb.hex dsdt.c" < end < else 86c93 < action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
action "iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
89d95 < end 92,98c98 < makerule ssdt.c < depends "$(MAINBOARD)/ssdt_lb_x.dsl" < action "/usr/sbin/iasl -tc $(MAINBOARD)/ssdt_lb_x.dsl" < action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt_lb_x.hex" < action "mv ssdt_lb_x.hex ssdt.c" < end < object ./ssdt.o ---
#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb 101d100 < if K8_SB_HT_CHAIN_ON_BUS0 104,111c103 < action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci2.asl" < action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" < action "mv pci2.hex ssdt2.c" < end < else < makerule ssdt2.c < depends "$(MAINBOARD)/dx_bus0/pci2.asl" < action "/usr/sbin/iasl -tc $(MAINBOARD)/dx_bus0/pci2.asl"
action "iasl -tc $(MAINBOARD)/dx/pci2.asl"
115d106 < end 126c117 < action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o cache_as_ram_auto.o" ---
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
167,168c158,164 < < if USE_FALLBACK_IMAGE ---
if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else if USE_FALLBACK_IMAGE 170a167 end 187c184,185 < if USE_FALLBACK_IMAGE
if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE 189a188,191 else mainboardinit cpu/x86/32bit/reset32.inc ldscript /cpu/x86/32bit/reset32.lds end 190a193,196 if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else 192a199 end 219c226,233 < if USE_FALLBACK_IMAGE
if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds end end else if USE_FALLBACK_IMAGE 225a240 end diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/serengeti_leopard/dx/amd8111.asl LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8111.asl 15,18c15,18 < Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI1.LNKA, 0x00}, < Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI1.LNKB, 0x00}, < Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI1.LNKC, 0x00}, < Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI1.LNKD, 0x00}
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00}, Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00}, Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00}, Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
150,163c150,163 < Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 }, //USB < Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 }, < Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 }, < Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 }, < < Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 }, //Slot 4 < Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 }, < Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 }, < Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 }, < < Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 }, //Slot 3 < Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 }, < Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 }, < Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 } ---
Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 4 Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 3 Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/serengeti_leopard/dx/amd8111_pic.asl LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8111_pic.asl 12c12 < And (\_SB.PCI1.SBC3.PIBA, 0x0F, Local0) ---
And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0)
29c29 < And (\_SB.PCI1.SBC3.PIBA, 0x0F, Local1) ---
And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
38c38 < And (\_SB.PCI1.SBC3.PIBA, 0xF0, \_SB.PCI1.SBC3.PIBA) ---
And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
51c51 < And (\_SB.PCI1.SBC3.PIBA, 0x0F, Local1) ---
And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
88,89c88,89 < And (\_SB.PCI1.SBC3.PIBA, 0xF0, \_SB.PCI1.SBC3.PIBA) < Or (\_SB.PCI1.SBC3.PIBA, Local1, \_SB.PCI1.SBC3.PIBA) ---
And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA) Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
99c99 < And (\_SB.PCI1.SBC3.PIBA, 0xF0, Local0) ---
And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0)
116c116 < And (\_SB.PCI1.SBC3.PIBA, 0xF0, Local1) ---
And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
126c126 < And (\_SB.PCI1.SBC3.PIBA, 0x0F, \_SB.PCI1.SBC3.PIBA) ---
And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
139c139 < And (\_SB.PCI1.SBC3.PIBA, 0xF0, Local1) ---
And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
177c177 < And (\_SB.PCI1.SBC3.PIBA, 0x0F, \_SB.PCI1.SBC3.PIBA) ---
And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
179c179 < Or (\_SB.PCI1.SBC3.PIBA, Local1, \_SB.PCI1.SBC3.PIBA) ---
Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
189c189 < And (\_SB.PCI1.SBC3.PIDC, 0x0F, Local0) ---
And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0)
206c206 < And (\_SB.PCI1.SBC3.PIDC, 0x0F, Local1) ---
And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
215c215 < And (\_SB.PCI1.SBC3.PIDC, 0xF0, \_SB.PCI1.SBC3.PIDC) ---
And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
228c228 < And (\_SB.PCI1.SBC3.PIDC, 0x0F, Local1) ---
And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
265,266c265,266 < And (\_SB.PCI1.SBC3.PIDC, 0xF0, \_SB.PCI1.SBC3.PIDC) < Or (\_SB.PCI1.SBC3.PIDC, Local1, \_SB.PCI1.SBC3.PIDC) ---
And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC) Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
276c276 < And (\_SB.PCI1.SBC3.PIDC, 0xF0, Local0) ---
And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0)
293c293 < And (\_SB.PCI1.SBC3.PIDC, 0xF0, Local1) ---
And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
303c303 < And (\_SB.PCI1.SBC3.PIDC, 0x0F, \_SB.PCI1.SBC3.PIDC) ---
And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
316c316 < And (\_SB.PCI1.SBC3.PIDC, 0xF0, Local1) ---
And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
354c354 < And (\_SB.PCI1.SBC3.PIDC, 0x0F, \_SB.PCI1.SBC3.PIDC) ---
And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
356c356 < Or (\_SB.PCI1.SBC3.PIDC, Local1, \_SB.PCI1.SBC3.PIDC) ---
Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/serengeti_leopard/dx/amd8131.asl LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8131.asl 53,76c53,76 < Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 },//Slot 2 < Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 }, < Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 }, < Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 }, < < Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 }, < Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 }, < Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 }, < Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 }, < < Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI1.LNKC, 0x00 }, < Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI1.LNKD, 0x00 }, < Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI1.LNKA, 0x00 }, < Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI1.LNKB, 0x00 }, < < Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI1.LNKD, 0x00 }, < Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI1.LNKA, 0x00 }, < Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI1.LNKB, 0x00 }, < Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI1.LNKC, 0x00 }, < < Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 }, < Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 }, < Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 }, < Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 } ---
Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2 Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
109,112c109,112 < Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 },//Slot 1 < Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 }, < Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 }, < Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 } ---
Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/serengeti_leopard/dx/amd8151.asl LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8151.asl 18,21c18,21 < Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 }, < Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 }, < Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 }, < Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 } ---
Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/serengeti_leopard/dx/dsdt_lb.dsl LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/dsdt_lb.dsl 28,46d27 < /* < //hardcode begin < Name (BUSN, Package (0x04) { 0x04010003, 0x06050013, 0x00000000, 0x00000000 }) < Name (MMIO, Package (0x10) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, < 0x00f43003, 0x00f44f01, 0x0000d003, 0x00efff01, 0x00f40003, 0x00f42f00, 0x00f45003, 0x00f44f00 }) < Name (PCIO, Package (0x08) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00001003, 0x00001000, 0x00002003, 0x00002001 }) < Name (SBLK, 0x00) < Name (TOM1, 0x40000000) < < // for AMD opteron we could have four chains, so we will have PCI1, PCI2, PCI3, PCI4 < // PCI1 must be SBLK Chain < // If you have HT IO card that is connected to PCI2, PCI3, PCI4, then you man put Device in SSDT2, SSDT3, SSDT4, < // in acpi_tables.c you can link those SSDT to RSDT according to it's presence. < // Otherwise put the PCI2, PCI3, PCI4 in this dsdt < Name (HCLK, Package (0x04) { 0x00000001, 0x00000011, 0x00000000, 0x00000000 }) //[0,3]=1 enable [4,7]=node_id, [8,15]=linkn < < Name (SBDN, 3) // 8111 UnitID Base < //hardcode end < */ 54a36,37
External (CBST)
59,74d41 < Name (_BBN, 0) < < < // define L1IC Link1 on node0 init completed, so node1 is installed < // We must make sure our bus is 0 ? < OperationRegion (LDT1, PCI_Config, 0xA4, 0x01) < Field (LDT1, ByteAcc, Lock, Preserve) < { < , 5, < L1IC, 1 < } < < } < < Device (PCI1) < { 77,80c44 < // BUS 1 first HT Chain < Name (_HID, EisaId ("PNP0A03")) < Name (_ADR, 0x00180000) // Fake < Name (_UID, 0x02) ---
83c47 < Return (GBUS (0x00, \_SB.PCI0.SBLK)) ---
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
142c106 < Include ("pci1_hc.asl") ---
Include ("pci0_hc.asl")
145,146c109 < /* < Device (PCI2) ---
Device (PCI1)
148,151d110 < < // BUS ? Second HT Chain < Name (HCIN, 0x01) // HC2 < 153,164c112,113 < < Method (_ADR, 0, NotSerialized) //Fake bus should be 0 < { < Return (DADD(GHCN(HCIN), 0x00180000)) < } < Name (_UID, 0x03) < < Method (_BBN, 0, NotSerialized) < { < Return (GBUS (GHCN(HCIN), GHCL(HCIN))) < } < ---
Name (_ADR, 0x00000000) Name (_UID, 0x02)
167c116 < Return (\_SB.GHCE(HCIN)) ---
Return (\_SB.PCI0.CBST)
169,179c118 < < Method (_CRS, 0, NotSerialized) < { < Name (BUF0, ResourceTemplate () { }) < Store( GHCN(HCIN), Local4) < Store( GHCL(HCIN), Local5) < < Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) < Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) < Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) < Return (Local3) ---
Name (_BBN, 0x00)
182,184d120 < Include ("pci2_hc.asl") < } < */ 192c128 < Notify (\_SB.PCI1, 0x02) //PME# Wakeup ---
Notify (\_SB.PCI0, 0x02) //PME# Wakeup
197c133 < Notify (\_SB.PCI1.TP2P.USB0, 0x02) //USB Wakeup ---
Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
202c138 < Notify (\_SB.PCI1.PG0B, 0x02) ---
Notify (\_SB.PCI0.PG0B, 0x02)
207c143 < Notify (\_SB.PCI1.PG0A, 0x02) ---
Notify (\_SB.PCI0.PG0A, 0x02)
Only in LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx: pci0_hc.asl diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/serengeti_leopard/dx/pci2.asl LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/pci2.asl 21,24c21,24 < External (\_SB.PCI1.LNKA, DeviceObj) < External (\_SB.PCI1.LNKB, DeviceObj) < External (\_SB.PCI1.LNKC, DeviceObj) < External (\_SB.PCI1.LNKD, DeviceObj) ---
External (\_SB.PCI0.LNKA, DeviceObj) External (\_SB.PCI0.LNKB, DeviceObj) External (\_SB.PCI0.LNKC, DeviceObj) External (\_SB.PCI0.LNKD, DeviceObj) Only in LinuxBios_mine/src/mainboard/amd/serengeti_leopard: dx_bus0 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/serengeti_leopard/get_bus_conf.c LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/get_bus_conf.c 9a10,11 #include <cpu/amd/amdk8_sysconf.h>
12d13 < //busnum is default 25,26c26 < unsigned sblk; < unsigned pci1234[] = ---
static unsigned pci1234x[] = 38,40c38 < unsigned hc_possible_num; < unsigned sbdn; < unsigned hcdn[] =
static unsigned hcdnx[] = 63a63 int i; 69c69,73 < hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } 73,75c77,79 < sbdn = (hcdn[0] >> 8) & 0xff; < sbdn3 = hcdn[0] & 0xff; < sbdn5 = hcdn[1] & 0xff;
sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; sbdn3 = sysconf.hcdn[0] & 0xff; sbdn5 = sysconf.hcdn[1] & 0xff; 77,78c81 < // bus_8132_0 = node_link_to_bus(0, sblk); < bus_8132_0 = (pci1234[0] >> 16) & 0xff;
bus_8132_0 = (sysconf.pci1234[0] >> 16) & 0xff; 82c85 < dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sbdn,0));
dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
92c95 < printk_debug("ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0); ---
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_8111_0, sysconf.sbdn);
99,103d101 < #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE < bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); < bus_isa++; < // printk_debug("bus_isa=%d\n",bus_isa); < #endif 106c104 < printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8132_0); ---
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_8132_0, sbdn3);
112a111,115
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); #endif 115c118 < printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8132_0);
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_8132_0, sbdn3+1);
119,120c122,123 < if((pci1234[1] & 0x1) == 1) { < bus_8151_0 = (pci1234[1] >> 16) & 0xff; ---
if((sysconf.pci1234[1] & 0x1) == 1) { bus_8151_0 = (sysconf.pci1234[1] >> 16) & 0xff; 129a133,135 else { printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_8151_0, sbdn5+1); } diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/serengeti_leopard/irq_tables.c LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/irq_tables.c 11a12 #include <cpu/amd/amdk8_sysconf.h> 39,42d39 < extern unsigned pci1234[]; < < extern unsigned sbdn; < extern unsigned hcdn[]; 75c72 < pirq->rtr_devfn = ((sbdn+1)<<3)|0;
pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0; 89c86 < write_pirq_info(pirq_info, bus_8111_0, ((sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
write_pirq_info(pirq_info, bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); 95c92 < if(pci1234[1] & 0xf) {
if(sysconf.pci1234[1] & 0xf) { diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/serengeti_leopard/mainboard.c LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 10c6 < CHIP_NAME("AMD serengeti_leopard mainboard")
CHIP_NAME("AMD Serengeti Leopard Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/serengeti_leopard/mptable.c LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/mptable.c 9a10,11 #include <cpu/amd/amdk8_sysconf.h>
22,24d23 < extern unsigned pci1234[]; < extern unsigned sbdn; < extern unsigned hcdn[]; 105c104 < smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sbdn+1)<<2)|3, apicid_8111, 0x13); ---
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|3, apicid_8111, 0x13);
110c109 < if(pci1234[1] & 0xf) { ---
if(sysconf.pci1234[1] & 0xf) { diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/serengeti_leopard/Options.lb LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Options.lb 6a7,8 uses USE_FAILOVER_IMAGE uses HAVE_FAILOVER_BOOT 15a18 uses FAILOVER_SIZE 21,22c24,26 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 57,58c61,62 < uses K8_HW_MEM_HOLE_SIZEK < uses K8_HW_MEM_HOLE_SIZE_AUTO_INC
uses HW_MEM_HOLE_SIZEK uses HW_MEM_HOLE_SIZE_AUTO_INC 63c67 < uses K8_SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_ON_BUS0 78a83,85 uses CONFIG_LB_MEM_TOPK
uses CONFIG_USE_PRINTK_IN_CAR 93,94c100,107 < #256K < default FALLBACK_SIZE=0x40000
#default FALLBACK_SIZE=0x40000
#FALLBACK: 256K-4K default FALLBACK_SIZE=0x3f000 #FAILOVER: 4K default FAILOVER_SIZE=0x01000
default CONFIG_LB_MEM_TOPK=2048 99a113 default HAVE_FAILOVER_BOOT=1 144c158 < #default SERIAL_CPU_INIT=0
default SERIAL_CPU_INIT=0 155c169 < default K8_HW_MEM_HOLE_SIZEK=0x200000
#default HW_MEM_HOLE_SIZEK=0x200000 157c171 < #default K8_HW_MEM_HOLE_SIZEK=0x100000
default HW_MEM_HOLE_SIZEK=0x100000 159c173 < #default K8_HW_MEM_HOLE_SIZEK=0x80000
#default HW_MEM_HOLE_SIZEK=0x80000 162c176 < #default K8_HW_MEM_HOLE_SIZE_AUTO_INC=1
#default HW_MEM_HOLE_SIZE_AUTO_INC=1 172c186 < default HT_CHAIN_UNITID_BASE=0x4
default HT_CHAIN_UNITID_BASE=0xa 175c189 < default HT_CHAIN_END_UNITID_BASE=0x1
default HT_CHAIN_END_UNITID_BASE=0x6 178c192 < default K8_SB_HT_CHAIN_ON_BUS0=1
default SB_HT_CHAIN_ON_BUS0=2 189c203 < default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0 224c238 < default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) 234c248 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 243,244c257,258 < default CC="$(CROSS_COMPILE)gcc -m32" < default HOSTCC="gcc"
default CC="$(CROSS_COMPILE)gcc-4.0.2 -m32" default HOSTCC="gcc-4.0.2" 253a268 default CONFIG_USE_PRINTK_IN_CAR=1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/solo/auto.c LinuxBIOSv2/src/mainboard/amd/solo/auto.c 22c22 < #include "superio/NSC/pc87360/pc87360_early_serial.c"
#include "superio/nsc/pc87360/pc87360_early_serial.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/solo/Config.lb LinuxBIOSv2/src/mainboard/amd/solo/Config.lb 18c18 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 148c148 < chip superio/NSC/pc87360
chip superio/nsc/pc87360
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/solo/mainboard.c LinuxBIOSv2/src/mainboard/amd/solo/mainboard.c 1,2d0 < < #include <console/console.h> 4,6d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 10c5 < CHIP_NAME("AMD Solo7 mainboard") ---
CHIP_NAME("AMD Solo7 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/amd/solo/Options.lb LinuxBIOSv2/src/mainboard/amd/solo/Options.lb 19,20c19,21 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 148c149 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/arima/hdama/auto.c LinuxBIOSv2/src/mainboard/arima/hdama/auto.c 15d14 < #include "northbridge/amd/amdk8/incoherent_ht.c" 22c21 < #include "superio/NSC/pc87360/pc87360_early_serial.c"
#include "superio/nsc/pc87360/pc87360_early_serial.c" 25d23 < #include "cpu/amd/dualcore/dualcore.c" 143a142 #include "northbridge/amd/amdk8/incoherent_ht.c" 144a144 #include "cpu/amd/dualcore/dualcore.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/arima/hdama/Config.lb LinuxBIOSv2/src/mainboard/arima/hdama/Config.lb 18c18 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 231c231 < chip superio/NSC/pc87360
chip superio/nsc/pc87360
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/arima/hdama/mainboard.c LinuxBIOSv2/src/mainboard/arima/hdama/mainboard.c 1d0 < #include <console/console.h> 3,9d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> < #include <cpu/x86/msr.h> < #include <part/hard_reset.h> < #include <device/smbus.h> < #include <delay.h> 14c5 < CHIP_NAME("Arima Hdama mainboard") ---
CHIP_NAME("Arima HDAMA Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/arima/hdama/Options.lb LinuxBIOSv2/src/mainboard/arima/hdama/Options.lb 18,19c18,20 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 165c166 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/artecgroup/dbe61/auto.c LinuxBIOSv2/src/mainboard/artecgroup/dbe61/auto.c 40,57d39 < < < < /* sdram parameters for OLPC: < row address = 13 < col address = 9 < banks = 4 < dimm0size=128MB < d0_MB=1 (module banks) < d0_cb=4 (component banks) < do_psz=4KB (page size) < Trc=10 (clocks) (ref2act) < Tras=7 (act2pre) < Trcd=3 (act2cmd) < Trp=3 (pre2act) < Trrd=2 (act2act) < Tref=17.8ms < */ 68,110c50,51 < < #if 0 //GX3 < msr = rdmsr(MC_CF07_DATA); < < /* get module banks (sides) per dimm, SPD byte 5 */ < module_banks = 1; < module_banks >>= 1; < msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT); < msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT); < < /* get component banks per module bank, SPD byte 17 */ < val = 4; < val >>= 2; < msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT); < msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT); < < /* get the module bank density, SPD byte 31 */ < /* this is multiples of 8 MB */ < /* actually it is 2^x*4, where x is the value you put in */ < /* for OLPC, set default size */ < /* dimm size - hardcoded 128Mb */ < val = 5; < msr.hi &= ~(0xf << CF07_UPPER_D0_SZ_SHIFT); < msr.hi |= (val << CF07_UPPER_D0_SZ_SHIFT); < < /* page size = 2^col address */ < val = 2; /* 4096 bytes */ < msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT); < msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT); < < print_debug("computed msr.hi "); < print_debug_hex32(msr.hi); < print_debug("\r\n"); < < /* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */ < /* well, it may be close. It's about 200,000 ticks */ < msr.lo = 0x00003000; < wrmsr(MC_CF07_DATA, msr); < < #endif < < msr.hi = 0x00005012; < msr.lo = 0x05000040;
msr.hi = 0x10075012; msr.lo = 0x00000040; 143,146c84,88 < #define PLLMSRhi 0x00001490 < #define PLLMSRlo 0x02000030 < #define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24)) < #define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
/* CPU and GLIU mult/div */ #define PLLMSRhi 0x0000039C /* Hold Count - how long we will sit in reset */ #define PLLMSRlo 0x00DE0000
152,153d94 < __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02); < diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/artecgroup/dbe61/Config.lb LinuxBIOSv2/src/mainboard/artecgroup/dbe61/Config.lb 17c17 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) ---
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 128d127 < register "setupflash" = "1" 135,146c134,177 < device pci 1.0 on end < device pci 1.1 on end < chip southbridge/amd/cs5536 < register "enable_gpio0_inta" = "1" < register "enable_ide_nand_flash" = "1" < register "enable_uarta" = "1" < register "audio_irq" = "11" < register "usbf4_irq" = "5" < register "usbf5_irq" = "5" < register "usbf6_irq" = "5" < register "usbf7_irq" = "5" < device pci d.0 on end # Realtek 8139 LAN
device pci 1.0 on end # Host Bridge
# chip drivers/pci/realmode # device pci 1.1 on end # VGA # register "rom_address" = "0xfffc0000" # at the beginning of 256k # end
device pci 1.2 off end # AES chip southbridge/amd/cs5536_lx register "enable_ide_nand_flash" = "0"
register "isa_irq" = "0" #register "flash_irq" = "14"
## IDE IRQ register "enable_ide_irq" = "0"
register "audio_irq" = "5" register "usb_irq" = "7"
register "uart0_irq" = "0" register "uart1_irq" = "4"
## PCI INTA ... INTD and their GPIO pins ## int==0: disable register "pci_int[0]" = "0" register "pci_int[1]" = "10" register "pci_int[2]" = "0" register "pci_int[3]" = "0" register "pci_int_pin[0]" = "0" register "pci_int_pin[1]" = "7" register "pci_int_pin[2]" = "0" register "pci_int_pin[3]" = "0"
# Keyboard Emulation Logic IRQs # Enable keyboard IRQ2 register "enable_kel_keyb_irq" = "0" # Enable mouse IRQ12 register "enable_kel_mouse_irq" = "0" # Configure KEL Emulation IRQ, 0 to disable register "kel_emul_irq" = "0"
148c179,180 < device pci f.2 on end # IDE Controller ---
device pci f.1 on end # Flash controller device pci f.2 off end # IDE controller
152c184,185 < register "unwanted_vpci[0]" = "0" # End of list has a zero ---
device pci f.6 off end # UDC controller device pci f.7 off end # OTG controller
153a187,190
# chip drivers/pci/rtl8139 ## device pci d.0 on end # Realtek LAN # register "nic_irq" = "10" # end diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/artecgroup/dbe61/mainboard.c LinuxBIOSv2/src/mainboard/artecgroup/dbe61/mainboard.c 6a7,8 #include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> 8a11 #define DIVIL_LBAR_GPIO 0x5140000c 10c13 < static void init(struct device *dev)
static void init_gpio() 12,16c15,24 < unsigned bus = 0; < unsigned devNic = PCI_DEVFN(0xd, 0); < unsigned devUsb = PCI_DEVFN(0xf, 4); < device_t usb = NULL, nic = NULL; < unsigned char irqUsb = 0xa, irqNic = 0xb;
msr_t msr; printk_debug("Initializing GPIO module...\n");
// initialize the GPIO LBAR msr.lo = GPIO_BASE; msr.hi = 0x0000f001; wrmsr(DIVIL_LBAR_GPIO, msr); msr = rdmsr(DIVIL_LBAR_GPIO); printk_debug("DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo); } 17a26,28 static void init(struct device *dev) { // BOARD-SPECIFIC INIT 20,35c31 < // FIXME: do we need to initialize USB OHCI this way? < printk_debug("%s (%x,%x) set USB PCI interrupt line to %d\n", < __FUNCTION__, bus, devUsb, irqUsb); < < // initialize the USB controller < usb = dev_find_slot(bus, devUsb); < if (!usb) printk_err("Could not find USB\n"); < else pci_write_config8(usb, PCI_INTERRUPT_LINE, irqUsb); < < printk_debug("%s (%x,%x) set NIC PCI interrupt line to %d\n", < __FUNCTION__, bus, devNic, irqNic); < < // initialize the Realtek NIC < nic = dev_find_slot(bus, devNic); < if (!nic) printk_err("Could not find USB\n"); < else pci_write_config8(nic, PCI_INTERRUPT_LINE, irqNic);
init_gpio(); 46c42 < CHIP_NAME("artecgroup dbe61 mainboard ")
CHIP_NAME("Artec Group dbe61 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/artecgroup/dbe61/Options.lb LinuxBIOSv2/src/mainboard/artecgroup/dbe61/Options.lb 8c8 < uses CONFIG_ROM_STREAM
uses CONFIG_ROM_PAYLOAD 23,24c23,24 < uses CONFIG_ROM_STREAM_START < uses CONFIG_COMPRESSED_ROM_STREAM
uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 42a43,45 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_VIDEO_MB 49a53,55 default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=0 default CONFIG_VIDEO_MB=8 110c116 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 Only in LinuxBIOSv2/src/mainboard/artecgroup/dbe61: realmode diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/asus/p2b/Config.lb LinuxBIOSv2/src/mainboard/asus/p2b/Config.lb 17c17 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/asus/p2b/mainboard.c LinuxBIOSv2/src/mainboard/asus/p2b/mainboard.c 1d0 < #include <console/console.h> 3,6d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> < #include <arch/io.h> 10c5 < CHIP_NAME("ASUS P2B mainboard ")
CHIP_NAME("ASUS P2B Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/asus/p2b/Options.lb LinuxBIOSv2/src/mainboard/asus/p2b/Options.lb 8c8 < uses CONFIG_ROM_STREAM
uses CONFIG_ROM_PAYLOAD 23c23,24 < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 102c103 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/bitworks/ims/auto.c LinuxBIOSv2/src/mainboard/bitworks/ims/auto.c 13c13 < #include "superio/NSC/pc87351/pc87351_early_serial.c"
#include "superio/nsc/pc87351/pc87351_early_serial.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/bitworks/ims/Config.lb LinuxBIOSv2/src/mainboard/bitworks/ims/Config.lb 17c17 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/bitworks/ims/mainboard.c LinuxBIOSv2/src/mainboard/bitworks/ims/mainboard.c 1d0 < #include <console/console.h> 3,6d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> < #include <arch/io.h> 10c5 < CHIP_NAME("Bitworks IMS mainboard ")
CHIP_NAME("Bitworks IMS Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/bitworks/ims/Options.lb LinuxBIOSv2/src/mainboard/bitworks/ims/Options.lb 8c8 < uses CONFIG_ROM_STREAM
uses CONFIG_ROM_PAYLOAD 23c23,24 < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 102c103 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/broadcom/blast/cache_as_ram_auto.c LinuxBIOSv2/src/mainboard/broadcom/blast/cache_as_ram_auto.c 7c7 < #define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1 50c50 < #include "superio/NSC/pc87417/pc87417_early_serial.c"
#include "superio/nsc/pc87417/pc87417_early_serial.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/broadcom/blast/Config.lb LinuxBIOSv2/src/mainboard/broadcom/blast/Config.lb 18c18 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 220c220 < chip superio/NSC/pc87417
chip superio/nsc/pc87417
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/broadcom/blast/get_bus_conf.c LinuxBIOSv2/src/mainboard/broadcom/blast/get_bus_conf.c 10,11c10,23 < unsigned sblk; < unsigned pci1234[] = ---
#include <cpu/amd/amdk8_sysconf.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default unsigned char bus_isa = 10; unsigned char bus_bcm5780[7]; unsigned char bus_bcm5785_0 = 1; unsigned char bus_bcm5785_1 = 8; unsigned char bus_bcm5785_1_1 = 9; unsigned apicid_bcm5785[3];
unsigned pci1234x[] = 23,25c35 < unsigned hc_possible_num; < unsigned sbdn; < unsigned hcdn[] =
unsigned hcdnx[] = 36,45d45 < < // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables < //busnum is default < unsigned char bus_isa = 10; < unsigned char bus_bcm5780[7]; < unsigned char bus_bcm5785_0 = 1; < unsigned char bus_bcm5785_1 = 8; < unsigned char bus_bcm5785_1_1 = 9; < unsigned apicid_bcm5785[3]; < 64c64,68 < hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; }
68,69c72,73 < sbdn = (hcdn[0] >> 8) & 0xff; < sbdn2 = hcdn[0] & 0xff; // bcm5780 ---
sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780
71c75 < bus_bcm5785_0 = (pci1234[0] >> 16) & 0xff; ---
bus_bcm5785_0 = (sysconf.pci1234[0] >> 16) & 0xff; 75c79 < dev = dev_find_slot(bus_bcm5785_0, PCI_DEVFN(sbdn,0));
dev = dev_find_slot(bus_bcm5785_0, PCI_DEVFN(sysconf.sbdn,0));
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/broadcom/blast/irq_tables.c LinuxBIOSv2/src/mainboard/broadcom/blast/irq_tables.c 13,15c13 < extern unsigned pci1234[]; < extern unsigned sbdn; < extern unsigned hcdn[]; ---
#include <cpu/amd/amdk8_sysconf.h> 74c72 < pirq->rtr_devfn = (sbdn<<3)|0;
pirq->rtr_devfn = (sysconf.sbdn<<3)|0; 90c88 < write_pirq_info(pirq_info, bus_bcm5785_0, (sbdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
write_pirq_info(pirq_info, bus_bcm5785_0, (sysconf.sbdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/broadcom/blast/mainboard.c LinuxBIOSv2/src/mainboard/broadcom/blast/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 10c6 < CHIP_NAME("Broadcom blast mainboard")
CHIP_NAME("Broadcom Blast Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/broadcom/blast/mptable.c LinuxBIOSv2/src/mainboard/broadcom/blast/mptable.c 11,13c11 < extern unsigned pci1234[]; < extern unsigned sbdn; < extern unsigned hcdn[];
#include <cpu/amd/amdk8_sysconf.h> 98c96 < smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_bcm5785_0, ((1+sbdn)<<2)|1, apicid_bcm5785[0], 0xe); // IDE
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, apicid_bcm5785[0], 0xe); // IDE 107c105 < smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sbdn)<<2)|i, apicid_bcm5785[0], 0xa); //
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); //
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/broadcom/blast/Options.lb LinuxBIOSv2/src/mainboard/broadcom/blast/Options.lb 20,21c20,22 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START ---
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 56c57 < uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK 59c60 < uses K8_SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_ON_BUS0 131c132 < default K8_HW_MEM_HOLE_SIZEK=0x100000
default HW_MEM_HOLE_SIZEK=0x100000 144c145 < default K8_SB_HT_CHAIN_ON_BUS0=1
default SB_HT_CHAIN_ON_BUS0=1 198c199 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/dell/s1850/auto.c LinuxBIOSv2/src/mainboard/dell/s1850/auto.c 14c14 < #include "northbridge/intel/E7520/raminit.h"
#include "northbridge/intel/e7520/raminit.h" 23c23 < #include "northbridge/intel/E7520/memory_initialized.c"
#include "northbridge/intel/e7520/memory_initialized.c" 72c72 < #include "northbridge/intel/E7520/raminit.c"
#include "northbridge/intel/e7520/raminit.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/dell/s1850/Config.lb LinuxBIOSv2/src/mainboard/dell/s1850/Config.lb 23c23 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 28c28 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 135c135 < chip northbridge/intel/E7520 # mch
chip northbridge/intel/e7520 # mch 150c150 < chip superio/NSC/pc8374
chip superio/nsc/pc8374
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/dell/s1850/failover.c LinuxBIOSv2/src/mainboard/dell/s1850/failover.c 12c12 < #include "northbridge/intel/E7520/memory_initialized.c" ---
#include "northbridge/intel/e7520/memory_initialized.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/dell/s1850/mainboard.c LinuxBIOSv2/src/mainboard/dell/s1850/mainboard.c 1d0 < #include <console/console.h> 3,6d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> < #include <cpu/x86/msr.h> 10c5 < CHIP_NAME("Dell S1850")
CHIP_NAME("Dell S1850 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/dell/s1850/Options.lb LinuxBIOSv2/src/mainboard/dell/s1850/Options.lb 18,19c18,20 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 157c158 < default CONFIG_ROM_STREAM=1
default CONFIG_ROM_PAYLOAD=1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/densitron/dpx114/Config.lb LinuxBIOSv2/src/mainboard/densitron/dpx114/Config.lb 18c18 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/densitron/dpx114/mainboard.c LinuxBIOSv2/src/mainboard/densitron/dpx114/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 9c5 < CHIP_NAME("Densitron DPX114 mainboard ")
CHIP_NAME("Densitron DPX114 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/densitron/dpx114/Options.lb LinuxBIOSv2/src/mainboard/densitron/dpx114/Options.lb 8c8 < uses CONFIG_ROM_STREAM
uses CONFIG_ROM_PAYLOAD 23c23,24 < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 100c101 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/digitallogic/adl855pc/Config.lb LinuxBIOSv2/src/mainboard/digitallogic/adl855pc/Config.lb 18c18 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/digitallogic/adl855pc/mainboard.c LinuxBIOSv2/src/mainboard/digitallogic/adl855pc/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 9c5 < CHIP_NAME("Digital Logic ADL855PC mainboard ")
CHIP_NAME("DIGITAL-LOGIC ADL855PC Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/digitallogic/adl855pc/Options.lb LinuxBIOSv2/src/mainboard/digitallogic/adl855pc/Options.lb 8c8 < uses CONFIG_ROM_STREAM
uses CONFIG_ROM_PAYLOAD 24c24,25 < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 105c106 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/digitallogic/msm586seg/Config.lb LinuxBIOSv2/src/mainboard/digitallogic/msm586seg/Config.lb 20c20 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 25c25 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/digitallogic/msm586seg/mainboard.c LinuxBIOSv2/src/mainboard/digitallogic/msm586seg/mainboard.c 145c145 < CHIP_NAME("Digital Logic MSM586SEG mainboard ")
CHIP_NAME("DIGITAL-LOGIC MSM586SEG Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/digitallogic/msm586seg/Options.lb LinuxBIOSv2/src/mainboard/digitallogic/msm586seg/Options.lb 9c9 < uses CONFIG_ROM_STREAM
uses CONFIG_ROM_PAYLOAD 25c25,26 < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 113c114 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 Only in LinuxBIOSv2/src/mainboard/digitallogic: msm800sev diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/eaglelion/5bcm/auto.c LinuxBIOSv2/src/mainboard/eaglelion/5bcm/auto.c 13c13 < #include "superio/NSC/pc97317/pc97317_early_serial.c"
#include "superio/nsc/pc97317/pc97317_early_serial.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/eaglelion/5bcm/Config.lb LinuxBIOSv2/src/mainboard/eaglelion/5bcm/Config.lb 17c17 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 133c133 < chip superio/NSC/pc97317
chip superio/nsc/pc97317
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/eaglelion/5bcm/mainboard.c LinuxBIOSv2/src/mainboard/eaglelion/5bcm/mainboard.c 1d0 < #include <console/console.h> 3,6d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> < #include <arch/io.h> 10c5 < CHIP_NAME("Eaglelion 5BCM mainboard ") ---
CHIP_NAME("Eaglelion 5BCM Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/eaglelion/5bcm/Options.lb LinuxBIOSv2/src/mainboard/eaglelion/5bcm/Options.lb 8c8 < uses CONFIG_ROM_STREAM
uses CONFIG_ROM_PAYLOAD 23c23,24 < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 108c109 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/embeddedplanet/ep405pc/Options.lb LinuxBIOSv2/src/mainboard/embeddedplanet/ep405pc/Options.lb 23c23 < uses CONFIG_FS_STREAM
uses CONFIG_FS_PAYLOAD 26a27 uses CONFIG_COMPRESSED_PAYLOAD_LZMA 96c97 < default CONFIG_FS_STREAM=1
default CONFIG_FS_PAYLOAD=1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/emulation/qemu-i386/Config.lb LinuxBIOSv2/src/mainboard/emulation/qemu-i386/Config.lb 6,14c6,7 < default FALLBACK_SIZE = 128*1024 < < if USE_FALLBACK_IMAGE < default ROM_SECTION_SIZE = 128 * 1024 # FALLBACK_SIZE < default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) < else < default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) < default ROM_SECTION_OFFSET = 0 < end
default ROM_SECTION_SIZE = ROM_SIZE default ROM_SECTION_OFFSET = 0 21c14 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 26c19 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 85,91c78,79 < if USE_FALLBACK_IMAGE < mainboardinit cpu/x86/16bit/reset16.inc < ldscript /cpu/x86/16bit/reset16.lds < else < mainboardinit cpu/x86/32bit/reset32.inc < ldscript /cpu/x86/32bit/reset32.lds < end
mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds 103,112d90 < ### This is the early phase of linuxBIOS startup < ### Things are delicate and we test to see if we should < ### failover to another image. < ### < if USE_FALLBACK_IMAGE < ldscript /arch/i386/lib/failover.lds < mainboardinit ./failover.inc < end < < ### diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/emulation/qemu-i386/irq_tables.c LinuxBIOSv2/src/mainboard/emulation/qemu-i386/irq_tables.c 3,5c3,5 < Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up < < Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
* Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM 13,18c13,18 < 32+16*5, /* there can be total 5 devices on the bus */ < 0, /* Where the interrupt router lies (bus) */ < 0x88, /* Where the interrupt router lies (dev) */ < 0x1c20, /* IRQs devoted exclusively to PCI usage */ < 0x1106, /* Vendor */ < 0x8231, /* Device */
32+16*6, /* there can be total 6 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x01<<3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x7000, /* Device */ 21c21 < 0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
0x7, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ 23,30c23,29 < /* 8231 ethernet */ < {0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0}, < /* 8231 internal */ < {0,0x88, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0}, < /* PCI slot */ < {0,0xa0, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0}, < {0,0x50, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0}, < {0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x01<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x0, 0x0}, {0x00,(0x02<<3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x1, 0x0}, {0x00,(0x03<<3)|0x0, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0x0def8}}, 0x2, 0x0}, {0x00,(0x04<<3)|0x0, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0x0def8}}, 0x3, 0x0}, {0x00,(0x05<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x4, 0x0}, {0x00,(0x06<<3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x5, 0x0},
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/emulation/qemu-i386/mainboard.c LinuxBIOSv2/src/mainboard/emulation/qemu-i386/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 9c5 < CHIP_NAME("qemu mainboard ") ---
CHIP_NAME("QEMU Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/emulation/qemu-i386/Options.lb LinuxBIOSv2/src/mainboard/emulation/qemu-i386/Options.lb 9c9,12 < uses CONFIG_ROM_STREAM
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD uses CONFIG_ROM_PAYLOAD 24c27 < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD_START 105c108 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/ibm/e325/auto.c LinuxBIOSv2/src/mainboard/ibm/e325/auto.c 16d15 < #include "northbridge/amd/amdk8/incoherent_ht.c" 25c24 < #include "superio/NSC/pc87366/pc87366_early_serial.c"
#include "superio/nsc/pc87366/pc87366_early_serial.c" 28d26 < #include "cpu/amd/dualcore/dualcore.c" 127a126 #include "northbridge/amd/amdk8/incoherent_ht.c" 129a129 #include "cpu/amd/dualcore/dualcore.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/ibm/e325/Config.lb LinuxBIOSv2/src/mainboard/ibm/e325/Config.lb 18c18 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 150c150 < chip superio/NSC/pc87366
chip superio/nsc/pc87366
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/ibm/e325/mainboard.c LinuxBIOSv2/src/mainboard/ibm/e325/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 9c5 < CHIP_NAME("IBM E325 mainboard ") ---
CHIP_NAME("IBM eServer 325 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/ibm/e325/Options.lb LinuxBIOSv2/src/mainboard/ibm/e325/Options.lb 18,19c18,20 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 149c150 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/ibm/e326/auto.c LinuxBIOSv2/src/mainboard/ibm/e326/auto.c 16d15 < #include "northbridge/amd/amdk8/incoherent_ht.c" 25c24 < #include "superio/NSC/pc87366/pc87366_early_serial.c"
#include "superio/nsc/pc87366/pc87366_early_serial.c" 28d26 < #include "cpu/amd/dualcore/dualcore.c" 127a126 #include "northbridge/amd/amdk8/incoherent_ht.c" 129a129 #include "cpu/amd/dualcore/dualcore.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/ibm/e326/Config.lb LinuxBIOSv2/src/mainboard/ibm/e326/Config.lb 18c18 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 160c160 < chip superio/NSC/pc87366
chip superio/nsc/pc87366
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/ibm/e326/mainboard.c LinuxBIOSv2/src/mainboard/ibm/e326/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 9c5 < CHIP_NAME("IBM E326 mainboard ") ---
CHIP_NAME("IBM eServer 326 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/ibm/e326/Options.lb LinuxBIOSv2/src/mainboard/ibm/e326/Options.lb 18,19c18,20 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 155c156 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 Only in LinuxBIOSv2/src/mainboard: iei diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/intel/jarrell/auto.c LinuxBIOSv2/src/mainboard/intel/jarrell/auto.c 14,15c14,15 < #include "northbridge/intel/E7520/raminit.h" < #include "superio/NSC/pc87427/pc87427.h"
#include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" 22,23c22,23 < #include "superio/NSC/pc87427/pc87427_early_init.c" < #include "northbridge/intel/E7520/memory_initialized.c"
#include "superio/nsc/pc87427/pc87427_early_init.c" #include "northbridge/intel/e7520/memory_initialized.c" 50c50 < #include "northbridge/intel/E7520/raminit.c"
#include "northbridge/intel/e7520/raminit.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/intel/jarrell/Config.lb LinuxBIOSv2/src/mainboard/intel/jarrell/Config.lb 23c23 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 28c28 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 135c135 < chip northbridge/intel/E7520
chip northbridge/intel/e7520 166c166 < chip superio/NSC/pc87427
chip superio/nsc/pc87427
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/intel/jarrell/failover.c LinuxBIOSv2/src/mainboard/intel/jarrell/failover.c 12c12 < #include "northbridge/intel/E7520/memory_initialized.c" ---
#include "northbridge/intel/e7520/memory_initialized.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/intel/jarrell/mainboard.c LinuxBIOSv2/src/mainboard/intel/jarrell/mainboard.c 1d0 < #include <console/console.h> 3,7d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> < #include <cpu/x86/msr.h> < #include <arch/io.h> 11c5 < CHIP_NAME("Intel Jarell mainboard ")
CHIP_NAME("Intel Jarell Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/intel/jarrell/Options.lb LinuxBIOSv2/src/mainboard/intel/jarrell/Options.lb 18,19c18,20 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 171c172 < default CONFIG_ROM_STREAM=1
default CONFIG_ROM_PAYLOAD=1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/intel/xe7501devkit/Config.lb LinuxBIOSv2/src/mainboard/intel/xe7501devkit/Config.lb 24c24 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/intel/xe7501devkit/mainboard.c LinuxBIOSv2/src/mainboard/intel/xe7501devkit/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 10c6 < CHIP_NAME("Intel Xeon E7501 DevKit mainboard")
CHIP_NAME("Intel Xeon E7501 DevKit Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/intel/xe7501devkit/Options.lb LinuxBIOSv2/src/mainboard/intel/xe7501devkit/Options.lb 12c12,13 < uses CONFIG_ROM_STREAM
uses CONFIG_ROM_PAYLOAD uses CONFIG_COMPRESSED_PAYLOAD_LZMA 48c49 < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD_START 170c171 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 Only in LinuxBIOSv2/src/mainboard: iwill Only in LinuxBios_mine/src/mainboard: Iwill diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/lippert/frontrunner/Config.lb LinuxBIOSv2/src/mainboard/lippert/frontrunner/Config.lb 17c17 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/lippert/frontrunner/mainboard.c LinuxBIOSv2/src/mainboard/lippert/frontrunner/mainboard.c 1d0 < #include <console/console.h> 3,6d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> < #include <arch/io.h> 10c5 < CHIP_NAME("Lippert frontrunner mainboard ")
CHIP_NAME("Lippert Cool Frontrunner Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/lippert/frontrunner/Options.lb LinuxBIOSv2/src/mainboard/lippert/frontrunner/Options.lb 8c8 < uses CONFIG_ROM_STREAM
uses CONFIG_ROM_PAYLOAD 23c23,24 < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 108c109 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/motorola/sandpoint/clock.c LinuxBIOSv2/src/mainboard/motorola/sandpoint/clock.c 1,2c1,18 < /* Copyright 2000 AG Electronics Ltd. */ < /* This code is distributed without warranty under the GPL v2 (see COPYING) */
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 2000 AG Electronics Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/motorola/sandpoint/flash/amd800.c LinuxBIOSv2/src/mainboard/motorola/sandpoint/flash/amd800.c 1,2c1,18 < /* Copyright 2000 AG Electronics Ltd. */ < /* This code is distributed without warranty under the GPL v2 (see COPYING) */
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 2000 AG Electronics Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/motorola/sandpoint/flash/flash.c LinuxBIOSv2/src/mainboard/motorola/sandpoint/flash/flash.c 1,2c1,18 < /* Copyright 2000 AG Electronics Ltd. */ < /* This code is distributed without warranty under the GPL v2 (see COPYING) */
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 2000 AG Electronics Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/motorola/sandpoint/flash.h LinuxBIOSv2/src/mainboard/motorola/sandpoint/flash.h 1,2c1,18 < /* Copyright 2000 AG Electronics Ltd. */ < /* This code is distributed without warranty under the GPL v2 (see COPYING) */
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 2000 AG Electronics Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/motorola/sandpoint/nvram/nvram.c LinuxBIOSv2/src/mainboard/motorola/sandpoint/nvram/nvram.c 1,2c1,18 < /* Copyright 2000 AG Electronics Ltd. */ < /* This code is distributed without warranty under the GPL v2 (see COPYING) */
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 2000 AG Electronics Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/motorola/sandpoint/nvram.h LinuxBIOSv2/src/mainboard/motorola/sandpoint/nvram.h 1,2c1,19 < /* Copyright 2000 AG Electronics Ltd. */ < /* This code is distributed without warranty under the GPL v2 (see COPYING) */
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 2000 AG Electronics Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/motorola/sandpoint/Options.lb LinuxBIOSv2/src/mainboard/motorola/sandpoint/Options.lb 25c25 < uses CONFIG_FS_STREAM ---
uses CONFIG_FS_PAYLOAD 86c86 < default CONFIG_FS_STREAM=1
default CONFIG_FS_PAYLOAD=1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Config.lb LinuxBIOSv2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Config.lb 17c17 < chip superio/NSC/pc97307
chip superio/nsc/pc97307
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb LinuxBIOSv2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb 20c20 < uses CONFIG_FS_STREAM ---
uses CONFIG_FS_PAYLOAD 23a24 uses CONFIG_COMPRESSED_PAYLOAD_LZMA 81c82 < default CONFIG_FS_STREAM=1
default CONFIG_FS_PAYLOAD=1 Only in LinuxBIOSv2/src/mainboard: msi diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/newisys/khepri/auto.c LinuxBIOSv2/src/mainboard/newisys/khepri/auto.c 21d20 < #include "northbridge/amd/amdk8/incoherent_ht.c" 23c22 < #include "superio/NSC/pc87360/pc87360_early_serial.c"
#include "superio/nsc/pc87360/pc87360_early_serial.c" 26d24 < #include "cpu/amd/dualcore/dualcore.c" 82a81 #include "northbridge/amd/amdk8/incoherent_ht.c" 87a87 #include "cpu/amd/dualcore/dualcore.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/newisys/khepri/Config.lb LinuxBIOSv2/src/mainboard/newisys/khepri/Config.lb 18c18 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 151c151 < chip superio/NSC/pc87360
chip superio/nsc/pc87360
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/newisys/khepri/mainboard.c LinuxBIOSv2/src/mainboard/newisys/khepri/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 9c5 < CHIP_NAME("Newisys 2100 mainboard") ---
CHIP_NAME("Newisys 2100 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/newisys/khepri/Options.lb LinuxBIOSv2/src/mainboard/newisys/khepri/Options.lb 18,19c18,20 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 113,114c114,115 < default MAINBOARD_PART_NUMBER="KHEPRI" < default MAINBOARD_VENDOR="NEWISYS"
default MAINBOARD_PART_NUMBER="Khepri" default MAINBOARD_VENDOR="Newisys" 146c147 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 Only in LinuxBIOSv2/src/mainboard/olpc: btest diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/olpc/rev_a/cmos.layout LinuxBIOSv2/src/mainboard/olpc/rev_a/cmos.layout 38a39 440 1 e 0 dcon_present diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/olpc/rev_a/Config.lb LinuxBIOSv2/src/mainboard/olpc/rev_a/Config.lb 17c17 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 137a138,148 # 0x51400025 (IRQ Mapper LPC Mask)= 0x00001002 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # 0x5140004E (LPC Serial IRQ Control) = 0xEFFD0080. # Frame Pulse Width = 4clocks # IRQ Data Frames = 17Frames # SIRQ Mode = continous , It would be better if the EC could operate in # Active(Quiet) mode. Save power.... # SIRQ Enable = Enabled # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK register "lpc_irq" = "0x00001002" register "lpc_serirq_enable" = "0xEFFD0080" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/olpc/rev_a/mainboard.c LinuxBIOSv2/src/mainboard/olpc/rev_a/mainboard.c 6a7 #include <pc80/mc146818rtc.h> 7a9 #include "../southbridge/amd/cs5536/cs5536_smbus2.h" 8a11 /* Borrowed from mc146818rtc.c */ 9a13,69 #define CMOS_READ(addr) ({ \ outb((addr),RTC_PORT(0)); \ inb(RTC_PORT(1)); \ })
#define CMOS_WRITE(val, addr) ({ \ outb((addr),RTC_PORT(0)); \ outb((val),RTC_PORT(1)); \ })
static void write_bit(unsigned char val) {
unsigned char byte = CMOS_READ(440 / 8);
/* Don't change it if its already set */
if ((byte & 1) == (val & 1)) return;
byte &= ~1; byte |= val & 1; CMOS_WRITE(val, 440/8); }
static unsigned short _getsmbusbase(void) { unsigned devfn = PCI_DEVFN(0xf, 0); device_t dev = dev_find_slot(0x0, devfn); unsigned long addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
return (unsigned short) (addr & ~1); }
static void init_dcon(void) {
int ret = 1; unsigned short rev = 0; unsigned short iobase = _getsmbusbase();
printk_debug("CHECKING FOR DCON (%x)\n", iobase);
/* Get the IO base for the SMBUS */
rev = do_smbus_read_word(iobase, 0x0D << 1, 0x00);
if (rev & 0xDC00) { printk_debug("DCON FOUND - REV %x\n", rev);
/* Enable the DCON */ ret = do_smbus_write_word(iobase, 0x0D << 1, 0x01, 0x0069); if (ret != 0) printk_debug("DCON ENABLE FAILED\n", ret); } else printk_debug("DCON NOT FOUND (%x)\n", rev);
write_bit(rev > 0 ? 1 : 0); } 34a95,96
init_dcon(); 44c106 < CHIP_NAME("olpc rev_a mainboard ")
CHIP_NAME("OLPC rev_a Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/olpc/rev_a/Options.lb LinuxBIOSv2/src/mainboard/olpc/rev_a/Options.lb 8c8 < uses CONFIG_ROM_STREAM
uses CONFIG_ROM_PAYLOAD 23,25c23,26 < uses CONFIG_ROM_STREAM_START < uses CONFIG_COMPRESSED_ROM_STREAM < uses CONFIG_PRECOMPRESSED_ROM_STREAM
uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD 110c111 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/sunw/ultra40/auto.c LinuxBIOSv2/src/mainboard/sunw/ultra40/auto.c 94c94 < #define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/sunw/ultra40/cache_as_ram_auto.c LinuxBIOSv2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c 9c9 < #define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/sunw/ultra40/Config.lb LinuxBIOSv2/src/mainboard/sunw/ultra40/Config.lb 18,19c18,19 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1 24c24 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/sunw/ultra40/failover.c LinuxBIOSv2/src/mainboard/sunw/ultra40/failover.c 25a26,29 #define SUPERIO_COM1_DEV PNP_DEV(0x2e, LPC47B397_SP1)
#define SUPERIO_COM1_IO_BASE 0x3f8
44c48 < lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); ---
lpc47b397_enable_serial(SUPERIO_COM1_DEV, SUPERIO_COM1_IO_BASE);
45a50,51
#if 0 /* what's this? 48a55,56 */ #endif diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/sunw/ultra40/mainboard.c LinuxBIOSv2/src/mainboard/sunw/ultra40/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 10c6 < CHIP_NAME("Sun ultra40 mainboard")
CHIP_NAME("Sun Ultra 40 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/sunw/ultra40/Options.lb LinuxBIOSv2/src/mainboard/sunw/ultra40/Options.lb 19,20c19,21 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 55c56 < uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK 69c70 < uses K8_SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_ON_BUS0 137c138 < default K8_HW_MEM_HOLE_SIZEK=0x100000
default HW_MEM_HOLE_SIZEK=0x100000 149c150 < default K8_SB_HT_CHAIN_ON_BUS0=2
default SB_HT_CHAIN_ON_BUS0=2 215c216 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dai_g/auto.c LinuxBIOSv2/src/mainboard/supermicro/x6dai_g/auto.c 14c14 < #include "northbridge/intel/E7525/raminit.h"
#include "northbridge/intel/e7525/raminit.h" 22c22 < #include "northbridge/intel/E7525/memory_initialized.c"
#include "northbridge/intel/e7525/memory_initialized.c" 53c53 < #include "northbridge/intel/E7525/raminit.c"
#include "northbridge/intel/e7525/raminit.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dai_g/Config.lb LinuxBIOSv2/src/mainboard/supermicro/x6dai_g/Config.lb 23c23 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 28c28 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 135c135 < chip northbridge/intel/E7525 # mch
chip northbridge/intel/e7525 # mch diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dai_g/failover.c LinuxBIOSv2/src/mainboard/supermicro/x6dai_g/failover.c 12c12 < #include "northbridge/intel/E7525/memory_initialized.c"
#include "northbridge/intel/e7525/memory_initialized.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dai_g/mainboard.c LinuxBIOSv2/src/mainboard/supermicro/x6dai_g/mainboard.c 1d0 < #include <console/console.h> 3,6d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> < #include <cpu/x86/msr.h> 10c5 < CHIP_NAME("Supermicro X6DAI_G mainboard ")
CHIP_NAME("Supermicro X6DAi-G Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dai_g/Options.lb LinuxBIOSv2/src/mainboard/supermicro/x6dai_g/Options.lb 18,19c18,20 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 157c158 < default CONFIG_ROM_STREAM=1
default CONFIG_ROM_PAYLOAD=1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhe_g/auto.c LinuxBIOSv2/src/mainboard/supermicro/x6dhe_g/auto.c 14c14 < #include "northbridge/intel/E7520/raminit.h"
#include "northbridge/intel/e7520/raminit.h" 23c23 < #include "northbridge/intel/E7520/memory_initialized.c"
#include "northbridge/intel/e7520/memory_initialized.c" 71c71 < #include "northbridge/intel/E7520/raminit.c"
#include "northbridge/intel/e7520/raminit.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhe_g/Config.lb LinuxBIOSv2/src/mainboard/supermicro/x6dhe_g/Config.lb 23c23 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 28c28 < default _ROMBASE =( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE =( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 135c135 < chip northbridge/intel/E7520 # MCH
chip northbridge/intel/e7520 # MCH diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhe_g/failover.c LinuxBIOSv2/src/mainboard/supermicro/x6dhe_g/failover.c 12c12 < #include "northbridge/intel/E7520/memory_initialized.c"
#include "northbridge/intel/e7520/memory_initialized.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhe_g/mainboard.c LinuxBIOSv2/src/mainboard/supermicro/x6dhe_g/mainboard.c 1d0 < #include <console/console.h> 3,6d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> < #include <cpu/x86/msr.h> 10c5 < CHIP_NAME("Supermicro X6DHE_G mainboard")
CHIP_NAME("Supermicro X6DHE-G Mainboard")
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhe_g/Options.lb LinuxBIOSv2/src/mainboard/supermicro/x6dhe_g/Options.lb 18,19c18,20 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START ---
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 157c158 < default CONFIG_ROM_STREAM=1
default CONFIG_ROM_PAYLOAD=1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhe_g2/auto.c LinuxBIOSv2/src/mainboard/supermicro/x6dhe_g2/auto.c 14,15c14,15 < #include "northbridge/intel/E7520/raminit.h" < #include "superio/NSC/pc87427/pc87427.h"
#include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" 22,23c22,23 < #include "superio/NSC/pc87427/pc87427_early_init.c" < #include "northbridge/intel/E7520/memory_initialized.c"
#include "superio/nsc/pc87427/pc87427_early_init.c" #include "northbridge/intel/e7520/memory_initialized.c" 71c71 < #include "northbridge/intel/E7520/raminit.c"
#include "northbridge/intel/e7520/raminit.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhe_g2/auto.updated.c LinuxBIOSv2/src/mainboard/supermicro/x6dhe_g2/auto.updated.c 14c14 < #include "northbridge/intel/E7520/raminit.h"
#include "northbridge/intel/e7520/raminit.h" 23c23 < #include "northbridge/intel/E7520/memory_initialized.c"
#include "northbridge/intel/e7520/memory_initialized.c" 71c71 < #include "northbridge/intel/E7520/raminit.c"
#include "northbridge/intel/e7520/raminit.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhe_g2/Config.lb LinuxBIOSv2/src/mainboard/supermicro/x6dhe_g2/Config.lb 23c23 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 28c28 < default _ROMBASE =( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE =( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 135c135 < chip northbridge/intel/E7520 # MCH
chip northbridge/intel/e7520 # MCH 170c170 < chip superio/NSC/pc87427
chip superio/nsc/pc87427
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhe_g2/failover.c LinuxBIOSv2/src/mainboard/supermicro/x6dhe_g2/failover.c 12c12 < #include "northbridge/intel/E7520/memory_initialized.c" ---
#include "northbridge/intel/e7520/memory_initialized.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhe_g2/mainboard.c LinuxBIOSv2/src/mainboard/supermicro/x6dhe_g2/mainboard.c 1d0 < #include <console/console.h> 3,6d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> < #include <cpu/x86/msr.h> 10c5 < CHIP_NAME("Supermicro X6DHE_G2 mainboard")
CHIP_NAME("Supermicro X6DHE-G2 Mainboard")
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhe_g2/Options.lb LinuxBIOSv2/src/mainboard/supermicro/x6dhe_g2/Options.lb 18,19c18,20 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START ---
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 157c158 < default CONFIG_ROM_STREAM=1
default CONFIG_ROM_PAYLOAD=1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhr_ig/auto.c LinuxBIOSv2/src/mainboard/supermicro/x6dhr_ig/auto.c 14c14 < #include "northbridge/intel/E7520/raminit.h"
#include "northbridge/intel/e7520/raminit.h" 23c23 < #include "northbridge/intel/E7520/memory_initialized.c"
#include "northbridge/intel/e7520/memory_initialized.c" 72c72 < #include "northbridge/intel/E7520/raminit.c"
#include "northbridge/intel/e7520/raminit.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhr_ig/Config.lb LinuxBIOSv2/src/mainboard/supermicro/x6dhr_ig/Config.lb 23c23 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 28c28 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 135c135 < chip northbridge/intel/E7520 # mch
chip northbridge/intel/e7520 # mch diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhr_ig/failover.c LinuxBIOSv2/src/mainboard/supermicro/x6dhr_ig/failover.c 12c12 < #include "northbridge/intel/E7520/memory_initialized.c"
#include "northbridge/intel/e7520/memory_initialized.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhr_ig/mainboard.c LinuxBIOSv2/src/mainboard/supermicro/x6dhr_ig/mainboard.c 1d0 < #include <console/console.h> 3,6d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> < #include <cpu/x86/msr.h> 10c5 < CHIP_NAME("Supermicro x6dhr-ig")
CHIP_NAME("Supermicro X6DHR-iG Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhr_ig/Options.lb LinuxBIOSv2/src/mainboard/supermicro/x6dhr_ig/Options.lb 18,19c18,20 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 157c158 < default CONFIG_ROM_STREAM=1
default CONFIG_ROM_PAYLOAD=1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhr_ig2/auto.c LinuxBIOSv2/src/mainboard/supermicro/x6dhr_ig2/auto.c 14c14 < #include "northbridge/intel/E7520/raminit.h"
#include "northbridge/intel/e7520/raminit.h" 23c23 < #include "northbridge/intel/E7520/memory_initialized.c"
#include "northbridge/intel/e7520/memory_initialized.c" 72c72 < #include "northbridge/intel/E7520/raminit.c"
#include "northbridge/intel/e7520/raminit.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhr_ig2/Config.lb LinuxBIOSv2/src/mainboard/supermicro/x6dhr_ig2/Config.lb 23c23 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 28c28 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 135c135 < chip northbridge/intel/E7520 # mch
chip northbridge/intel/e7520 # mch diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhr_ig2/failover.c LinuxBIOSv2/src/mainboard/supermicro/x6dhr_ig2/failover.c 12c12 < #include "northbridge/intel/E7520/memory_initialized.c"
#include "northbridge/intel/e7520/memory_initialized.c" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhr_ig2/mainboard.c LinuxBIOSv2/src/mainboard/supermicro/x6dhr_ig2/mainboard.c 1d0 < #include <console/console.h> 3,6d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> < #include <cpu/x86/msr.h> 10c5 < CHIP_NAME("Supermicro x6dhr-ig2")
CHIP_NAME("Supermicro X6DHR-iG2 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/supermicro/x6dhr_ig2/Options.lb LinuxBIOSv2/src/mainboard/supermicro/x6dhr_ig2/Options.lb 18,19c18,20 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 157c158 < default CONFIG_ROM_STREAM=1
default CONFIG_ROM_PAYLOAD=1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/technologic/ts5300/Config.lb LinuxBIOSv2/src/mainboard/technologic/ts5300/Config.lb 20c20 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 25c25 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/technologic/ts5300/mainboard.c LinuxBIOSv2/src/mainboard/technologic/ts5300/mainboard.c 152c152 < CHIP_NAME("Technologic Systems TS5300 mainboard ")
CHIP_NAME("Technologic Systems TS-5300 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/technologic/ts5300/Options.lb LinuxBIOSv2/src/mainboard/technologic/ts5300/Options.lb 9,10c9 < uses CONFIG_COMPRESSED_ROM_STREAM < uses CONFIG_ROM_STREAM
uses CONFIG_ROM_PAYLOAD 26c25,26 < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 137,138c137 < default CONFIG_COMPRESSED_ROM_STREAM = 1 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/totalimpact/briq/Options.lb LinuxBIOSv2/src/mainboard/totalimpact/briq/Options.lb 21c21,22 < uses CONFIG_IDE_STREAM
uses CONFIG_IDE_PAYLOAD uses CONFIG_COMPRESSED_PAYLOAD_LZMA 82c83 < default CONFIG_IDE_STREAM=1
default CONFIG_IDE_PAYLOAD=1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2735/Config.lb LinuxBIOSv2/src/mainboard/tyan/s2735/Config.lb 18,19c18,19 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1 24c24 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2735/mainboard.c LinuxBIOSv2/src/mainboard/tyan/s2735/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 10c6 < CHIP_NAME("Tyan s2735 mainboard")
CHIP_NAME("Tyan S2735 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2735/Options.lb LinuxBIOSv2/src/mainboard/tyan/s2735/Options.lb 20,21c20,22 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 192c193 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2850/cache_as_ram_auto.c LinuxBIOSv2/src/mainboard/tyan/s2850/cache_as_ram_auto.c 82,83d81 < #define K8_4RANK_DIMM_SUPPORT 1 < diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2850/Config.lb LinuxBIOSv2/src/mainboard/tyan/s2850/Config.lb 18c18 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2850/mainboard.c LinuxBIOSv2/src/mainboard/tyan/s2850/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 10c6 < CHIP_NAME("Tyan s2850 mainboard")
CHIP_NAME("Tyan S2850 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2850/Options.lb LinuxBIOSv2/src/mainboard/tyan/s2850/Options.lb 19,20c19,21 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 55c56 < uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK 125c126 < default K8_HW_MEM_HOLE_SIZEK=0x100000
default HW_MEM_HOLE_SIZEK=0x100000 138c139 < default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0 183c184 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2875/cache_as_ram_auto.c LinuxBIOSv2/src/mainboard/tyan/s2875/cache_as_ram_auto.c 71c71 < #define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2875/Config.lb LinuxBIOSv2/src/mainboard/tyan/s2875/Config.lb 18c18 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2875/mainboard.c LinuxBIOSv2/src/mainboard/tyan/s2875/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 10c6 < CHIP_NAME("Tyan s2875 mainboard")
CHIP_NAME("Tyan S2875 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2875/Options.lb LinuxBIOSv2/src/mainboard/tyan/s2875/Options.lb 19,20c19,21 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 55c56 < uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK 126c127 < default K8_HW_MEM_HOLE_SIZEK=0x100000
default HW_MEM_HOLE_SIZEK=0x100000 139c140 < default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0 184c185 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2880/cache_as_ram_auto.c LinuxBIOSv2/src/mainboard/tyan/s2880/cache_as_ram_auto.c 72c72 < #define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2880/Config.lb LinuxBIOSv2/src/mainboard/tyan/s2880/Config.lb 18c18 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2880/mainboard.c LinuxBIOSv2/src/mainboard/tyan/s2880/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 10c6 < CHIP_NAME("Tyan s2880 mainboard")
CHIP_NAME("Tyan S2880 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2880/Options.lb LinuxBIOSv2/src/mainboard/tyan/s2880/Options.lb 19,20c19,21 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 55c56 < uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK 125c126 < default K8_HW_MEM_HOLE_SIZEK=0x100000
default HW_MEM_HOLE_SIZEK=0x100000 138c139 < default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0 183c184 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2881/auto.c LinuxBIOSv2/src/mainboard/tyan/s2881/auto.c 23c23 < #include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/cpu_rev.c" 110c110 < #define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2881/cache_as_ram_auto.c LinuxBIOSv2/src/mainboard/tyan/s2881/cache_as_ram_auto.c 4c4 < #define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1 21a22,32 #if 0 static void post_code(uint8_t value) { #if 1 int i; for(i=0;i<0x80000;i++) { outb(value, 0x80); } #endif } #endif
115a128
/* Setup the ck804 */
118a132
// post_code(0x22); 129a144 // post_code(0x23); 135a151 // post_code(0x25); 172a189 // post_code(0x32); 181a199,202 #if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif 199a221,226 #if 0 dump_spd_registers(&cpu[0]); #endif #if 0 dump_smbus_registers(); #endif 209a237,239 #if 0 dump_pci_devices(); #endif diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2881/Config.lb LinuxBIOSv2/src/mainboard/tyan/s2881/Config.lb 18c18 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2881/get_bus_conf.c LinuxBIOSv2/src/mainboard/tyan/s2881/get_bus_conf.c 9a10,11 #include <cpu/amd/amdk8_sysconf.h>
23,24c25 < unsigned sblk; < unsigned pci1234[] = ---
unsigned pci1234x[] = 36,38c37 < unsigned hc_possible_num; < unsigned sbdn; < unsigned hcdn[] =
unsigned hcdnx[] = 60a60 int i; 66c66,70 < hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; }
70,71c74,75 < sbdn = (hcdn[0] >> 8) & 0xff; < sbdn3 = hcdn[0] & 0xff; ---
sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; sbdn3 = sysconf.hcdn[0] & 0xff; 73c77 < bus_8131_0 = (pci1234[0] >> 16) & 0xff;
bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff; 77c81 < dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sbdn,0));
dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
94,98d97 < #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE < bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); < bus_isa++; < // printk_debug("bus_isa=%d\n",bus_isa); < #endif 107a107,111
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); #endif diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2881/irq_tables.c LinuxBIOSv2/src/mainboard/tyan/s2881/irq_tables.c 12a13,14 #include <cpu/amd/amdk8_sysconf.h>
37,38d38 < extern unsigned sbdn; < extern unsigned hcdn[]; 70c70 < pirq->rtr_devfn = ((sbdn+1)<<3)|0; ---
pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0; 84c84 < write_pirq_info(pirq_info, bus_8111_0, ((sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
write_pirq_info(pirq_info, bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2881/mainboard.c LinuxBIOSv2/src/mainboard/tyan/s2881/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 10c6 < CHIP_NAME("Tyan s2881 mainboard")
CHIP_NAME("Tyan S2881 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2881/mptable.c LinuxBIOSv2/src/mainboard/tyan/s2881/mptable.c 6a7,8 #include <cpu/amd/amdk8_sysconf.h>
17,18d18 < extern unsigned sbdn; < extern unsigned hcdn[]; 103c101 < smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sbdn+1)<<2)|0, apicid_8111, 0x13); ---
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|0, apicid_8111, 0x13);
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2881/Options.lb LinuxBIOSv2/src/mainboard/tyan/s2881/Options.lb 19,20c19,21 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START ---
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 55c56,61 < uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK
uses HT_CHAIN_UNITID_BASE uses HT_CHAIN_END_UNITID_BASE uses SB_HT_CHAIN_ON_BUS0 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY 123a130,141 ##HT Unit ID offset, default is 1, the typical one default HT_CHAIN_UNITID_BASE=0x0a
##real SB Unit ID, default is 0x20, mean dont touch it at last default HT_CHAIN_END_UNITID_BASE=0x06
#make the SB HT chain on bus 0, default is not (0) default SB_HT_CHAIN_ON_BUS0=0
##only offset for SB chain?, default is yes(1) #default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
125c143 < default K8_HW_MEM_HOLE_SIZEK=0x100000 ---
default HW_MEM_HOLE_SIZEK=0x100000 138c156 < default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0 183c201 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2882/auto.c LinuxBIOSv2/src/mainboard/tyan/s2882/auto.c 111c111 < #define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2882/cache_as_ram_auto.c LinuxBIOSv2/src/mainboard/tyan/s2882/cache_as_ram_auto.c 71c71 < #define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2882/Config.lb LinuxBIOSv2/src/mainboard/tyan/s2882/Config.lb 18c18 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2882/mainboard.c LinuxBIOSv2/src/mainboard/tyan/s2882/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 10c6 < CHIP_NAME("Tyan s2882 mainboard")
CHIP_NAME("Tyan S2882 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2882/Options.lb LinuxBIOSv2/src/mainboard/tyan/s2882/Options.lb 19,20c19,21 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 55c56 < uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK 125c126 < default K8_HW_MEM_HOLE_SIZEK=0x100000
default HW_MEM_HOLE_SIZEK=0x100000 138c139 < default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0 183c184 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2885/auto.c LinuxBIOSv2/src/mainboard/tyan/s2885/auto.c 22c22 < #include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/cpu_rev.c" 109c109 < #define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2885/cache_as_ram_auto.c LinuxBIOSv2/src/mainboard/tyan/s2885/cache_as_ram_auto.c 15a16,26 #if 0 static void post_code(uint8_t value) { #if 1 int i; for(i=0;i<0x80000;i++) { outb(value, 0x80); } #endif } #endif
71c83 < #define K8_4RANK_DIMM_SUPPORT 1 ---
#define QRANK_DIMM_SUPPORT 1 115a128 /* Setup the ck804 */ 118a132 // post_code(0x22); 129a144 // post_code(0x23); 135a151 // post_code(0x25); 172a189 // post_code(0x32); 177a195,196 // dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
181a201,204
#if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif 210a234,237 #if 0 dump_pci_devices(); #endif
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2885/Config.lb LinuxBIOSv2/src/mainboard/tyan/s2885/Config.lb 18c18 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) ---
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2885/get_bus_conf.c LinuxBIOSv2/src/mainboard/tyan/s2885/get_bus_conf.c 9a10 #include <cpu/amd/amdk8_sysconf.h> 25,26c26 < unsigned sblk; < unsigned pci1234[] =
unsigned pci1234x[] = 38,40c38 < unsigned hc_possible_num; < unsigned sbdn; < unsigned hcdn[] =
unsigned hcdnx[] = 63a62 int i; 69c68,72 < hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; }
73,75c76,78 < sbdn = (hcdn[0] >> 8) & 0xff; < sbdn3 = hcdn[0] & 0xff; < sbdn5 = hcdn[1] & 0xff; ---
sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; sbdn3 = sysconf.hcdn[0] & 0xff; sbdn5 = sysconf.hcdn[1] & 0xff; 77c80 < bus_8131_0 = (pci1234[0] >> 16) & 0xff;
bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff; 81c84 < dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sbdn,0));
dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
98,102d100 < #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE < bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); < bus_isa++; < // printk_debug("bus_isa=%d\n",bus_isa); < #endif 111a110,115
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); #endif
119c123 < bus_8151_0 = (pci1234[1] >> 16) & 0xff; ---
bus_8151_0 = (sysconf.pci1234[1] >> 16) & 0xff; diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2885/irq_tables.c LinuxBIOSv2/src/mainboard/tyan/s2885/irq_tables.c 12a13,14 #include <cpu/amd/amdk8_sysconf.h>
39,40d40 < extern unsigned sbdn; < extern unsigned hcdn[]; 73c73 < pirq->rtr_devfn = ((sbdn+1)<<3)|0; ---
pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0; 87c87 < write_pirq_info(pirq_info, bus_8111_0, ((sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
write_pirq_info(pirq_info, bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2885/mainboard.c LinuxBIOSv2/src/mainboard/tyan/s2885/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 10c6 < CHIP_NAME("Tyan s2885 mainboard")
CHIP_NAME("Tyan S2885 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2885/mptable.c LinuxBIOSv2/src/mainboard/tyan/s2885/mptable.c 6a7,8 #include <cpu/amd/amdk8_sysconf.h>
19,20d20 < extern unsigned sbdn; < extern unsigned hcdn[]; 102c102 < smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sbdn+1)<<2)|3, apicid_8111, 0x13); ---
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|3, apicid_8111, 0x13);
104c104 < smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sbdn+1)<<2)|1, apicid_8111, 0x11); ---
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|1, apicid_8111, 0x11);
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2885/Options.lb LinuxBIOSv2/src/mainboard/tyan/s2885/Options.lb 19,20c19,21 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START ---
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 55c56 < uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK 65a67,73 uses HT_CHAIN_UNITID_BASE uses HT_CHAIN_END_UNITID_BASE uses SB_HT_CHAIN_ON_BUS0 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses CONFIG_LB_MEM_TOPK
127a136,147
##HT Unit ID offset, default is 1, the typical one default HT_CHAIN_UNITID_BASE=0x0a
##real SB Unit ID, default is 0x20, mean dont touch it at last default HT_CHAIN_END_UNITID_BASE=0x06
#make the SB HT chain on bus 0, default is not (0) default SB_HT_CHAIN_ON_BUS0=2
##only offset for SB chain?, default is yes(1) #default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
129c149 < default K8_HW_MEM_HOLE_SIZEK=0x100000 ---
default HW_MEM_HOLE_SIZEK=0x100000 142c162 < default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0 191c211 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2891/auto.c LinuxBIOSv2/src/mainboard/tyan/s2891/auto.c 15c15 < #include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/cpu_rev.c" 72c72 < #define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2891/cache_as_ram_auto.c LinuxBIOSv2/src/mainboard/tyan/s2891/cache_as_ram_auto.c 5c5 < #define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1 23a24,34 #if 0 static void post_code(uint8_t value) { #if 1 int i; for(i=0;i<0x80000;i++) { outb(value, 0x80); } #endif } #endif
95c108,109 < byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); ---
/* subject decoding*/ byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
98a113
/* LPC Positive Decode 0 */
99a115
/* Serial 0, Serial 1 */
103a120,122
/* s2891 has onboard LPC port 80 */ /*Hope I can enable port 80 here It will decode port 80 to LPC, If you are using PCI post code you can not do this */
135a155
// post_code(0x22); 146a167 // post_code(0x23); 152a174 // post_code(0x25); 189a212,213 // post_code(0x32);
197a222,225
#if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif 214c242 < soft_reset();
// soft_reset(); 223a252,257 #if 0 dump_spd_registers(&cpu[0]); #endif #if 0 dump_smbus_registers(); #endif 227a262,269 #if 0 print_pci_devices(); #endif
#if 0 dump_pci_devices(); #endif
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2891/Config.lb LinuxBIOSv2/src/mainboard/tyan/s2891/Config.lb 18,19c18,19 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) < default CONFIG_ROM_STREAM = 1 ---
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1 24c24 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 317,318c317,318 < # register "rom_address" = "0xfff80000" #for 512K < register "rom_address" = "0xfff00000" #for 1M
register "rom_address" = "0xfff80000" #for 512K # register "rom_address" = "0xfff00000" #for 1M
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2891/get_bus_conf.c LinuxBIOSv2/src/mainboard/tyan/s2891/get_bus_conf.c 9a10
#include <cpu/amd/amdk8_sysconf.h> 28,29c29,30 < unsigned sblk; < unsigned pci1234[] =
unsigned pci1234x[] =
41,43c42 < unsigned hc_possible_num; < unsigned sbdn; < unsigned hcdn[] = ---
unsigned hcdnx[] = 67a67,68 unsigned sbdn; int i; 73c74,78 < hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; }
77,79c82,83 < sbdn = (hcdn[0] & 0xff); // first byte of first chain < < sbdn3 = (hcdn[1] & 0xff); // first byte of second chain ---
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain sbdn = sysconf.sbdn; 81,87c85 < // bus_ck804_0 = node_link_to_bus(0, sblk); < bus_ck804_0 = (pci1234[0] >> 16) & 0xff; < < if(pci1234[2] & 1) { < bus_coproc_0 = (pci1234[2] >> 16) & 0xff; < coprocdn = (hcdn[2] & 0xff); < }
sbdn3 = (sysconf.hcdn[1] & 0xff); // first byte of second chain 88a87 bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff; 156,158c155,156 < bus_8131_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); < bus_8131_0++; < bus_isa = bus_8131_0; // incase only one installed
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++;
165c162 < bus_8131_0 = (pci1234[1] >> 16) & 0xff; ---
bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff;
193a191,194
if(sysconf.pci1234[2] & 1) { bus_coproc_0 = (sysconf.pci1234[2] >> 16) & 0xff; coprocdn = (sysconf.hcdn[2] & 0xff); }
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2891/irq_tables.c LinuxBIOSv2/src/mainboard/tyan/s2891/irq_tables.c 12a13,14
#include <cpu/amd/amdk8_sysconf.h>
43,44d44 < extern unsigned sbdn; < extern unsigned hcdn[]; 46d45 < extern unsigned pci1234[]; 60a60
unsigned sbdn; 62a63 sbdn = sysconf.sbdn; 99c99 < if(pci1234[2] & 1) {
if(sysconf.pci1234[2] & 1) {
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2891/mainboard.c LinuxBIOSv2/src/mainboard/tyan/s2891/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 10c6 < CHIP_NAME("Tyan s2891 mainboard") ---
CHIP_NAME("Tyan S2891 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2891/mptable.c LinuxBIOSv2/src/mainboard/tyan/s2891/mptable.c 6a7,8 #include <cpu/amd/amdk8_sysconf.h>
21,22d22 < extern unsigned sbdn; < extern unsigned hcdn[]; 32a33
unsigned sbdn; 56a58 sbdn = sysconf.sbdn; 77a80 /* Initialize interrupt mapping*/ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2891/Options.lb LinuxBIOSv2/src/mainboard/tyan/s2891/Options.lb 19,20c19,21 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 56,57c57 < uses K8_HW_MEM_HOLE_SIZEK < uses K8_HT_FREQ_1G_SUPPORT
uses HW_MEM_HOLE_SIZEK 72c72 < uses K8_SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_ON_BUS0 79c80 < #default ROM_SIZE=524288
default ROM_SIZE=524288 82c83 < default ROM_SIZE=1048576
#default ROM_SIZE=1048576 140,143c141 < default K8_HW_MEM_HOLE_SIZEK=0x100000 < < #Opteron K8 1G HT Support < default K8_HT_FREQ_1G_SUPPORT=1
default HW_MEM_HOLE_SIZEK=0x100000 152c150 < default K8_SB_HT_CHAIN_ON_BUS0=2
default SB_HT_CHAIN_ON_BUS0=2 155,156c153 < default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 <
#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 223c220 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 232,233c229,230 < default CC="$(CROSS_COMPILE)gcc -m32" < default HOSTCC="gcc"
default CC="$(CROSS_COMPILE)gcc-3.3.6 -m32" default HOSTCC="gcc-3.3.6" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2891/resourcemap.c LinuxBIOSv2/src/mainboard/tyan/s2891/resourcemap.c 261,262c261,262 < // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, < // PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203,
// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */ // PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2892/auto.c LinuxBIOSv2/src/mainboard/tyan/s2892/auto.c 15c15 < #include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/cpu_rev.c" 72c72 < #define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2892/cache_as_ram_auto.c LinuxBIOSv2/src/mainboard/tyan/s2892/cache_as_ram_auto.c 15a16,26 #if 0 static void post_code(uint8_t value) { #if 1 int i; for(i=0;i<0x80000;i++) { outb(value, 0x80); } #endif } #endif
57c68 < #define K8_4RANK_DIMM_SUPPORT 1 ---
#define QRANK_DIMM_SUPPORT 1 101c112 < byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
134a145
// post_code(0x22); 145a157 // post_code(0x23); 151a164 // post_code(0x25); 170,179c183,186 < static const struct mem_controller cpu[] = { < { < .node_id = 0, < .f0 = PCI_DEV(0, 0x18, 0), < .f1 = PCI_DEV(0, 0x18, 1), < .f2 = PCI_DEV(0, 0x18, 2), < .f3 = PCI_DEV(0, 0x18, 3), < .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, < .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, < },
static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0,
181,189c188,189 < { < .node_id = 1, < .f0 = PCI_DEV(0, 0x19, 0), < .f1 = PCI_DEV(0, 0x19, 1), < .f2 = PCI_DEV(0, 0x19, 2), < .f3 = PCI_DEV(0, 0x19, 3), < .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, < .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, < }, ---
(0xa<<3)|4, (0xa<<3)|6, 0, 0, (0xa<<3)|5, (0xa<<3)|7, 0, 0,
193d192 < unsigned bsp_apicid = 0; 194a194,197
unsigned bsp_apicid = 0;
struct mem_controller ctrl[8]; unsigned nodes;
199a203,204
// post_code(0x32);
207a213,216
#if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif 226a236,241 allow_all_aps_stop(bsp_apicid);
nodes = get_nodes(); //It's the time to set ctrl now; fill_mem_ctrl(nodes, ctrl, spd_addr);
227a243,248
#if 0 dump_spd_registers(&cpu[0]); #endif #if 0 dump_smbus_registers(); #endif 230c251,259 < sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
sdram_initialize(nodes, ctrl);
#if 0 print_pci_devices(); #endif
#if 0 dump_pci_devices(); #endif
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2892/Config.lb LinuxBIOSv2/src/mainboard/tyan/s2892/Config.lb 18,19c18,19 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) < default CONFIG_ROM_STREAM = 1 ---
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1 24c24 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 316,317c316 < # register "rom_address" = "0xfff80000" #for 512K < register "rom_address" = "0xfff00000" #for 1M
register "rom_address" = "0xfff80000"
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2892/get_bus_conf.c LinuxBIOSv2/src/mainboard/tyan/s2892/get_bus_conf.c 9a10
#include <cpu/amd/amdk8_sysconf.h> 27,28c28 < unsigned sblk; < unsigned pci1234[] =
unsigned pci1234x[] = 40,42c40 < unsigned hc_possible_num; < unsigned sbdn; < unsigned hcdn[] =
unsigned hcdnx[] = 63a62 unsigned sbdn; 65a65 int i; 71c71,75 < hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; }
75c79,80 < sbdn = (hcdn[0] & 0xff); // first byte of first chain ---
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain sbdn = sysconf.sbdn; 77c82 < sbdn3 = (hcdn[1] & 0xff); // first byte of second chain
sbdn3 = (sysconf.hcdn[1] & 0xff); // first byte of second chain 79,80c84 < // bus_ck804_0 = node_link_to_bus(0, sblk); < bus_ck804_0 = (pci1234[0] >> 16) & 0xff;
bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff; 148,150c152,153 < bus_8131_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); < bus_8131_0++; < bus_isa = bus_8131_0; // incase only one installed
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++;
157c159,160 < bus_8131_0 = (pci1234[1] >> 16) & 0xff; ---
bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff;
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2892/irq_tables.c LinuxBIOSv2/src/mainboard/tyan/s2892/irq_tables.c 12a13,14
#include <cpu/amd/amdk8_sysconf.h>
42,43d43 < extern unsigned sbdn; < extern unsigned hcdn[]; 54a55
unsigned sbdn; 59a61 sbdn = sysconf.sbdn; diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2892/mainboard.c LinuxBIOSv2/src/mainboard/tyan/s2892/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 10c6 < CHIP_NAME("Tyan s2892 mainboard")
CHIP_NAME("Tyan S2892 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2892/mptable.c LinuxBIOSv2/src/mainboard/tyan/s2892/mptable.c 6a7,8 #include <cpu/amd/amdk8_sysconf.h>
21,22d22 < extern unsigned sbdn; < extern unsigned hcdn[]; 31a32
unsigned sbdn; 55a57 sbdn = sysconf.sbdn; 76a79,80 /* Initialize interrupt mapping*/
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2892/Options.lb LinuxBIOSv2/src/mainboard/tyan/s2892/Options.lb 19,20c19,21 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START ---
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 56,57c57 < uses K8_HW_MEM_HOLE_SIZEK < uses K8_HT_FREQ_1G_SUPPORT
uses HW_MEM_HOLE_SIZEK 66c66 < uses K8_SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_ON_BUS0 68a69,70 uses CONFIG_LB_MEM_TOPK
71c73 < #default ROM_SIZE=524288 ---
default ROM_SIZE=524288 74c76 < default ROM_SIZE=1048576
#default ROM_SIZE=1048576 131,136d132 < #1G memory hole < default K8_HW_MEM_HOLE_SIZEK=0x100000 < < #Opteron K8 1G HT Support < default K8_HT_FREQ_1G_SUPPORT=1 < 144c140 < default K8_SB_HT_CHAIN_ON_BUS0=2
default SB_HT_CHAIN_ON_BUS0=2 148a145,147 #1G memory hole default HW_MEM_HOLE_SIZEK=0x100000
207c207 < default CONFIG_ROM_STREAM = 1 ---
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2892/resourcemap.c LinuxBIOSv2/src/mainboard/tyan/s2892/resourcemap.c 261,262c261,262 < // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, < // PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203,
// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */ // PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2895/auto.c LinuxBIOSv2/src/mainboard/tyan/s2895/auto.c 16c16 < #include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/cpu_rev.c" 26c26 < #include <cpu/amd/model_fxx_msr.h>
#include "cpu/amd/model_fxx/model_fxx_msr.h" 94c94 < #define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2895/cache_as_ram_auto.c LinuxBIOSv2/src/mainboard/tyan/s2895/cache_as_ram_auto.c 9c9 < #define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1 23a24,25
#if USE_FAILOVER_IMAGE==0 27a30,40 #if 0 static void post_code(uint8_t value) { #if 1 int i; for(i=0;i<0x8000;i++) { outb(value, 0x80); } #endif } #endif
35,36d48 < #if CONFIG_USE_INIT == 0 < #include "lib/memcpy.c" 41d52 < #include "northbridge/amd/amdk8/debug.c" 42a54,59
#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c" #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
#define SUPERIO_GPIO_IO_BASE 0x400
#if USE_FAILOVER_IMAGE==0 44d60 < #include "cpu/amd/mtrr/amd_earlymtrr.c" 47c63,70 < #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
#if CONFIG_USE_INIT == 0 #include "lib/memcpy.c" #endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
61,63d83 < #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT) < < #define SUPERIO_GPIO_IO_BASE 0x400 96a117
#define CK804B_BUSN 0x80 118a140 #endif 120c142 < #if USE_FALLBACK_IMAGE == 1
#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) 136c158 < byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
144,145c166,168 < #if 1 < lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); ---
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
146a170
lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
150d173 < #endif 177a201
// post_code(0x22); 188a213 // post_code(0x23); 194a220,226 // post_code(0x25); #if HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ ) #endif 203,204c234,235 < < #if USE_FALLBACK_IMAGE == 1
#if HAVE_FAILOVER_BOOT==1 #if USE_FAILOVER_IMAGE==1 206c237 < #endif
#else
208c239,245 < ---
#endif #else #if USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif
210a248,249
#if USE_FAILOVER_IMAGE==0
231a271,272
// post_code(0x32);
239c280,286 < setup_s2895_resource_map(); ---
sio_gpio_setup();
setup_mb_resource_map(); #if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif 256c303 < soft_reset();
// soft_reset();
265a313,318
#if 0 dump_spd_registers(&cpu[0]); #endif #if 0 dump_smbus_registers(); #endif 269a323,330 #if 0 print_pci_devices(); #endif
#if 0 dump_pci_devices(); #endif
271a333
#endif diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2895/Config.lb LinuxBIOSv2/src/mainboard/tyan/s2895/Config.lb 5,7c5,7 < if USE_FALLBACK_IMAGE < default ROM_SECTION_SIZE = FALLBACK_SIZE < default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
if USE_FAILOVER_IMAGE default ROM_SECTION_SIZE = FAILOVER_SIZE default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) 9c9,13 < default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) else default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
10a15
end
18,19c23 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) < default CONFIG_ROM_STREAM = 1 ---
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 24c28 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 34d37 < default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) 36c39,47 < arch i386 end
if USE_FAILOVER_IMAGE default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) else if USE_FALLBACK_IMAGE default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) else default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) end end 37a49 arch i386 end 95c107,108 < if USE_FALLBACK_IMAGE
if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE 97a111,116 end else if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end 116c135,136 < if USE_FALLBACK_IMAGE
if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE 118a139,142 else mainboardinit cpu/x86/32bit/reset32.inc ldscript /cpu/x86/32bit/reset32.lds end 119a144,147 if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else 121a150 end 139c168,169 < if USE_FALLBACK_IMAGE
if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE 141a172,177 end else if USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end 158,159c192,193 < if USE_FALLBACK_IMAGE < ldscript /arch/i386/lib/failover.lds
if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE 160a195,201 ldscript /arch/i386/lib/failover_failover.lds end end else if USE_FALLBACK_IMAGE if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds 163a205 end diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2895/get_bus_conf.c LinuxBIOSv2/src/mainboard/tyan/s2895/get_bus_conf.c 9a10,11 #include <cpu/amd/amdk8_sysconf.h>
34,35c36 < unsigned sblk; < unsigned pci1234[] = ---
unsigned pci1234x[] = 47,49c48 < unsigned hc_possible_num; < unsigned sbdn; < unsigned hcdn[] =
unsigned hcdnx[] = 70a70 unsigned sbdn; 72a73 int i; 78c79,83 < hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; }
82c87,88 < sbdn = (hcdn[0] & 0xff); // first byte of first chain ---
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain sbdn = sysconf.sbdn; 84c90 < sbdn3 = (hcdn[1] & 0xff);
sbdn3 = (sysconf.hcdn[1] & 0xff); 86c92 < sbdnb = (hcdn[2] & 0xff); // first byte of second chain
sbdnb = (sysconf.hcdn[2] & 0xff); // first byte of second chain 88,89c94 < // bus_ck804_0 = node_link_to_bus(0, sblk); < bus_ck804_0 = (pci1234[0] >> 16) & 0xff;
bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff; 161c166 < bus_8131_0 = (pci1234[1] >> 16) & 0xff;
bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff;
190,191c195,196 < if(pci1234[2] & 0xf) { //if the second cpu is installed < bus_ck804b_0 = (pci1234[2]>>16) & 0xff; ---
if(sysconf.pci1234[2] & 0x0f) { //if the second cpu is installed bus_ck804b_0 = (sysconf.pci1234[2]>>16) & 0xff; diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2895/irq_tables.c LinuxBIOSv2/src/mainboard/tyan/s2895/irq_tables.c 12a13,14 #include <cpu/amd/amdk8_sysconf.h>
47d48 < extern unsigned pci1234[]; 49,50d49 < extern unsigned sbdn; < extern unsigned hcdn[]; 60a60
unsigned sbdn; 65a66 sbdn = sysconf.sbdn; 101c102 < if(pci1234[2] & 0xf) {
if(sysconf.pci1234[2] & 0xf) { diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2895/mainboard.c LinuxBIOSv2/src/mainboard/tyan/s2895/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 10c6 < CHIP_NAME("Tyan s2895 mainboard")
CHIP_NAME("Tyan S2895 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2895/mptable.c LinuxBIOSv2/src/mainboard/tyan/s2895/mptable.c 6a7,8 #include <cpu/amd/amdk8_sysconf.h>
28,31d29 < extern unsigned pci1234[]; < < extern unsigned sbdn; < extern unsigned hcdn[]; 40a39
unsigned sbdn; 64a64 sbdn = sysconf.sbdn; 85a86 /* Initialize interrupt mapping*/ 113c114 < if(pci1234[2] & 0xf) {
if(sysconf.pci1234[2] & 0xf) {
184c185 < if(pci1234[2] & 0xf) { ---
if(sysconf.pci1234[2] & 0xf) { diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2895/Options.lb LinuxBIOSv2/src/mainboard/tyan/s2895/Options.lb 4a5,6 uses USE_FAILOVER_IMAGE uses HAVE_FAILOVER_BOOT 13a16 uses FAILOVER_SIZE 19,20c22,24 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 55c59 < uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK 62a67,68 uses SERIAL_CPU_INIT
69c75 < uses K8_SB_HT_CHAIN_ON_BUS0 ---
uses SB_HT_CHAIN_ON_BUS0 71a78,79 uses CONFIG_LB_MEM_TOPK
74c82 < #default ROM_SIZE=524288 ---
default ROM_SIZE=524288 77c85 < default ROM_SIZE=1048576
#default ROM_SIZE=1048576 83,84c91 < #256K < default FALLBACK_SIZE=0x40000
#default FALLBACK_SIZE=0x40000 86,88c93,99 < ### < ### Build options < ###
#FALLBACK: 256K-4K default FALLBACK_SIZE=0x3f000 #FAILOVER: 4K default FAILOVER_SIZE=0x01000
#more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 93a105 default HAVE_FAILOVER_BOOT=1 132a145,146 default SERIAL_CPU_INIT=0
137,140c151 < default K8_HW_MEM_HOLE_SIZEK=0x100000 < < #Opteron K8 1G HT Support < default K8_HT_FREQ_1G_SUPPORT=1 ---
default HW_MEM_HOLE_SIZEK=0x100000 149c160 < default K8_SB_HT_CHAIN_ON_BUS0=2
default SB_HT_CHAIN_ON_BUS0=2 153a165,167 #Opteron K8 1G HT Support default K8_HT_FREQ_1G_SUPPORT=1
166c180 < default ENABLE_APIC_EXT_ID=1 ---
default ENABLE_APIC_EXT_ID=0 204c218 < default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) 209c223 < default _RAMBASE=0x00004000
default _RAMBASE=0x00100000 214c228 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 223,224c237,238 < default CC="$(CROSS_COMPILE)gcc -m32" < default HOSTCC="gcc"
default CC="$(CROSS_COMPILE)gcc-4.0.2 -m32" default HOSTCC="gcc-4.0.2" diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s2895/resourcemap.c LinuxBIOSv2/src/mainboard/tyan/s2895/resourcemap.c 6c6 < static void setup_s2895_resource_map(void)
static void setup_mb_resource_map(void) 186c186 < PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001,
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001, // need to talk to ANALOG of second CK804 to release PCI E reset
256,259c256,259 < PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, < PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, < PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xff800013, < PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, ---
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xff800013, /* link 0 of cpu 1 --> Nvidia CK 804 Slave */ PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, /*113 link 1 of cpu 1 --> HT connector */
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s4880/cache_as_ram_auto.c LinuxBIOSv2/src/mainboard/tyan/s4880/cache_as_ram_auto.c 86c86 < #define K8_4RANK_DIMM_SUPPORT 1 ---
#define QRANK_DIMM_SUPPORT 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s4880/Config.lb LinuxBIOSv2/src/mainboard/tyan/s4880/Config.lb 18,19c18,19 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1 24c24 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s4880/mainboard.c LinuxBIOSv2/src/mainboard/tyan/s4880/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 10c6 < CHIP_NAME("Tyan s4880 mainboard")
CHIP_NAME("Tyan S4880 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s4880/Options.lb LinuxBIOSv2/src/mainboard/tyan/s4880/Options.lb 19,20c19,21 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 55c56 < uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK 129c130 < default K8_HW_MEM_HOLE_SIZEK=0x100000
default HW_MEM_HOLE_SIZEK=0x100000 142c143 < default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0 192c193 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s4882/auto.c LinuxBIOSv2/src/mainboard/tyan/s4882/auto.c 118c118 < #define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s4882/cache_as_ram_auto.c LinuxBIOSv2/src/mainboard/tyan/s4882/cache_as_ram_auto.c 95c95 < #define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s4882/Config.lb LinuxBIOSv2/src/mainboard/tyan/s4882/Config.lb 18,19c18,19 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1 24c24 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s4882/mainboard.c LinuxBIOSv2/src/mainboard/tyan/s4882/mainboard.c 1d0 < #include <console/console.h> 3,5d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> 10c6 < CHIP_NAME("Tyan s4882 mainboard")
CHIP_NAME("Tyan S4882 Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/tyan/s4882/Options.lb LinuxBIOSv2/src/mainboard/tyan/s4882/Options.lb 19,20c19,21 < uses CONFIG_ROM_STREAM < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 55c56 < uses K8_HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZEK 129c130 < default K8_HW_MEM_HOLE_SIZEK=0x100000
default HW_MEM_HOLE_SIZEK=0x100000 142c143 < default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0 191c192 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/via/epia/auto.c LinuxBIOSv2/src/mainboard/via/epia/auto.c 85,111d84 < // Set to 1 if your DIMMs are CL=2 < #ifndef TEST_IFDEF < #define TEST_IFDEF 1 < #endif < < < static void test_ifdef(void) < { < < #if TEST_IFDEF // blows up < outb(50,100); < outb(51,100); < outb(52,100); < #else /* ok */ < outb(60,100); < outb(61,100); < outb(62,100); < #endif < < outb(70,100); // does this work < outb(71,100); < outb(72,100); < < < } < < 116,118d88 < test_ifdef(); < < diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/via/epia/Config.lb LinuxBIOSv2/src/mainboard/via/epia/Config.lb 17c17 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) Only in LinuxBIOSv2/src/mainboard/via/epia: .Config.lb.swp diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/via/epia/mainboard.c LinuxBIOSv2/src/mainboard/via/epia/mainboard.c 1d0 < #include <console/console.h> 3,6d1 < #include <device/pci.h> < #include <device/pci_ids.h> < #include <device/pci_ops.h> < #include <arch/io.h> 10c5 < CHIP_NAME("VIA EPIA mainboard ")
CHIP_NAME("VIA EPIA Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/via/epia/Options.lb LinuxBIOSv2/src/mainboard/via/epia/Options.lb 16c16 < uses CONFIG_ROM_STREAM
uses CONFIG_ROM_PAYLOAD 31c31,32 < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA 42,49d42 < uses DEBUG < < < < default DEBUG=1 < default DEFAULT_CONSOLE_LOGLEVEL=255 < default MAXIMUM_CONSOLE_LOGLEVEL=255 < 50a44,50 # logging uses DEFAULT_CONSOLE_LOGLEVEL uses MAXIMUM_CONSOLE_LOGLEVEL
# logging uses DEFAULT_CONSOLE_LOGLEVEL uses MAXIMUM_CONSOLE_LOGLEVEL 54d53 < ## default TTYS0_BAUD=19200 130c129 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/via/epia-m/auto.c LinuxBIOSv2/src/mainboard/via/epia-m/auto.c 41,45d39 < /* < static void memreset(int controllers, const struct mem_controller *ctrl) < { < } < */ 56,58d47 < /* < #include "sdram/generic_sdram.c" < */ 74c63 < // // a chance to assign I/Os
// a chance to assign I/Os 79d67 < // 135c123 < /* init_timer();*/
// init_timer(); 172a161,162 //dump_pci_devices();
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/via/epia-m/Config.lb LinuxBIOSv2/src/mainboard/via/epia-m/Config.lb 18c18 < default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) ---
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 23c23 < default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 134a135,141
device apic_cluster 0 on chip cpu/via/model_centaur device apic 0 on end end end
183,188d189 < < device apic_cluster 0 on < chip cpu/via/model_centaur < device apic 0 on end < end < end diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/via/epia-m/dsdt.asl LinuxBIOSv2/src/mainboard/via/epia-m/dsdt.asl 208,211c208,212 < Package () {0x000AFFFF, 0x00, LNKD, 0x00}, // Cardbus Link D < Package () {0x000AFFFF, 0x01, LNKA, 0x00}, // Cardbus Link A < Package () {0x000AFFFF, 0x02, LNKB, 0x00}, // Cardbus Link B < Package () {0x000AFFFF, 0x03, LNKC, 0x00}, // Cardbus Link C ---
/* Epia-MII 6000e cardbus: */ Package () {0x000AFFFF, 0x00, LNKA, 0x00}, // Cardbus Link A Package () {0x000AFFFF, 0x01, LNKB, 0x00}, // Cardbus Link B Package () {0x000AFFFF, 0x02, LNKC, 0x00}, // Cardbus Link C Package () {0x000AFFFF, 0x03, LNKD, 0x00}, // Cardbus Link D
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/via/epia-m/dsdt.c LinuxBIOSv2/src/mainboard/via/epia-m/dsdt.c 4,6c4,6 < * ASL Optimizing Compiler / AML Disassembler version 20040715 [Aug 16 2004] < * Copyright (C) 2000 - 2004 Intel Corporation < * Supports ACPI Specification Revision 2.0c ---
* ASL Optimizing Compiler version 20060127 [Apr 23 2006] * Copyright (C) 2000 - 2006 Intel Corporation * Supports ACPI Specification Revision 3.0a 8c8 < * Compilation of "dsdt.asl" - Thu Oct 27 09:25:57 2005
* Compilation of "dsdt.asl" - Wed Sep 6 11:36:08 2006 16c16 < 0x01,0x11,0x4C,0x58,0x42,0x49,0x4F,0x53, /* 00000008 "..LXBIOS" */
0x01,0x03,0x4C,0x58,0x42,0x49,0x4F,0x53, /* 00000008 "..LXBIOS" */
19c19 < 0x15,0x07,0x04,0x20,0x10,0x12,0x5F,0x50, /* 00000020 "... .._P" */ ---
0x27,0x01,0x06,0x20,0x10,0x12,0x5F,0x50, /* 00000020 "'.. .._P" */
84c84 < 0x00,0x4C,0x4E,0x4B,0x44,0x00,0x12,0x0D, /* 00000228 ".LNKD..." */ ---
0x00,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0D, /* 00000228 ".LNKA..." */
86c86 < 0x4E,0x4B,0x41,0x00,0x12,0x0E,0x04,0x0C, /* 00000238 "NKA....." */ ---
0x4E,0x4B,0x42,0x00,0x12,0x0E,0x04,0x0C, /* 00000238 "NKB....." */
88c88 < 0x4B,0x42,0x00,0x12,0x0E,0x04,0x0C,0xFF, /* 00000248 "KB......" */ ---
0x4B,0x43,0x00,0x12,0x0E,0x04,0x0C,0xFF, /* 00000248 "KC......" */
90c90 < 0x43,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 00000258 "C......." */ ---
0x44,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 00000258 "D......." */
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/via/epia-m/mainboard.c LinuxBIOSv2/src/mainboard/via/epia-m/mainboard.c 44c44 < CHIP_NAME("VIA EPIA-M mainboard ") ---
CHIP_NAME("VIA EPIA-M Mainboard") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/mainboard/via/epia-m/Options.lb LinuxBIOSv2/src/mainboard/via/epia-m/Options.lb 8c8 < uses CONFIG_ROM_STREAM
uses CONFIG_ROM_PAYLOAD 23c23,25 < uses CONFIG_ROM_STREAM_START
uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA 117c119 < default CONFIG_ROM_STREAM = 1
default CONFIG_ROM_PAYLOAD = 1 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/amdk8/amdk8_acpi.c LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8_acpi.c 45a46 #include <cpu/amd/amdk8_sysconf.h> 177a180,251
unsigned long acpi_fill_slit(unsigned long current) { /* need to find out the node num at first */ /* fill the first 8 byte with that num */ /* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */
/* because We has assume that we know the topology of the HT connection, So we can have set if we know the node_num */ static uint8_t hops_8[] = { 0, 1, 1, 2, 2, 3, 3, 4, 1, 0, 2, 1, 3, 2, 4, 3, 1, 2, 0, 1, 1, 2, 2, 3, 2, 1, 1, 0, 2, 1, 3, 2, 2, 3, 1, 2, 0, 1, 1, 2, 3, 2, 2, 1, 1, 0, 2, 1, 3, 4, 2, 3, 1, 2, 0, 1, 4, 4, 3, 2, 2, 1, 1, 0 };
// uint8_t outer_node[8];
uint8_t *p = (uint8_t *)current; int nodes = sysconf.nodes; int i,j; memset(p, 0, 8+nodes*nodes); // memset((uint8_t *)outer_node, 0, 8); *p = (uint8_t) nodes; p += 8;
#if 0 for(i=0;i<sysconf.hc_possible_num;i++) { if((sysconf.pci1234[i]&1) !=1 ) continue; outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node } #endif
for(i=0;i<nodes;i++) { for(j=0;j<nodes; j++) { if(i==j) { p[i*nodes+j] = 10; } else { #if 0 int k; uint8_t latency_factor = 0; int k_start, k_end; if(i<j) { k_start = i; k_end = j; } else { k_start = j; k_end = i; } for(k=k_start;k<=k_end; k++) { if(outer_node[k]) { latency_factor = 1; break; } } p[i*nodes+j] = hops_8[i*nodes+j] * 2 + latency_factor + 10; #else p[i*nodes+j] = hops_8[i*nodes+j] * 2 + 10; #endif
} } }
current += 8+nodes*nodes;
return current; }
179a254,333
// moved from mb acpi_tables.c static void int_to_stream(uint32_t val, uint8_t *dest) { int i; for(i=0;i<4;i++) { *(dest+i) = (val >> (8*i)) & 0xff; } }
// used by acpi_tables.h
void update_ssdt(void *ssdt) { uint8_t *BUSN; uint8_t *MMIO; uint8_t *PCIO; uint8_t *SBLK; uint8_t *TOM1; uint8_t *SBDN; uint8_t *HCLK; uint8_t *HCDN; uint8_t *CBST;
int i; device_t dev; uint32_t dword; msr_t msr;
BUSN = ssdt+0x3a; //+5 will be next BUSN MMIO = ssdt+0x57; //+5 will be next MMIO PCIO = ssdt+0xaf; //+5 will be next PCIO SBLK = ssdt+0xdc; // one byte TOM1 = ssdt+0xe3; // SBDN = ssdt+0xed;// HCLK = ssdt+0xfa; //+5 will be next HCLK HCDN = ssdt+0x12a; //+5 will be next HCDN CBST = ssdt+0x157; //
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); for(i=0;i<4;i++) { dword = pci_read_config32(dev, 0xe0+i*4); int_to_stream(dword, BUSN+i*5); } for(i=0;i<0x10;i++) { dword = pci_read_config32(dev, 0x80+i*4); int_to_stream(dword, MMIO+i*5); } for(i=0;i<0x08;i++) { dword = pci_read_config32(dev, 0xc0+i*4); int_to_stream(dword, PCIO+i*5); }
*SBLK = (uint8_t)(sysconf.sblk);
msr = rdmsr(TOP_MEM); int_to_stream(msr.lo, TOM1);
for(i=0;i<sysconf.hc_possible_num;i++) { int_to_stream(sysconf.pci1234[i], HCLK + i*5); int_to_stream(sysconf.hcdn[i], HCDN + i*5); } for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 int_to_stream(0x00000000, HCLK + i*5); int_to_stream(0x20202020, HCDN + i*5); }
int_to_stream(sysconf.sbdn, SBDN);
if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0 *CBST = (uint8_t) (0x0f); } else { *CBST = (uint8_t) (0x00); }
}
//end
Only in LinuxBIOSv2/src/northbridge/amd/amdk8: amdk8_f.h Only in LinuxBIOSv2/src/northbridge/amd/amdk8: amdk8_f_pci.c diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/amdk8/amdk8.h LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8.h 4a5,8
#if K8_REV_F_SUPPORT == 1 #include "amdk8_f.h"
#else 143c150 < #define DCL_UpperCSMap (1<<29)
233a241,269
#include "raminit.h" //struct definitions
#if RAMINIT_SYSINFO==1 struct link_pair_st { device_t udev; uint32_t upos; uint32_t uoffs; device_t dev; uint32_t pos; uint32_t offs;
} __attribute__((packed));
struct sys_info { uint8_t ctrl_present[NODE_NUMS]; struct mem_controller ctrl[NODE_NUMS];
uint32_t nodes; struct link_pair_st link_pair[16];// enough? only in_conherent uint32_t link_pair_num; uint32_t ht_c_num; uint32_t sbdn; uint32_t sblk; uint32_t sbbusn; } __attribute__((packed)); #endif
234a271,272
#endif /* AMDK8_H */
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/amdk8/coherent_ht.c LinuxBIOSv2/src/northbridge/amd/amdk8/coherent_ht.c 1644a1645,1648
static inline unsigned get_nodes(void) { return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1; } diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/amdk8/coherent_ht_car.c LinuxBIOSv2/src/northbridge/amd/amdk8/coherent_ht_car.c 116c116 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 288a289 #if K8_REV_F_SUPPORT == 0 289a291 #endif 1504c1506 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 1592a1595 #if K8_REV_F_SUPPORT == 0 1593a1597 #endif 1611a1616 #if K8_REV_F_SUPPORT == 0 1612a1618 #endif 1640a1647 #if K8_REV_F_SUPPORT == 0 1645a1653 #endif 1658a1667 #if K8_REV_F_SUPPORT == 0 1699a1709 #endif 1736a1747,1751 static inline unsigned get_nodes(void) { return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1; }
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/amdk8/Config.lb LinuxBIOSv2/src/northbridge/amd/amdk8/Config.lb 21a22,28
makerule ssdt.c depends "$(TOP)/src/northbridge/amd/amdk8/ssdt.dsl" action "iasl -tc $(TOP)/src/northbridge/amd/amdk8/ssdt.dsl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex" action "mv ssdt.hex ssdt.c" end object ./ssdt.o
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/amdk8/debug.c LinuxBIOSv2/src/northbridge/amd/amdk8/debug.c 9c9 < #if CONFIG_USE_INIT==1 ---
#if CONFIG_USE_PRINTK_IN_CAR 20,21c20,21 < #if CONFIG_USE_INIT < printk_debug("PCI: %02x:%02x.%02x", (dev>>16) & 0xff, (dev>>11) & 0x1f, (dev>>8) & 0x7);
#if CONFIG_USE_PRINTK_IN_CAR printk_debug("PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); 24c24 < print_debug_hex8((dev >> 16) & 0xff);
print_debug_hex8((dev >> 20) & 0xff); 26c26 < print_debug_hex8((dev >> 11) & 0x1f);
print_debug_hex8((dev >> 15) & 0x1f); 28c28 < print_debug_hex8((dev >> 8) & 7);
print_debug_hex8((dev >> 12) & 7); 46c46 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 53c53 < if(((dev>>8) & 0x07) == 0) {
if(((dev>>12) & 0x07) == 0) {
71c71 < #if CONFIG_USE_INIT ---
#if CONFIG_USE_PRINTK_IN_CAR 80c80 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 89a90,122 #if K8_REV_F_SUPPORT == 1 static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index); static void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) { int i; print_debug_pci_dev(dev); print_debug(" -- index_reg="); print_debug_hex32(index_reg);
for(i = 0; i < 0x40; i++) { uint32_t val; int j; #if CONFIG_USE_PRINTK_IN_CAR printk_debug("\r\n%02x:",i); #else print_debug("\r\n"); print_debug_hex8(i); print_debug_char(':'); #endif val = pci_read_config32_index_wait(dev, index_reg, i); for(j=0;j<4;j++) { #if CONFIG_USE_PRINTK_IN_CAR printk_debug(" %02x", val & 0xff); #else print_debug_char(' '); print_debug_hex8(val&0xff); #endif val >>= 8; }
} print_debug("\r\n"); } #endif
105c138 < if(((dev>>8) & 0x07) == 0) { ---
if(((dev>>12) & 0x07) == 0) {
130c163 < if(((dev>>8) & 0x07) == 0) { ---
if(((dev>>12) & 0x07) == 0) {
139a173,177
#ifndef DEBUG_SMBUS #define DEBUG_SMBUS 0 #endif
#if DEBUG_SMBUS == 1 149c187 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 161c199 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 174c212 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 186c224 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 198c236 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 211c249 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 229c267 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 243c281 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 252c290 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 261a300 #endif 268c307 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 277c316 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 285c324 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 304c343 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 312c351 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/amdk8/get_sblk_pci1234.c LinuxBIOSv2/src/northbridge/amd/amdk8/get_sblk_pci1234.c 41a42,43 #include <cpu/amd/amdk8_sysconf.h>
80,86d81 < extern unsigned pci1234[]; < extern unsigned hcdn[]; < extern unsigned hc_possible_num; < extern unsigned sblk; < < unsigned hcdn_reg[4]; // defined in northbridge.c < 154a150,156
1n: 3 2n: 2x2 - 1 4n: 1x4 - 2 6n: 2 8n: 2 Total: 12
172c174 < sblk = (dword>>8) & 0x3; ---
sysconf.sblk = (dword>>8) & 0x3;
176c178,179 < pci1234[0] = dword; ---
sysconf.pci1234[0] = dword; sysconf.hcid[0] = 0;
192,193c195,196 < pci1234[0] = dwordx; < hcdn[0] = hcdn_reg[j]; ---
sysconf.pci1234[0] = dwordx; sysconf.hcdn[0] = sysconf.hcdn_reg[j];
199,202c202,205 < for(i=1;i<hc_possible_num;i++) { < if((dwordx & 0xff0) == (pci1234[i] & 0xff0)) { < pci1234[i] = dwordx; < hcdn[i] = hcdn_reg[j]; ---
for(i=1;i<sysconf.hc_possible_num;i++) { if((dwordx & 0xff0) == (sysconf.pci1234[i] & 0xff0)) { sysconf.pci1234[i] = dwordx; sysconf.hcdn[i] = sysconf.hcdn_reg[j];
207,210c210,213 < for(i=1;i<hc_possible_num;i++) { < if((dwordx & 0xff0) == (dwordx & pci1234[i] & 0xff0)) { < pci1234[i] = dwordx; < hcdn[i] = hcdn_reg[j]; ---
for(i=1;i<sysconf.hc_possible_num;i++) { if((dwordx & 0xff0) == (dwordx & sysconf.pci1234[i] & 0xff0)) { sysconf.pci1234[i] = dwordx; sysconf.hcdn[i] = sysconf.hcdn_reg[j];
217,220c220,223 < for(i=1;i<hc_possible_num;i++) { < if((pci1234[i] & 1) != 1) { < pci1234[i] = 0; < hcdn[i] = 0x20202020; ---
for(i=1;i<sysconf.hc_possible_num;i++) { if((sysconf.pci1234[i] & 1) != 1) { sysconf.pci1234[i] = 0; sysconf.hcdn[i] = 0x20202020;
221a225
sysconf.hcid[i] = 0;
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/amdk8/incoherent_ht.c LinuxBIOSv2/src/northbridge/amd/amdk8/incoherent_ht.c 2,8c2,5 < * incoherent hypertransport enumeration < * originally written by Eric Biederman < * < * 2004.12 yhlu add multi ht chain dynamically support < * 2005.11 yhlu add let real sb to use small unitid < * 2006.03 stepan cleanups < */ ---
This should be done by Eric 2004.12 yhlu add multi ht chain dynamically support 2005.11 yhlu add let real sb to use small unitid */ 25,28c22 < /* Do we need to allocate MMIO? Currently we direct the last 64M < * to the southbridge link only. We have to remain access to the < * 4G-4M range for the southbridge (Flash ROM) < */
// Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM 35c29 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 58,60c52 < < /* loop through the linked list */ < while(pos != 0) {
while(pos != 0) { /* loop through the linked list */ 92c84 < // actually, only for one HT device HT chain, and unitid is 0
//actually, only for one HT device HT chain, and unitid is 0 160a153 #if K8_REV_F_SUPPORT == 0 163a157 #endif 275,278c268,269 < static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, < unsigned offset_unitid, struct sys_info *sysinfo); < < static int scan_pci_bus(unsigned bus, struct sys_info *sysinfo)
static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo); static int scan_pci_bus( unsigned bus , struct sys_info *sysinfo) 280,296c271,279 < static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, < unsigned offset_unitid); < < static int scan_pci_bus(unsigned bus) < #endif < { < /* Here we already can access PCI_DEV(bus, 0, 0) to < * PCI_DEV(bus, 0x1f, 0x7). < * < * So scan these devices to find out whether there are more bridges. < * < * - If we find a pci bridge, set the bus number in the bridge, and < * continue with the next device. < * < * - For hypertransport bridges, set the bus number in the bridge and < * call ht_setup_chainx(), and scan_pci_bus() < *
static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid); static int scan_pci_bus( unsigned bus) #endif { /* here we already can access PCI_DEV(bus, 0, 0) to PCI_DEV(bus, 0x1f, 0x7) So We can scan these devices to find out if they are bridge If it is pci bridge, We need to set busn in bridge, and go on For ht bridge, We need to set the busn in bridge and ht_setup_chainx, and the scan_pci_bus 317c300 < #if CONFIG_USE_INIT == 1
#if CONFIG_USE_PRINTK_IN_CAR 333c316 < #if CONFIG_USE_INIT == 1
#if CONFIG_USE_PRINTK_IN_CAR 359,363c342,344 < /* Here we need to figure out if dev is a ht < * bridge. If it is, we need to call < * ht_setup_chainx() first < * < * Not verified --- yhlu
/* here we need to figure out if dev is a ht bridge if it is ht bridge, we need to call ht_setup_chainx at first Not verified --- yhlu
365,370c346,347 < < uint8_t upos; // is this valid C? < < // one func one ht sub < upos = ht_lookup_host_capability(dev); < ---
uint8_t upos; upos = ht_lookup_host_capability(dev); // one func one ht sub
425,427c401 < // execute this function even with HT_CHAIN_UNITID_BASE == 0, < // because of the end_of_chain check, and we need it to < // optimize the links ---
//even HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link 437,438c411 < // record the device id of last ht device, so we can set the < // unit id to HT_CHAIN_END_UNITID_BASE
//let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE
522,524c495,497 < /* Find which side of the ht link we are on, by reading < * which direction our last write to PCI_CAP_FLAGS came < * from. ---
/* Find which side of the ht link we are on, * by reading which direction our last write to PCI_CAP_FLAGS * came from.
530,532c503 < /* store the link pair here and we will setup the < * Hypertransport link later, after we get final FID/VID < */ ---
/* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */
547c518 < /* Remember the location of the last device */ ---
/* Remeber the location of the last device */
621,624c590 < < < static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, < uint8_t linkt, uint8_t val) ---
static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt, uint8_t val) 633d598 < dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,3), 0xdc); 635,636c600,601 < /* coherent link only linkt = 3, non coherent = 7*/ < if ( (link_type & 7) == linkt ) {
if ( (link_type & 7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/ dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,3), 0xdc); 639d603 < } 644a609 } 660a626,633 unsigned devn = 1;
#if HT_CHAIN_UNITID_BASE != 1 #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 if(i==0) // to check if it is sb ht chain #endif devn = HT_CHAIN_UNITID_BASE; #endif 668c641 < reg = pci_read_config32( PCI_DEV(busn, 1, 0), PCI_VENDOR_ID);
reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); // ? the chain dev maybe offseted
683a657,718
static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val) { uint32_t dword; uint8_t link_type; unsigned regpos; device_t dev;
/* This works on an Athlon64 because unimplemented links return 0 */ regpos = 0x98 + (linkn * 0x20); dev = PCI_DEV(0,0x18+node,0); dword = pci_read_config32(dev, regpos); link_type = dword & 0xff;
if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/ regpos = 0x90 + (linkn * 0x20); dword = pci_read_config32(dev, regpos );
if (dword != val) { pci_write_config32(dev, regpos, val); return 1; } }
return 0; } static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val) { int reset_needed; uint8_t i;
reset_needed = 0;
for (i = 0; i < ht_c_num; i++) { uint32_t reg; uint8_t nodeid, linkn; uint8_t busn; unsigned devn = 1;
#if HT_CHAIN_UNITID_BASE != 1 #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 if(i==0) // to check if it is sb ht chain #endif devn = HT_CHAIN_UNITID_BASE; #endif
reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); if((reg & 3) != 3) continue; // not enabled
nodeid = ((reg & 0xf0)>>4); // nodeid linkn = ((reg & 0xf00)>>8); // link n busn = (reg & 0xff0000)>>16; //busn
reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1? if ( (reg & 0xffff) == vendorid ) { reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val); } }
return reset_needed; }
690c725 < /* Assumption: The HT chain that is bus 0 has the HT I/O Hub on it. ---
/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. 692c727 < * non coherent links the appropriate bus registers for the
* non Coherent links the appropriate bus registers for the 720,727c754,756 < // We need to setup 0x94, 0xb4, and 0xd4 according to reg < < // nodeid; it will decide 0x18 or 0x19 < devpos = ((reg & 0xf0)>>4)+0x18; < < // link n; it will decide 0x94 or 0xb4, 0x0xd4; < regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; <
//We need setup 0x94, 0xb4, and 0xd4 according to the reg devpos = ((reg & 0xf0)>>4)+0x18; // nodeid; it will decide 0x18 or 0x19 regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n; it will decide 0x94 or 0xb4, 0x0xd4;
756,758c785 < /* You can not use use this in romcc, because recursive < * function calls in romcc will kill you < */ ---
/* You can use use this in romcc, because there is function call in romcc, recursive will kill you */
763,764c790 < // take out reset_needed that is stored in upword < reset_needed |= (scan_pci_bus(bus)>>16); ---
reset_needed |= (scan_pci_bus(bus)>>16); // take out reset_needed that stored in upword
777,781c803,805 < static inline unsigned get_nodes(void) < { < return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1; < } < ---
#if defined (__GNUC__) static inline unsigned get_nodes(void); #endif 806c830 < sysinfo->sblnk = (reg>>8) & 3;
sysinfo->sblk = (reg>>8) & 3; 813,814c837 < /* 0 will be used ht chain with SB we need to keep SB in bus 0 in auto stage */ < next_busn=0x3f+1;
next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/ 827a851,852
#if K8_ALLOCATE_IO_RANGE == 1 830a856 #endif 842,848c867,868 < < /* skip if link is non conherent or not connected*/ < if ((reg & 0x17) != 7) continue; < < print_linkn_in("NC node|link=", < ((nodeid & 0xf)<<4)|(linkn & 0xf)); <
if ((reg & 0x17) != 7) continue; /* it is not non conherent or not connected*/ print_linkn_in("NC node|link=", ((nodeid & 0xf)<<4)|(linkn & 0xf));
850,853c870 < < /* compare (temp & 0xffff) with < * (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) < */ ---
/*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */
855,860c872,873 < reg = pci_read_config32( PCI_DEV(0, 0x18, 1), < 0xe0 + ht_c_num * 4); < < if ( ((reg & 0xffff) == (tempreg & 0xffff)) < || ((reg & 0xffff) == 0x0000) ) { < /*we got it*/ ---
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4); if(((reg & 0xffff) == (tempreg & 0xffff)) || ((reg & 0xffff) == 0x0000)) { /*we got it*/
864,870c877,879 < < /* used up the maximum allowed 4 non conherent links */ < if(ht_c_num == 4) break; < < /* update to 0xe0...*/ < if((reg & 0xf) == 3) continue; /* SbLink so don't touch it */ < ---
if(ht_c_num == 4) break; /*used up only 4 non conherent allowed*/ /*update to 0xe0...*/ if((reg & 0xf) == 3) continue; /*SbLink so don't touch it */
874,876c882 < pci_write_config32(PCI_DEV(0, 0x18, 1), < 0xe0 + ht_c_num * 4, tempreg); < ---
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg);
881,891c887,890 < < // limit < tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); < pci_write_config32( PCI_DEV(0, 0x18, 1), < 0xC4 + ht_c_num * 8, tempreg); < < // base :ISA and VGA ? < tempreg = 3 /*| ( 3<<4)*/ | (next_io_base<<12); < pci_write_config32(PCI_DEV(0, 0x18, 1), < 0xC0 + ht_c_num * 8, tempreg); < ---
tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg); tempreg = 3 /*| ( 3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ? pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0 + ht_c_num * 8, tempreg);
896,899c896 < < /* update 0xe0, 0xe4, 0xe8, 0xec from PCI_DEV(0, 0x18,1) < * to PCI_DEV(0, 0x19,1) to PCI_DEV(0, 0x1f,1); < */ ---
/*update 0xe0, 0xe4, 0xe8, 0xec from PCI_DEV(0, 0x18,1) to PCI_DEV(0, 0x19,1) to PCI_DEV(0, 0x1f,1);*/
940a938
sysinfo->sbdn = get_sbdn(sysinfo->sbbusn); 950c948 < // We need to use the recorded link pair info to optimize the link
// We need to use recorded link pair info to optimize the link 958,960c956 < reset_needed |= ht_optimize_link(link_pair->udev, < link_pair->upos, link_pair->uoffs, < link_pair->dev, link_pair->pos, link_pair->offs);
reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs);
963c959 < reset_needed |= optimize_link_read_pointers(sysinfo->ht_c_num); ---
reset_needed |= optimize_link_read_pointers_chain(sysinfo->ht_c_num); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/amdk8/misc_control.c LinuxBIOSv2/src/northbridge/amd/amdk8/misc_control.c 123a124 #if K8_REV_F_SUPPORT == 0 179a181 #endif diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/amdk8/northbridge.c LinuxBIOSv2/src/northbridge/amd/amdk8/northbridge.c 33c33 < #if K8_HW_MEM_HOLE_SIZEK != 0
#if HW_MEM_HOLE_SIZEK != 0 36a37,40 #include <cpu/amd/amdk8_sysconf.h>
struct amdk8_sysconf_t sysconf;
100,101d103 < unsigned hcdn_reg[4]; // it will be used by get_sblk_pci1234 < 163c165 < #if K8_SB_HT_CHAIN_ON_BUS0 > 0 ---
#if SB_HT_CHAIN_ON_BUS0 > 0 168c170 < #if K8_SB_HT_CHAIN_ON_BUS0 > 1
#if SB_HT_CHAIN_ON_BUS0 > 1 251c253 < hcdn_reg[index] = temp;
sysconf.hcdn_reg[index] = temp;
280c282 < #if K8_SB_HT_CHAIN_ON_BUS0 > 0 ---
#if SB_HT_CHAIN_ON_BUS0 > 0 289c291 < #if K8_SB_HT_CHAIN_ON_BUS0 > 0
#if SB_HT_CHAIN_ON_BUS0 > 0 776c778 < #if K8_HW_MEM_HOLE_SIZEK != 0
#if HW_MEM_HOLE_SIZEK != 0 788c790 < mem_hole.hole_startk = K8_HW_MEM_HOLE_SIZEK;
mem_hole.hole_startk = HW_MEM_HOLE_SIZEK;
934c936 < #if K8_HW_MEM_HOLE_SIZEK != 0 ---
#if HW_MEM_HOLE_SIZEK != 0 1018c1020 < #if K8_HW_MEM_HOLE_SIZEK != 0
#if HW_MEM_HOLE_SIZEK != 0 1022a1025 #if K8_REV_F_SUPPORT == 0 1023a1027 #endif 1035c1039 < if(mem_hole.node_id!=-1) { // We need to select K8_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....!
if(mem_hole.node_id!=-1) { // We need to select HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....!
1041c1045 < #if K8_HW_MEM_HOLE_SIZE_AUTO_INC == 1 ---
#if HW_MEM_HOLE_SIZE_AUTO_INC == 1
1061a1066
#if K8_REV_F_SUPPORT == 0 1062a1068 #endif 1101c1107 < #if K8_HW_MEM_HOLE_SIZEK != 0
#if HW_MEM_HOLE_SIZEK != 0
1102a1109
#if K8_REV_F_SUPPORT == 0
1103a1111
#endif
1142d1149 < int j; 1172d1178 < int apicid_offset; 1174d1179 < int nodes; 1176d1180 < int enable_apic_ext_id; 1180d1183 < unsigned lift_bsp_apicid; 1183,1184c1186,1187 < enable_apic_ext_id = 0; < lift_bsp_apicid = 0; ---
sysconf.enabled_apic_ext_id = 0; sysconf.lift_bsp_apicid = 0; 1189c1192 < apicid_offset = bsp_apicid;
sysconf.apicid_offset = bsp_apicid; 1206c1209,1210 < nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1;
sysconf.nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1;
1210c1214 < enable_apic_ext_id = 1; ---
sysconf.enabled_apic_ext_id = 1;
1213c1217 < apicid_offset = APIC_ID_OFFSET; ---
sysconf.apicid_offset = APIC_ID_OFFSET;
1216c1220 < lift_bsp_apicid = 1; ---
sysconf.lift_bsp_apicid = 1;
1223c1227 < for(i = 0; i < nodes; i++) { ---
for(i = 0; i < sysconf.nodes; i++) { 1264a1269 #if K8_REV_F_SUPPORT == 0 1265a1271,1273 #else e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 #endif 1324,1326c1332,1334 < if(enable_apic_ext_id) { < if(lift_bsp_apicid) { < cpu->path.u.apic.apic_id += apicid_offset;
if(sysconf.enabled_apic_ext_id) { if(sysconf.lift_bsp_apicid) { cpu->path.u.apic.apic_id += sysconf.apicid_offset;
1330c1338 < cpu->path.u.apic.apic_id += apicid_offset; ---
cpu->path.u.apic.apic_id += sysconf.apicid_offset;
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/amdk8/raminit.c LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.c 5a6,8
#if K8_REV_F_SUPPORT == 1 #include "raminit_f.c" #else 17,18c20,21 < #ifndef K8_4RANK_DIMM_SUPPORT < #define K8_4RANK_DIMM_SUPPORT 0
#ifndef QRANK_DIMM_SUPPORT #define QRANK_DIMM_SUPPORT 0 21c24 < #if USE_DCACHE_RAM == 1
#if defined (__GNUC__) 38c41 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 47,48c50,51 < dev = register_values[i] & ~0xff; < where = register_values[i] & 0xff;
dev = register_values[i] & ~0xfff; where = register_values[i] & 0xfff;
68a72,74
#if RAMINIT_SYSINFO==1 static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) #else 69a76 #endif 549c556 < #if CONFIG_USE_INIT
#if CONFIG_USE_PRINTK_IN_CAR 558,559c565,566 < dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x18, 0) + ctrl->f0; < where = register_values[i] & 0xff;
dev = (register_values[i] & ~0xfff) - PCI_DEV(0, 0x18, 0) + ctrl->f0; where = register_values[i] & 0xfff;
627c634 < #if K8_4RANK_DIMM_SUPPORT == 1 ---
#if QRANK_DIMM_SUPPORT == 1 641c648 < #if K8_4RANK_DIMM_SUPPORT == 1
#if QRANK_DIMM_SUPPORT == 1 685c692 < #if K8_4RANK_DIMM_SUPPORT == 1
#if QRANK_DIMM_SUPPORT == 1 714c721 < #if K8_4RANK_DIMM_SUPPORT == 1
#if QRANK_DIMM_SUPPORT == 1 762c769 < #if K8_4RANK_DIMM_SUPPORT == 1
#if QRANK_DIMM_SUPPORT == 1 773c780 < #if K8_4RANK_DIMM_SUPPORT == 1
#if QRANK_DIMM_SUPPORT == 1 796c803 < #if K8_4RANK_DIMM_SUPPORT == 1
#if QRANK_DIMM_SUPPORT == 1 807c814 < #if K8_4RANK_DIMM_SUPPORT == 1
#if QRANK_DIMM_SUPPORT == 1 815c822 < #if K8_4RANK_DIMM_SUPPORT == 1
#if QRANK_DIMM_SUPPORT == 1 889c896 < if(tom_k>(4*1024*1024)) {
if(tom_k > (4*1024*1024)) { 899c906 < #if K8_HW_MEM_HOLE_SIZEK != 0
#if HW_MEM_HOLE_SIZEK != 0 1534c1541 < #if K8_4RANK_DIMM_SUPPORT
#if QRANK_DIMM_SUPPORT 1800c1807 < #if K8_4RANK_DIMM_SUPPORT == 1
#if QRANK_DIMM_SUPPORT == 1 1809c1816 < #if K8_4RANK_DIMM_SUPPORT == 1
#if QRANK_DIMM_SUPPORT == 1 1817c1824 < #if K8_4RANK_DIMM_SUPPORT == 1
#if QRANK_DIMM_SUPPORT == 1 2141a2149,2151 #if RAMINIT_SYSINFO==1 static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) #else 2142a2153 #endif 2186c2197 < #if K8_HW_MEM_HOLE_SIZEK != 0
#if HW_MEM_HOLE_SIZEK != 0 2245c2256 < hole_startk = 4*1024*1024 - K8_HW_MEM_HOLE_SIZEK;
hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK;
2247c2258 < #if K8_HW_MEM_HOLE_SIZE_AUTO_INC == 1 ---
#if HW_MEM_HOLE_SIZE_AUTO_INC == 1 2290a2302,2304 #if RAMINIT_SYSINFO == 1 static void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo) #else 2291a2306 #endif 2391c2406 < #if K8_HW_MEM_HOLE_SIZEK != 0
#if HW_MEM_HOLE_SIZEK != 0 2452a2468,2471 static void set_sysinfo_in_ram(unsigned val) { }
2474a2494,2495
#endif
Only in LinuxBIOSv2/src/northbridge/amd/amdk8: raminit_f.c Only in LinuxBIOSv2/src/northbridge/amd/amdk8: raminit_f_dqs.c diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/amdk8/raminit.h LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.h 3a4,5
#define NODE_NUMS 8
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/amdk8/setup_resource_map.c LinuxBIOSv2/src/northbridge/amd/amdk8/setup_resource_map.c 15c15 < #if CONFIG_USE_INIT ---
#if CONFIG_USE_PRINTK_IN_CAR 24,25c24,25 < dev = (register_values[i] & ~0xff) + offset_pci_dev; < where = register_values[i] & 0xff;
dev = (register_values[i] & ~0xfff) + offset_pci_dev; where = register_values[i] & 0xfff;
59c59 < #if CONFIG_USE_INIT ---
#if CONFIG_USE_PRINTK_IN_CAR 61c61 < i/4, register_values[i],
i>>2, register_values[i],
67c67 < print_debug_hex16(i/4); ---
print_debug_hex16(i>>2);
87,88c87,88 < dev = (register_values[i+1] & ~0xff) + offset_pci_dev; < where = register_values[i+1] & 0xff; ---
dev = (register_values[i+1] & ~0xfff) + offset_pci_dev; where = register_values[i+1] & 0xfff;
154c154 < #if CONFIG_USE_INIT ---
#if CONFIG_USE_PRINTK_IN_CAR 176,177c176,177 < dev = register_values[i+1] & ~0xff; < where = register_values[i+1] & 0xff;
dev = register_values[i+1] & ~0xfff; where = register_values[i+1] & 0xfff;
Only in LinuxBIOSv2/src/northbridge/amd/amdk8: spd_ddr2.h Only in LinuxBIOSv2/src/northbridge/amd/amdk8: ssdt.dsl diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/gx2/northbridge.c LinuxBIOSv2/src/northbridge/amd/gx2/northbridge.c 534c534 < CHIP_NAME("AMD GX2 Northbridge") ---
CHIP_NAME("AMD GX (previously GX2) Northbridge") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/gx2/pll_reset.c LinuxBIOSv2/src/northbridge/amd/gx2/pll_reset.c 129c129 < #define DEFAULT_FBDIV 24 // 400/266 018 ;300/200
#define DEFAULT_FBDIV 22 // 366/244 ; 24 400/266 018 ;300/200 diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/gx2/raminit.c LinuxBIOSv2/src/northbridge/amd/gx2/raminit.c 87a88,95 /* the above setting is supposed to be good for "slow" ram. We have found that for * some dram, at some clock rates, e.g. hynix at 366/244, this will actually * cause errors. The fix is to just set it to 0x310. Tested on 3 boards * with 3 different type of dram -- Hynix, PSC, infineon. * I am leaving this comment here so that at some future time nobody is tempted * to mess with this setting -- RGM, 9/2006 */ msr.hi = 0x00000310; 97c105,116 < /* DRAM working now?? */
/* Fixes from Jordan Crouse of AMD. */
/* make sure there is nothing stale in the cache */ __asm__("wbinvd\n");
print_debug("RAM DLL lock\r\n"); /* The RAM dll needs a write to lock on so generate a few dummy writes */ volatile unsigned long *ptr; for (i=0;i<5;i++) { ptr = (void *)i; *ptr = (unsigned long)i; } diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/lx/chipsetinit.c LinuxBIOSv2/src/northbridge/amd/lx/chipsetinit.c 277c277 < totalmem = sizeram() << 20 - 1;
totalmem = (sizeram() << 20) - 1; diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/lx/grphinit.c LinuxBIOSv2/src/northbridge/amd/lx/grphinit.c 4,5c4 < < #define VIDEO_MB 8 // MB of video memory
#include <console/console.h> 35a35,36 uint16_t wClassIndex, wData, res;
36a38
printk_debug("Graphics init...\n"); 39,40c41,64 < /* NOTE: SoftVG expects the memory size to be given in 512 KB pages */ < vrWrite((VRC_VG << 8) + VG_MEM_SIZE, 0x0100 | (VIDEO_MB * 2));
/* NOTE: SoftVG expects the memory size to be given in 2MB blocks */
wClassIndex = (VRC_VG << 8) + VG_MEM_SIZE;
/* * Graphics Driver Enabled (13) 0, NO (lets BIOS controls the GP) * External Monochrome Card Support(12) 0, NO * Controller Priority Select(11) 1, Primary * Display Select(10:8) 0x0, CRT * Graphics Memory Size(7:1) CONFIG_VIDEO_MB >> 1, * defined in mainboard/../Options.lb * PLL Reference Clock Bypass(0) 0, Default */
/* video RAM has to be given in 2MB chunks * the value is read @ 7:1 (value in 7:0 looks like /2) * so we can add the real value in megabytes */
wData = 0x0800 | (CONFIG_VIDEO_MB & VG_MEM_MASK); vrWrite(wClassIndex, wData);
res = vrRead(wClassIndex); printk_debug("VRC_VG value: 0x%04x\n", res); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/lx/northbridge.c LinuxBIOSv2/src/northbridge/amd/lx/northbridge.c 17,51d16 < #define VIDEO_MB 8 < < extern void graphics_init(void); < < #define NORTHBRIDGE_FILE "northbridge.c" < < /* todo: add a resource record. We don't do this here because this may be called when < * very little of the platform is actually working. < */ < int < sizeram(void) < { < msr_t msr; < int sizem = 0; < unsigned short dimm; < < msr = rdmsr(0x20000018); < printk_debug("sizeram: %08x:%08x\n", msr.hi, msr.lo); < < /* dimm 0 */ < dimm = msr.hi; < /* installed? */ < if ((dimm & 7) != 7) < sizem = (1 << ((dimm >> 12)-1)) * 8; < < < /* dimm 1*/ < dimm = msr.hi >> 16; < /* installed? */ < if ((dimm & 7) != 7) < sizem += (1 << ((dimm >> 12)-1)) * 8; < < printk_debug("sizeram: sizem 0x%x\n", sizem); < return sizem; < } 89a55,58 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
extern void graphics_init(void); extern void cpubug(void); 90a60,63 void northbridge_init_early(void); void chipsetinit(struct northbridge_amd_lx_config *nb); void setup_realmode_idt(void); void do_vsmbios(void); 114,116c87,89 < P2D_BM(0x10000020, 0x1, 0x0, 0x0, 0xfff80), < P2D_BM(0x10000021, 0x1, 0x0, 0x80000, 0xfffe0), < P2D_SC(0x1000002c, 0x1, 0x0, 0x0, 0xff03, 0xC0000),
P2D_BM(MSR_GLIU0_BASE1, 0x1, 0x0, 0x0, 0xfff80), P2D_BM(MSR_GLIU0_BASE2, 0x1, 0x0, 0x80000, 0xfffe0), P2D_SC(MSR_GLIU0_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), 118,120c91,93 < P2D_BM(0x40000020, 0x1, 0x0, 0x0, 0xfff80), < P2D_BM(0x40000021, 0x1, 0x0, 0x80000, 0xfffe0), < P2D_SC(0x4000002e, 0x1, 0x0, 0x0, 0xff03, 0xC0000), // GX3 0x4000002d -> 0x4000002e
P2D_BM(MSR_GLIU1_BASE1, 0x1, 0x0, 0x0, 0xfff80), P2D_BM(MSR_GLIU1_BASE2, 0x1, 0x0, 0x80000, 0xfffe0), P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), 123a97,124 /* todo: add a resource record. We don't do this here because this may be called when * very little of the platform is actually working. */ int sizeram(void) { msr_t msr; int sizem = 0; unsigned short dimm;
msr = rdmsr(0x20000018); printk_debug("sizeram: %08x:%08x\n", msr.hi, msr.lo);
/* dimm 0 */ dimm = msr.hi; sizem = (1 << ((dimm >> 12)-1)) * 8;
/* dimm 1*/ dimm = msr.hi >> 16; /* installed? */ if ((dimm & 7) != 7) sizem += (1 << ((dimm >> 12)-1)) * 8;
printk_debug("sizeram: sizem 0x%x\n", sizem); return sizem; }
176,177c177 < sizereg *= 1024; // convert to bytes < sizereg >>= 12; ---
sizereg >>= 2; 182a183,189
// GX3 //msr.hi = 0x04FFFC02; //msr.lo = 0x1077BE00;
//sizekbytes = 122616;
201a209
#if 0 // andrei: this is done in northbridge.c SMMGL0Init and SystemInit! 214,230c222 < #if 0 < /* This has already been done elsewhere */ < printk_debug("size_kb 0x%x, membytes 0x%x\n", size_kb, membytes); < msr.hi = 0x20000000 | membytes>>24; < msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20); < wrmsr(0x10000028, msr); < msr.hi = 0x20000000 | membytes>>24; < msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20); < wrmsr(0x40000029, msr); < #endif < #if 0 < msr = rdmsr(0x10000028); < printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo); < msr = rdmsr(0x40000029); < printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo); < #endif < #if 1
247,270d238 < #if 0 < < msr.hi = 0x2cfbc040; < msr.lo = 0x400fffc0; < wrmsr(0x10000026, msr); < msr = rdmsr(0x10000026); < printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo); < #endif < #if 0 < msr.hi = 0x22fffc02; < msr.lo = 0x10ffbf00; < wrmsr(0x1808, msr); < msr = rdmsr(0x1808); < printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo); < #endif < #if 0 // SDG - don't do this < /* now do the default MSR values */ < for(i = 0; msr_defaults[i].msr_no; i++) { < msr_t msr; < wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr); // MSR - see table above < msr = rdmsr(msr_defaults[i].msr_no); < printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo); < } < #endif 277a245,367
void print_conf(void) { int i; unsigned long iol; msr_t msr;
int cpu_msr_defs[] = { L2_CONFIG_MSR, CPU_IM_CONFIG, CPU_DM_CONFIG0, CPU_DM_CONFIG1, CPU_DM_PFLOCK, CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM, GLCP_DELAY_CONTROLS, GL_END };
int gliu0_msr_defs[] = {MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU0_BASE3, MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6, GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM, GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2, MSR_GLIU0_SHADOW, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5, GLIU0_GLD_MSR_COH, GL_END };
int gliu1_msr_defs[] = {MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, MSR_GLIU1_BASE6, MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, GLIU1_P2D_R_0, GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW, GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0, GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3, GLIU1_GLD_MSR_COH, GL_END };
int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END };
int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LEG_IO, MDD_PIN_OPT, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, MDD_IRQM_PRIM, GL_END };
int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, GLPCI_RC3, GLPCI_EXT_MSR, GLPCI_SPARE, GL_END };
int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6, MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END };
printk_debug("---------- CPU ------------\n");
for(i = 0; cpu_msr_defs[i] != GL_END; i++) { msr = rdmsr(cpu_msr_defs[i]); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cpu_msr_defs[i], msr.hi, msr.lo); }
printk_debug("---------- GLIU 0 ------------\n");
for(i = 0; gliu0_msr_defs[i] != GL_END; i++) { msr = rdmsr(gliu0_msr_defs[i]); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu0_msr_defs[i], msr.hi, msr.lo); }
printk_debug("---------- GLIU 1 ------------\n");
for(i = 0; gliu1_msr_defs[i] != GL_END; i++) { msr = rdmsr(gliu1_msr_defs[i]); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu1_msr_defs[i], msr.hi, msr.lo); }
printk_debug("---------- RCONF ------------\n");
for(i = 0; rconf_msr[i] != GL_END; i++) { msr = rdmsr(rconf_msr[i]); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], msr.hi, msr.lo); }
printk_debug("---------- VARIA ------------\n"); msr = rdmsr(0x51300010); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi, msr.lo);
msr = rdmsr(0x51400015); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi, msr.lo);
printk_debug("---------- DIVIL IRQ ------------\n"); msr = rdmsr(MDD_IRQM_YLOW); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi, msr.lo); msr = rdmsr(MDD_IRQM_YHIGH); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH, msr.hi, msr.lo); msr = rdmsr(MDD_IRQM_ZLOW); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi, msr.lo); msr = rdmsr(MDD_IRQM_ZHIGH); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH, msr.hi, msr.lo);
printk_debug("---------- PCI ------------\n");
for(i = 0; pci_msr[i] != GL_END; i++) { msr = rdmsr(pci_msr[i]); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], msr.hi, msr.lo); }
printk_debug("---------- LPC/UART DMA ------------\n");
for(i = 0; dma_msr[i] != GL_END; i++) { msr = rdmsr(dma_msr[i]); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], msr.hi, msr.lo); }
printk_debug("---------- CS5536 ------------\n");
for(i = 0; cs5536_msr[i] != GL_END; i++) { msr = rdmsr(cs5536_msr[i]); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i], msr.hi, msr.lo); }
iol = inl(GPIOL_INPUT_ENABLE); printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_INPUT_ENABLE, iol); iol = inl(GPIOL_EVENTS_ENABLE); printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_EVENTS_ENABLE, iol); iol = inl(GPIOL_INPUT_INVERT_ENABLE); printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_INPUT_INVERT_ENABLE, iol); iol = inl(GPIO_MAPPER_X); printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_MAPPER_X, iol);
} 311a401 //msr_t msr; 313c403,404 < printk_debug("northbridge: %s()\n", __FUNCTION__);
printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
316c407,462 < irq_init_steering(dev, nb->irqmap); ---
/* * Swiss cheese */ //msr = rdmsr(MSR_GLIU0_SHADOW);
//msr.hi |= 0x3; //msr.lo |= 0x30000;
// not needed (also irq steering is in legacy vsm so it wouldnt work either) // irq_init_steering(dev, nb->irqmap);
//printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo); //printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo); }
void northbridge_set_resources(struct device *dev) { struct resource *resource, *last; unsigned link; uint8_t line;
last = &dev->resource[dev->resources];
for(resource = &dev->resource[0]; resource < last; resource++) {
// andrei: do not change the base address, it will make the VSA virtual registers unusable //pci_set_resource(dev, resource); // FIXME: static allocation may conflict with dynamic mappings! }
for(link = 0; link < dev->links; link++) { struct bus *bus; bus = &dev->link[link]; if (bus->children) { printk_debug("my_dev_set_resources: assign_resources %d\n", bus); assign_resources(bus); } }
/* set a default latency timer */ pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
/* set a default secondary latency timer */ if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40); }
/* zero the irq settings */ line = pci_read_config8(dev, PCI_INTERRUPT_PIN); if (line) { pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); }
/* set the cache line size, so far 64 bytes is good for everyone */ pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2); 321c467 < .set_resources = pci_dev_set_resources,
.set_resources = northbridge_set_resources, 331c477 < .device = PCI_DEVICE_ID_AMD_LX,
.device = PCI_DEVICE_ID_AMD_LXBRIDGE, 334d479 < #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) 339,340c484 < < printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __FUNCTION__);
printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__); 358,360c502,503 < if (!sizek) { < return; < }
if (!sizek) return;
364c507 < resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ ---
resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | 368,394d510 < static void tolm_test(void *gp, struct device *dev, struct resource *new) < { < struct resource **best_p = gp; < struct resource *best; < best = *best_p; < if (!best || (best->base > new->base)) { < best = new; < } < *best_p = best; < } < < #if 0 < static uint32_t find_pci_tolm(struct bus *bus) < { < struct resource *min; < uint32_t tolm; < min = 0; < search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); < tolm = 0xffffffffUL; < if (min && tolm > min->base) { < tolm = min->base; < } < return tolm; < } < #endif < #define FRAMEBUFFERK 4096 < 397c513 < #if 0
int idx; 399d514 < uint32_t pci_tolm; 401c516,517 < pci_tolm = find_pci_tolm(&dev->link[0]);
printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
403,437c519,520 < if (mc_dev) { < unsigned int tomk, tolmk; < unsigned int ramreg = 0; < int i, idx; < unsigned int *bcdramtop = (unsigned int *)(GX_BASE + BC_DRAM_TOP); < unsigned int *mcgbaseadd = (unsigned int *)(GX_BASE + MC_GBASE_ADD); < < for(i=0; i<0x20; i+= 0x10) { < unsigned int *mcreg = (unsigned int *)(GX_BASE + MC_BANK_CFG); < unsigned int mem_config = *mcreg; < < if (((mem_config & (DIMM_PG_SZ << i)) >> (4 + i)) == 7) < continue; < ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2); < } < < tomk = ramreg << 10; < < /* Sort out the framebuffer size */ < tomk -= FRAMEBUFFERK; < *bcdramtop = ((tomk << 10) - 1); < *mcgbaseadd = (tomk >> 9); < < printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop); < printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd); < < printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10)); < < /* Compute the top of Low memory */ < tolmk = pci_tolm >> 10; < if (tolmk >= tomk) { < /* The PCI hole does does not overlap the memory. < */ < tolmk = tomk; < } ---
if (mc_dev) { 440c523,524 < ram_resource(dev, idx++, 0, tolmk);
ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 1024, ((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE - 1024);
442c526 < #endif ---
445a530,555
static void pci_domain_enable(device_t dev) { struct northbridge_amd_lx_config *nb = (struct northbridge_amd_lx_config *)dev->chip_info;
printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
// do this here for now -- this chip really breaks our device model enable_L2_cache(); northbridge_init_early(); cpubug(); chipsetinit(nb); setup_lx(); setup_realmode_idt();
printk_debug("Before VSA:\n"); print_conf();
do_vsmbios(); // do the magic stuff here, so prepare your tambourine ;)
printk_debug("After VSA:\n"); print_conf();
graphics_init(); pci_set_method(dev); }
447a558,559
printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
456d567 < .init = 0, 457a569
.enable = pci_domain_enable,
461a574,575
printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
477,478d590 < void chipsetInit (void); < 481,485c593,595 < printk_debug("lx north: enable_dev\n"); < void northbridgeinit(void); < void chipsetinit(struct northbridge_amd_lx_config *nb); < void setup_realmode_idt(void); < void do_vsmbios(void); ---
printk_spew(">> Entering northbridge.c: %s with path %d\n", __FUNCTION__, dev->path.type);
487,500c597 < if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { < struct northbridge_amd_lx_config *nb = (struct northbridge_amd_lx_config *)dev->chip_info; < extern void cpubug(void); < printk_debug("DEVICE_PATH_PCI_DOMAIN\n"); < /* cpubug MUST be called before setup_lx(), so we force the issue here */ < enable_L2_cache(); < northbridgeinit(); < /* cpubug(); GX3*/ < chipsetinit(nb); < setup_lx(); < /* do this here for now -- this chip really breaks our device model */ < setup_realmode_idt(); < do_vsmbios(); < graphics_init(); ---
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) 502,505c599 < pci_set_method(dev); < ram_resource(dev, 0, 0, ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE); < } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { < printk_debug("DEVICE_PATH_APIC_CLUSTER\n");
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) 507,508d600 < } < printk_debug("lx north: end enable_dev\n"); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/lx/northbridge.h LinuxBIOSv2/src/northbridge/amd/lx/northbridge.h 4a5 int sizeram(void); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/lx/northbridgeinit.c LinuxBIOSv2/src/northbridge/amd/lx/northbridgeinit.c 29d28 < {.desc_name=MSR_GLIU0_DMM, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/ 41d39 < {.desc_name=MSR_GLIU1_DMM,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Cat0xc and fix dynamicly.*/ 44d41 < {.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0*/ 105,107d101 < /* do we have dmi or not? assume NO per AMD */ < int havedmi = 0; < 115c109 < printk_debug("%s: write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
// printk_debug("%s: write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo); //GX3 118c112 < printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
// printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo); // GX3 147c141 < * system. We will adjust for SMM and DMM now and Frame Buffer later.
* system. We will adjust for SMM now and Frame Buffer later. 153c147,148 < sizebytes -= SMM_SIZE*1024 +1;
sizebytes -= ((SMM_SIZE)<<10); printk_debug("usable RAM: %d bytes\n", sizebytes); 155,158d149 < if (havedmi) < sizebytes -= DMM_SIZE * 1024 + 1; < < sizebytes -= 1; 165,180d155 < wrmsr(gl->desc_name, msr); // MSR - see table above < msr = rdmsr(gl->desc_name); < printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, < gl->desc_name, msr.hi, msr.lo); < < } < static void < DMMGL0Init(struct gliutable *gl) { < msr_t msr; < int sizebytes = sizeram()<<20; < long offset; < < if (! havedmi) < return; < < printk_debug("%s: %d bytes\n", __FUNCTION__, sizebytes); 182,193c157 < sizebytes -= DMM_SIZE*1024; < offset = sizebytes - DMM_OFFSET; < printk_debug("%s: offset is 0x%08x\n", __FUNCTION__, offset); < offset >>= 12; < msr.hi = (gl->hi) | (offset << 8); < /* I don't think this is needed */ < msr.hi &= 0xffffff00; < msr.hi |= (DMM_OFFSET >> 24); < msr.lo = DMM_OFFSET << 8; < msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff; < < wrmsr(gl->desc_name, msr); // MSR - See table above
wrmsr(gl->desc_name, msr); // MSR - see table above 195,196c159,160 < printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo); <
/* printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo); */ // GX3 198,205d161 < static void < DMMGL1Init(struct gliutable *gl) { < msr_t msr; < < if (! havedmi) < return; < < printk_debug("%s:\n", __FUNCTION__ ); 207,219d162 < msr.hi = gl->hi; < /* I don't think this is needed */ < msr.hi &= 0xffffff00; < msr.hi |= (DMM_OFFSET >> 24); < msr.lo = DMM_OFFSET << 8; < /* hmm. AMD source has SMM here ... SMM, not DMM? We think DMM */ < printk_err("%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __FUNCTION__); < msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff; < < wrmsr(gl->desc_name, msr); // MSR - See table above < msr = rdmsr(gl->desc_name); < printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo); < } 226,229c169 < sizebytes -= SMM_SIZE*1024; < < if (havedmi) < sizebytes -= DMM_SIZE * 1024;
sizebytes -= ((SMM_SIZE)<<10); 233a174 offset = (offset >> 12) & 0x000fffff; 235d175 < offset >>= 12; 237c177 < msr.hi = offset << 8;
msr.hi = offset << 8 | MSR_MC; 280,287d219 < case BMO_DMM: /* check for a DMM entry*/ < DMMGL0Init(gl); < break; < < case BM_DMM : /* check for a DMM entry*/ < DMMGL1Init(gl); < break; < 320c252,253 < int msrnum;
int msrnum, enable_preempt, enable_cpu_override; int nic_grants_control, enable_bus_parking; 417a351,358
/* Arbiter setup */
enable_preempt = GLPCI_ARB_LOWER_PRE0_SET | GLPCI_ARB_LOWER_PRE1_SET | GLPCI_ARB_LOWER_PRE2_SET | GLPCI_ARB_LOWER_CPRE_SET; enable_cpu_override = GLPCI_ARB_LOWER_COV_SET; enable_bus_parking = GLPCI_ARB_LOWER_PARK_SET; nic_grants_control = (0x4 << GLPCI_ARB_UPPER_R2_SHIFT) | (0x3 << GLPCI_ARB_UPPER_H2_SHIFT );
420,422d360 < msr.hi |= GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET; < msr.lo |= GLPCI_ARB_LOWER_IIE_SET; < wrmsr(msrnum, msr); 423a362,364
msr.hi |= nic_grants_control; msr.lo |= enable_cpu_override | enable_preempt | enable_bus_parking; wrmsr(msrnum, msr); 510c451 < printk_debug("%s: MSR 0x%08x is 0x%08x:0x%08x\n", __FUNCTION__, gating->msrnum, msr.hi, msr.lo);
//printk_debug("%s: MSR 0x%08x is 0x%08x:0x%08x\n", __FUNCTION__, gating->msrnum, msr.hi, msr.lo); //GX3
513,514c454,455 < printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __FUNCTION__, < gating->msrnum, msr.hi, msr.lo); ---
/* printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __FUNCTION__, gating->msrnum, msr.hi, msr.lo); */ // GX3
529c470 < printk_debug("%s: MSR 0x%08x is 0x%08x:0x%08x\n", __FUNCTION__, prio->msrnum, msr.hi, msr.lo); ---
// printk_debug("%s: MSR 0x%08x is 0x%08x:0x%08x\n", __FUNCTION__, prio->msrnum, msr.hi, msr.lo); // GX3
533,534c474,475 < printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __FUNCTION__, < prio->msrnum, msr.hi, msr.lo); ---
/* printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __FUNCTION__, prio->msrnum, msr.hi, msr.lo); */ // GX3
566c507 < msr_t msr; ---
msr_t msr = {0, 0}; 676a618 shadowSettings |= (uint64_t) 0x0000FFFFFFFF0000ULL; // Enable rw for C0000-CFFFF 707c649 < uint8_t RegionProp;
//uint8_t RegionProp; 724a667,668 printk_debug("SYSDESC: 0x%08X:0x%08X\n",msr.hi,msr.lo);
731a676,677
printk_debug("RCONF LO: 0x%08X\n",msr.lo);
754a701,702
printk_debug("CPU_RCONF_SMM (180E) 0x%08x : 0x%08x\n", msr.hi, msr.lo);
758,760c706,707 < /* ***************************************************************************/ < /* **/ < /* * northBridgeInit*/ ---
/****************************************************************************/ /* * northbridge_init_early */ 770,771c717 < void < northbridgeinit(void)
void northbridge_init_early(void) 793a740,741
/* GX3 OK */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/lx/pll_reset.c LinuxBIOSv2/src/northbridge/amd/lx/pll_reset.c 9c9 < print_debug("MSR GLCP_SYS_RSTPLL (");
print_debug("_MSR GLCP_SYS_RSTPLL ("); 21a22,23 print_debug("CONFIGURING PLL");
24,69c26,27 < /* < * 64 - 32 | 31-0 < * < * (03FB) < * 0000 0011 1111 1011 | 1000 0000 1101 1110 0000 0000 1000 0001 < * < * (039C) < * 0000 0011 1001 1100 | 1000 0000 1101 1110 0000 0000 1000 0001 < * < * (029C) < * 0000 0010 1001 1100 | 1000 0000 1101 1110 0000 0000 1000 0001 < * < * (02CB) < * 0000 0010 1100 1011 | 1000 0000 1101 1110 0000 0000 1000 0001 < * < * 00101 1 00101 1 | 100000 0 0 11011110 0000 0000 1000 0001 < * GLIUMULT GLIUDIV COREMULT COREDIV | SWFLAGS (RO) (RO) HOLD_COUNT < */ < < /* ### 02CB ### < * GLIUMULT = 6 < * GLIUDIV = 2 < * COREMULT = 6 < * COREDIV = 2 < * < * ### 03FB ### < * GLIUMULT = 8 < * GLIUDIV = 2 < * COREMULT = 30 < * COREDIV = 2 < * < * ### 039C ### bad... why? < * GLIUMULT = 8 < * GLIUDIV = 0 < * COREMULT = 15 < * COREDIV = 0 < * < * ### 029C ### good... < * GLIUMULT = 6 < * GLIUDIV = 0 < * COREMULT = 15 < * COREDIV = 0 < * < * CLOCK = 33 MHz < * < */ ---
// HARDCODED VALUES MOVED BACK TO auto.c AS THEY HAVE TO BE BOARD-SPECIFIC // (this file is included from there)
72c30 < msrGlcpSysRstpll.hi = 0x0000029C; ---
msrGlcpSysRstpll.hi = PLLMSRhi;
75c33 < msrGlcpSysRstpll.lo = 0x00DE0000; ---
msrGlcpSysRstpll.lo = PLLMSRlo;
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/amd/lx/raminit.c LinuxBIOSv2/src/northbridge/amd/lx/raminit.c 21,41c21,23 < // This is done by sdram_set_spd_registers() < /*WR_MSR MC_CF07_DATA, DIMMCONFIG, 0x05000040 < < ;WR_MSR MC_CF07_DATA, DIMMCONFIG, 0x00000040 ; MSR 20000018h except REF_INT bits [23:8]. REF_STAG value from DOCS*/ < < /* < * 0x18000100 : 0x696332A3 < * < * 63 - 32 | 31 15 0 < * xxxxxxx | 0110 1001 0110 0011 0011 0010 1010 0011 < * < * 30:28 CAS latency < * < * 010 - 2.0 < * 110 - 2.5 < * < */ < < msr.hi = 0x18000100; < msr.lo = 0x696332A3; < wrmsr(MC_CF8F_DATA, msr); ---
// This is done by sdram_set_spd_registers() that is called by sdram/generic_sdram.c just before this // sdram_set_spd_registers is responsible for reading ram settings from spd rom and configuring sdram conrtoller // Here follows generic sdram initialization procedure.
50a33
//ok 58c41 < msr.lo = 0x00001000;
msr.lo = 0x00000000; 61c44,49 < //print_debug("sdram_enable step 3\r\n");
// reset memory controller msr = rdmsr(MC_CF07_DATA); msr.lo |= 0x00000002; wrmsr(MC_CF07_DATA, msr); msr.lo &= 0xFFFFFFFD; wrmsr(MC_CF07_DATA, msr); 68c56 < msr.lo |= (0x01 << 3);
msr.lo |= 0x00000008;
70c58 < msr.lo &= ~(0x01 << 3); ---
msr.lo &= 0xFFFFFFF7;
76c64 < msr.lo |= 0x2B00; ---
msr.lo |= 0x3A00; 79,88d66 < < < /* set refresh staggering to 4 SDRAM clocks */ < msr = rdmsr(0x20000018); < msr.lo &= ~(0x03 << 6); < msr.lo |= (0x00 << 6); < wrmsr(0x20000018, msr); < //print_debug("sdram_enable step 5\r\n"); < < 92a71 // eeldus et bit29 = 0, mida ta praegu ka on 102a82 // eeldus et bit27:28=00, mida nad ka on 108d87 < //print_debug("sdram_enable step 7\r\n"); 109a89,95 //Delay i=inb(0x61); while (i==inb(0x61)); i=inb(0x61); while (i==inb(0x61)); i=inb(0x61); while (i==inb(0x61)); 117d102 < //print_debug("sdram_enable step 8\r\n"); 123,133c108 < /* load RDSYNC */ < /*msr = rdmsr(0x2000001f); < msr.hi = 0x000ff310; < msr.lo = 0x00000000; < wrmsr(0x2000001f, msr);*/ < < /* set delay control */ < msr = rdmsr(0x4c00000f); < msr.hi = 0x830d415a; < msr.lo = 0x8ea0ad6a; < wrmsr(0x4c00000f, msr);
print_debug("DRAM controller init done.\r\n"); 134a110 /* Fixes from Jordan Crouse of AMD. */ 136c112,113 < print_debug("DRAM controller init done.\r\n");
/* make sure there is nothing stale in the cache */ __asm__("wbinvd\n"); 138c115,121 < /* DRAM working now?? */
print_debug("RAM DLL lock\r\n"); /* The RAM dll needs a write to lock on so generate a few dummy writes */ volatile unsigned long *ptr; for (i=0;i<5;i++) { ptr = (void *)i; *ptr = (unsigned long)i; } diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/ibm/cpc710/cpc710_northbridge.c LinuxBIOSv2/src/northbridge/ibm/cpc710/cpc710_northbridge.c 101c101 < CHIP_NAME("CPC710")
CHIP_NAME("IBM CPC710 Northbridge") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/ibm/cpc925/cpc925_northbridge.c LinuxBIOSv2/src/northbridge/ibm/cpc925/cpc925_northbridge.c 101c101 < CHIP_NAME("CPC925")
CHIP_NAME("IBM CPC925 Northbridge") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/intel/e7501/northbridge.c LinuxBIOSv2/src/northbridge/intel/e7501/northbridge.c 190c190 < CHIP_NAME("Intel E7501 northbridge")
CHIP_NAME("Intel E7501 Northbridge") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/intel/e7501/raminit.c LinuxBIOSv2/src/northbridge/intel/e7501/raminit.c 96,97c96,97 < SPD_PRIMARY_DRAM_WIDTH, < SPD_NUM_BANKS_PER_DRAM
SPD_PRIMARY_SDRAM_WIDTH, SPD_NUM_BANKS_PER_SDRAM 563c563 < value = spd_read_byte(dimm_socket_address, SPD_PRIMARY_DRAM_WIDTH);
value = spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH); 628c628 < value = spd_read_byte(dimm_socket_address, SPD_NUM_BANKS_PER_DRAM);
value = spd_read_byte(dimm_socket_address, SPD_NUM_BANKS_PER_SDRAM);
704c704 < if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != MEMORY_TYPE_SDRAM_DDR) ---
if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR)
1328c1328 < value = spd_read_byte(dimm_socket_address, SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_05); ---
value = spd_read_byte(dimm_socket_address, SPD_SDRAM_CYCLE_TIME_2ND);
1337c1337 < value = spd_read_byte(dimm_socket_address, SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_10); ---
value = spd_read_byte(dimm_socket_address, SPD_SDRAM_CYCLE_TIME_3RD);
1492c1492 < // looks at SPD_ADDRESS_CMD_HOLD. ---
// looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME. 1496c1496 < value = spd_read_byte(dimm_socket_address, SPD_ADDRESS_CMD_HOLD);
value = spd_read_byte(dimm_socket_address, SPD_CMD_SIGNAL_INPUT_HOLD_TIME);
Only in LinuxBIOSv2/src/northbridge/intel: e7520 Only in LinuxBios_mine/src/northbridge/intel: E7520 Only in LinuxBIOSv2/src/northbridge/intel: e7525 Only in LinuxBios_mine/src/northbridge/intel: E7525 Only in LinuxBIOSv2/src/northbridge/intel/i440bx: i440bx.h diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/intel/i440bx/northbridge.c LinuxBIOSv2/src/northbridge/intel/i440bx/northbridge.c 184c184 < CHIP_NAME("Intel 440bx Northbridge") ---
CHIP_NAME("Intel 440BX Northbridge") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/intel/i855pm/northbridge.c LinuxBIOSv2/src/northbridge/intel/i855pm/northbridge.c 160c160 < CHIP_NAME("intel i855pm Northbridge")
CHIP_NAME("Intel 855PM Northbridge")
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/transmeta/tm5800/northbridge.c LinuxBIOSv2/src/northbridge/transmeta/tm5800/northbridge.c 153c153 < CHIP_NAME("Transmeta tm5800 Northbridge") ---
CHIP_NAME("Transmeta TM5800 Northbridge") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/via/vt8601/northbridge.c LinuxBIOSv2/src/northbridge/via/vt8601/northbridge.c 193c193 < CHIP_NAME("VIA vt8601 Northbridge")
CHIP_NAME("VIA VT8601 Northbridge") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/via/vt8601/raminit.c LinuxBIOSv2/src/northbridge/via/vt8601/raminit.c 46c45 < /* Set to 1 if your DIMMs are CL=2 */
// Set to 1 if your DIMMs are CL=2 110c109 < print_debug(" is the north\r\n");
print_debug(" is the north\n"); 120c119 < /* memory clk enable. We are not using ECC */
// memory clk enable. We are not using ECC 121a121 print_debug_hex8(pci_read_config8(north, 0x78)); 123c123 < /* dram control, see the book. */
// dram control, see the book. 130,135c130,131 < /* dram control, see the book. */ < pci_write_config8(north, 0x6B, 0x0d); < < pci_write_config8(north, 0x58, 0x88); < pci_write_config8(north, 0x59, 0x00); <
// dram control, see the book. pci_write_config8(north, 0x6B, 0x0c); 137c133 < /* Initial setting, 256MB in each bank, will be rewritten later.*/
// Initial setting, 256MB in each bank, will be rewritten later. 138a135 print_debug_hex8(pci_read_config8(north, 0x5a)); 144,146c141,142 < /* It seems we have to take care of these 2 registers as if < they are bank 6 and 7. < */
// It seems we have to take care of these 2 registers as if // they are bank 6 and 7. 150,151c146 < < /* SDRAM in all banks */
// SDRAM in all banks 154,159c149,153 < /* DRAM timing. I'm suspicious of this < This is for all banks, 64 is 0,1. 65 is 2,3. 66 is 4,5. < ras precharge 4T, RAS pulse 5T < cas2 is 0xd6, cas3 is 0xe6 < we're also backing off write pulse width to 2T, so result is 0xee < */
// DRAM timing. I'm suspicious of this // This is for all banks, 64 is 0,1. 65 is 2,3. 66 is 4,5. // ras precharge 4T, RAS pulse 5T // cas2 is 0xd6, cas3 is 0xe6 // we're also backing off write pulse width to 2T, so result is 0xee 161,167c155,161 < pci_write_config8(north, 0x64, 0xd6); < pci_write_config8(north, 0x65, 0xd6); < pci_write_config8(north, 0x66, 0xd6); < #else /* CL=3 */ < pci_write_config8(north, 0x64, 0xe6); < pci_write_config8(north, 0x65, 0xe6); < pci_write_config8(north, 0x66, 0xe6);
pci_write_config8(north, 0x64, 0xd4); pci_write_config8(north, 0x65, 0xd4); pci_write_config8(north, 0x66, 0xd4); #else // CL=3 pci_write_config8(north, 0x64, 0xe4); pci_write_config8(north, 0x65, 0xe4); pci_write_config8(north, 0x66, 0xe4); 170,171c164,165 < /* dram frequency select. */ < /* enable 4K pages for 64M dram. */
// dram frequency select. // enable 4K pages for 64M dram. 179c173 < /* refresh counter, disabled. */
// refresh counter, disabled. 182c176 < //* clkenable configuration. kevinh FIXME - add precharge */
// clkenable configuration. kevinh FIXME - add precharge 184,188c178,180 < < /* dram read latch delay of 1 ns, MD drive 8 mA, < high drive strength on MA[2: 13], we#, cas#, ras# < As per Cindy Lee, set to 0x37, not 0x57 < */
// dram read latch delay of 1 ns, MD drive 8 mA, // high drive strength on MA[2: 13], we#, cas#, ras# // As per Cindy Lee, set to 0x37, not 0x57 190,195d181 < < < pci_write_config8(north, 0x67, 0xc4); < pci_write_config8(north, 0x61, 0xaa); < pci_write_config8(north, 0x62, 0x0a); < 206c192 < unsigned int banks, rows, cols;
unsigned int banks, rows, cols, reg; 260c246 < #define T133 7
#define T133 7 283c265 < print_debug(" is the computed timing\r\n");
print_debug(" is the computed timing\n"); 311d291 < unsigned char val; 320,323c300,301 < /* I forget why we need this, but we do */ < /* dimms_write(0xa55a5aa5);*/ < dimms_write(0); < dimms_read(0);
// I forget why we need this, but we do dimms_write(0xa55a5aa5); 329c307 < /* You need to do the memory reference. That causes the nop cycle. */
// You need to do the memory reference. That causes the nop cycle. 365c343 < #else /* CL=3 */
#else // CL=3 373,374c351 < /* dimms_write(0x55aa55aa); */ < dimms_write(0);
dimms_write(0x55aa55aa); 380c355 < /* Set the refresh rate. */
// Set the refresh rate. 387c362 < /* enable multi-page open */
// enable multi-page open 394c368 <
/* side 0 */
397c371 < ---
/* side 1 */
406,407c380,381 < < ---
/* Calculate the value of MA mapping type register, * based on size of SDRAM chips. */
409c383 < ---
/* convert module size to be in Mbits */
423,434d396 < < /* dumpnorth(north); */ < < for(i=0x56;i<0x6e;i++) { < val = pci_read_config8(north, i); < print_debug("reg "); < print_debug_hex8(i); < print_debug(" is "); < print_debug_hex8(val); < print_debug("\r\n"); < } < diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/northbridge/via/vt8623/northbridge.c LinuxBIOSv2/src/northbridge/via/vt8623/northbridge.c 367c367 < CHIP_NAME("VIA vt8623 Northbridge") ---
CHIP_NAME("VIA VT8623 Northbridge") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/pmc/altimus/mpc7410/mpc7410.c LinuxBIOSv2/src/pmc/altimus/mpc7410/mpc7410.c 1,2c1,18 < /* Copyright 2000 AG Electronics Ltd. */ < /* This code is distributed without warranty under the GPL v2 (see COPYING) */
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 2000 AG Electronics Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/pmc/altimus/mpc7410/setup.c LinuxBIOSv2/src/pmc/altimus/mpc7410/setup.c 1,2c1,18 < /* Copyright 2000 AG Electronics Ltd. */ < /* This code is distributed without warranty under the GPL v2 (see COPYING) */
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 2000 AG Electronics Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/amd/amd8111/amd8111.c LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111.c 68c68 < CHIP_NAME("AMD 8111")
CHIP_NAME("AMD-8111 Southbridge") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/amd/amd8111/amd8111_early_ctrl.c LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_early_ctrl.c 13c13 < return (dev>>11) & 0x1f;
return (dev>>15) & 0x1f;
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/amd/amd8111/amd8111_enable_rom.c LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_enable_rom.c 9c9 < dev = pci_locate_device(PCI_ID(0x1022, 0x7468), 0); ---
dev = pci_io_locate_device(PCI_ID(0x1022, 0x7468), 0); 12c12 < byte = pci_read_config8(dev, 0x43);
byte = pci_io_read_config8(dev, 0x43); 14c14 < pci_write_config8(dev, 0x43, byte);
pci_io_write_config8(dev, 0x43, byte); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/amd/amd8111/amd8111_reset.c LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_reset.c 5,7c5,7 < (((BUS) & 0xFF) << 16) | \ < (((DEV) & 0x1f) << 11) | \ < (((FN) & 0x7) << 8))
(((BUS) & 0xFFF) << 20) | \ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) 17c17 < addr = dev | where;
addr = (dev>>4) | where;
25c25 < addr = dev | where; ---
addr = (dev>>4) | where;
33c33 < addr = dev | where; ---
addr = (dev>>4) | where;
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/amd/cs5536/cs5536.c LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c 201c201 < CHIP_NAME("AMD cs5536") ---
CHIP_NAME("AMD Geode CS5536 Southbridge") Only in LinuxBIOSv2/src/southbridge/amd/cs5536: cs5536_smbus2.h Only in LinuxBIOSv2/src/southbridge/amd: cs5536_lx diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/broadcom/bcm5785/bcm5785.c LinuxBIOSv2/src/southbridge/broadcom/bcm5785/bcm5785.c 78c78 < CHIP_NAME("Serverworks bcm5785")
CHIP_NAME("Serverworks BCM5785 Southbridge") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c LinuxBIOSv2/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c 73a74,115 static unsigned get_sbdn(unsigned bus) { device_t dev;
/* Find the device. * There can only be one 8111 on a hypertransport chain/bus. */ dev = pci_locate_device_on_bus( PCI_ID(0x1166, 0x0036), bus);
return (dev>>15) & 0x1f;
}
#define SB_VFSMAF 0
static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { //ACPI Decode Enable outb(0x0e, 0xcd6); outb((1<<3), 0xcd7);
// set port to 0x2060 outb(0x67, 0xcd6); outb(0x60, 0xcd7); outb(0x68, 0xcd6); outb(0x20, 0xcd7);
outb(0x69, 0xcd6); outb(7, 0xcd7);
outb(0x64, 0xcd6); outb(9, 0xcd7); }
static void ldtstop_sb(void) { outb(1, 0x2060); }
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/broadcom/bcm5785/bcm5785_sata.c LinuxBIOSv2/src/southbridge/broadcom/bcm5785/bcm5785_sata.c 23a24,25
unsigned int mmio_base; volatile unsigned int *mmio_reg;
32a35,49
mmio_base = base; mmio_base &= 0xfffffffc; mmio_reg = (unsigned int *)( mmio_base + 0x10f0 ); * mmio_reg = 0x40000001; mmio_reg = ( unsigned int *)( mmio_base + 0x8c ); * mmio_reg = 0x00ff2007; mdelay( 10 ); * mmio_reg = 0x78592009; mdelay( 10 ); * mmio_reg = 0x00082004; mdelay( 10 ); * mmio_reg = 0x00002004; mdelay( 10 );
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/intel/esb6300/esb6300.c LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300.c 46c46 < CHIP_NAME("INTEL 6300ESB") ---
CHIP_NAME("Intel 6300ESB Southbridge") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/intel/i82801ca/i82801ca.c LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca.c 51c51 < CHIP_NAME("Intel 82801ca Southbridge")
CHIP_NAME("Intel 82801CA Southbridge") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/intel/i82801ca/i82801ca_lpc.c LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_lpc.c 124,125c124,125 < // Set ACPI base address to 0x1000 (I/O space) < pci_write_config32(dev, PMBASE, 0x00001001);
// Set ACPI base address to 0x1100 (I/O space) pci_write_config32(dev, PMBASE, 0x00001101);
Only in LinuxBIOSv2/src/southbridge/intel: i82801db diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/intel/i82801dbm/i82801dbm.c LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm.c 62,63c62,63 < struct chip_operations southbridge_intel_i82801dbm_control = { < CHIP_NAME("Intel 82801dbm Southbridge") ---
struct chip_operations southbridge_intel_i82801dbm_ops = { CHIP_NAME("Intel 82801DBM Southbridge") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/intel/pxhd/pxhd_bridge.c LinuxBIOSv2/src/southbridge/intel/pxhd/pxhd_bridge.c 256c256 < CHIP_NAME("PXHD")
CHIP_NAME("Intel PXHD Southbridge") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/nvidia/ck804/ck804.c LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804.c 195c195 < CHIP_NAME("Nvidia ck804")
CHIP_NAME("NVIDIA CK804 Southbridge") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/nvidia/ck804/ck804_early_setup.c LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_early_setup.c 5,25d4 < static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val) < { < uint32_t dword, dword_old; < uint8_t link_type; < < dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x98 + (linkn * 0x20)); < link_type = dword & 0xff; < < dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x90 + (linkn * 0x20) ); < < if ( (link_type & 0x7) == linkt ) { < dword = val; < } < < if (dword != dword_old) { < pci_write_config32(PCI_DEV(0,0x18+node,0), 0x90 + (linkn * 0x20), dword); < return 1; < } < < return 0; < } 28,53c7,9 < int reset_needed; < uint8_t i; < < reset_needed = 0; < < for (i = 0; i < ht_c_num; i++) { < uint32_t reg; < uint8_t nodeid, linkn; < uint8_t busn; < unsigned val; < < reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); < if((reg & 3) != 3) continue; < < nodeid = ((reg & 0xf0)>>4); < linkn = ((reg & 0xf00)>>8); < busn = (reg & 0xff0000)>>16; < < reg = pci_read_config32( PCI_DEV(busn, 1, 0), PCI_VENDOR_ID); < if ( (reg & 0xffff) == 0x10de ) { < val = 0x01610169; < reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val); < } < } < < return reset_needed;
unsigned vendorid = 0x10de; unsigned val = 0x01610169; return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/nvidia/ck804/ck804_early_setup_car.c LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c 6,19d5 < static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val) < { < uint32_t dword, dword_old; < uint8_t link_type; < < /* This works on an Athlon64 because unimplemented links return 0 */ < dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x98 + (linkn * 0x20)); < link_type = dword & 0xff; < < dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x90 + (linkn * 0x20) ); < < if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/ < dword = val; < } 21,27d6 < if (dword != dword_old) { < pci_write_config32(PCI_DEV(0,0x18+node,0), 0x90 + (linkn * 0x20), dword); < return 1; < } < < return 0; < } 30,55c9,11 < int reset_needed; < uint8_t i; < < reset_needed = 0; < < for (i = 0; i < ht_c_num; i++) { < uint32_t reg; < uint8_t nodeid, linkn; < uint8_t busn; < unsigned val; < < reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); < if((reg & 3) != 3) continue; < < nodeid = ((reg & 0xf0)>>4); < linkn = ((reg & 0xf00)>>8); < busn = (reg & 0xff0000)>>16; < < reg = pci_read_config32( PCI_DEV(busn, 1, 0), PCI_VENDOR_ID); < if ( (reg & 0xffff) == 0x10de ) { < val = 0x01610169; < reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val); < } < } < < return reset_needed; ---
unsigned vendorid = 0x10de; unsigned val = 0x01610169; return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/nvidia/ck804/ck804_enable_rom.c LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_enable_rom.c 5c5,9 < ---
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE #define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE #else #define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE #endif diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/nvidia/ck804/ck804_pci.c LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_pci.c 16a17,20 #if CONFIG_PCI_64BIT_PREF_MEM == 1 device_t pci_domain_dev; struct resource *mem1, *mem2; #endif 36a41,58 #if CONFIG_PCI_64BIT_PREF_MEM == 1 pci_domain_dev = dev->bus->dev; while(pci_domain_dev) { if(pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) break; pci_domain_dev = pci_domain_dev->bus->dev; }
if(!pci_domain_dev) return; // impossiable mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit mem2 = find_resource(pci_domain_dev, 2); // mem if(mem1->base > mem2->base) { dword = mem2->base & (0xffff0000UL); printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base); } else { dword = mem1->base & (0xffff0000UL); printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", mem1->base); } #else 38a61 #endif diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/nvidia/ck804/ck804_reset.c LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_reset.c 9,11c9,11 < (((BUS) & 0xFF) << 16) | \ < (((DEV) & 0x1f) << 11) | \ < (((FN) & 0x7) << 8))
(((BUS) & 0xFFF) << 20) | \ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12))
18c18 < addr = dev | where; ---
addr = (dev>>4) | where;
26c26 < addr = dev | where; ---
addr = (dev>>4) | where;
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/ricoh/rl5c476/rl5c476.c LinuxBIOSv2/src/southbridge/ricoh/rl5c476/rl5c476.c 215c215 < CHIP_NAME("RICOH RL5C476") ---
CHIP_NAME("Ricoh RL5C476 CardBus Controller") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/via/vt8231/vt8231.c LinuxBIOSv2/src/southbridge/via/vt8231/vt8231.c 71c71 < CHIP_NAME("VIA vt8231")
CHIP_NAME("VIA VT8231 Southbridge") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/via/vt8231/vt8231_early_serial.c LinuxBIOSv2/src/southbridge/via/vt8231/vt8231_early_serial.c 32,33d31 < #define COM1_BASE 0x3f8 < 54,56c52,53 < /* now go ahead and set up com1. < set address < */
// now go ahead and set up com1. // set address 58,76c55,61 < /* enable serial out and parallel port*/ < vt8231_writesuper(0xf2, 4); < < /* vt8231_writesuper(0xfa, 0x80); */ /* parallel stuff */ < vt8231_writesuper(0xf6, 0xde); /* parallel port address 0x378*/ < < /* < c = pci_read_config8(dev, 0x50); < c &= ~4; < pci_write_config8(dev, 0x50, c); < */ < < < /* That's it for the sio stuff. < movl $SUPERIOCONFIG, %eax < movb $9, %dl < PCI_WRITE_CONFIG_BYTE < set up reg to set baud rate. < */
// enable serial out vt8231_writesuper(0xf2, 7); // That's it for the sio stuff. // movl $SUPERIOCONFIG, %eax // movb $9, %dl // PCI_WRITE_CONFIG_BYTE // set up reg to set baud rate. 78c63 < /* Set 115 kb */
// Set 115 kb 80,85c65,67 < vt8231_writesioword(0x3f9, 0); < < /* Set 9.6 kb < WRITESIOWORD(0x3f8, 12) < now set no parity, one stop, 8 bits < */
// Set 9.6 kb // WRITESIOWORD(0x3f8, 12) // now set no parity, one stop, 8 bits 87c69 < /* now turn on RTS, DRT*/
// now turn on RTS, DRT 89,97c71,74 < < /* turn on fifo and clear them */ < vt8231_writesioword(0x3fa, 7); < < < /* Enable interrupts should they be enabled ???, is there an isr to process them ???*/ < vt8231_writesiobyte(0x3f9, 0x0); /* was 0x0f Ben */ < /* should be done. Dump a char for fun. */ < vt8231_writesiobyte(0x3f8, 65);
// Enable interrupts vt8231_writesiobyte(0x3f9, 0xf); // should be done. Dump a char for fun. vt8231_writesiobyte(0x3f8, 48); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/via/vt8231/vt8231_early_smbus.c LinuxBIOSv2/src/southbridge/via/vt8231/vt8231_early_smbus.c 19,20c19,20 < #define DIMM_BASE 0xa0 /* 1010000 is base for DIMM in SMBus */ < #define READ_CMD 0x01 /* 1 in the 0 bit of SMBHSTADD states to READ */
#define DIMM_BASE 0xa0 // 1010000 is base for DIMM in SMBus #define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ 36c35 < /* set IO base address to SMBUS_IO_BASE */
// set IO base address to SMBUS_IO_BASE 39c38 < /* Enable SMBus */
// Enable SMBus 89,91c88 < /* kill of transaction */ < outb( 2, SMBUS_IO_BASE + SMBHSTCTL); < //* outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
113c110 < static void smbus_reset(void) ---
void smbus_reset(void) 160,161d156 < outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); < 165d159 < print_err("smb -2\r\n"); 172,174c166 < byte = inb(SMBUS_IO_BASE + SMBHSTCTL); < byte &= 0xfe; < outb( byte, SMBUS_IO_BASE + SMBHSTCTL);
outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL); 182,186c172 < byte = inb(SMBUS_IO_BASE + SMBHSTCTL); < byte &= 0x03; < byte |= 0x08; < outb(byte, SMBUS_IO_BASE + SMBHSTCTL); <
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); 189,190c175 < byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); < outb(byte, SMBUS_IO_BASE + SMBHSTSTAT);
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); 196,198c181 < byte = inb(SMBUS_IO_BASE + SMBHSTCTL); < byte |= 0x40; < outb(byte, SMBUS_IO_BASE + SMBHSTCTL);
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); 203d183 < print_err("smb -4\r\n"); 209d188 < print_err("smb -3\r\n"); 220d198 < smbus_print_error(global_status_register); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/via/vt8235/vt8235.c LinuxBIOSv2/src/southbridge/via/vt8235/vt8235.c 95c95 < CHIP_NAME("VIA vt8235")
CHIP_NAME("VIA VT8235 Southbridge") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/southbridge/via/vt8235/vt8235_lpc.c LinuxBIOSv2/src/southbridge/via/vt8235/vt8235_lpc.c 44c44 < static const unsigned char cbPins[4] = { 'D','A','B','C'};
static const unsigned char cbPins[4] = { 'A','B','C','D'}; diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/stream/Config.lb LinuxBIOSv2/src/stream/Config.lb 1,3c1,3 < uses CONFIG_ROM_STREAM < uses CONFIG_IDE_STREAM < uses CONFIG_FS_STREAM
uses CONFIG_ROM_PAYLOAD uses CONFIG_IDE_PAYLOAD uses CONFIG_FS_PAYLOAD 4a5 uses CONFIG_SERIAL_PAYLOAD 6c7 < if CONFIG_ROM_STREAM
if CONFIG_ROM_PAYLOAD 10c11 < if CONFIG_IDE_STREAM
if CONFIG_IDE_PAYLOAD 15c16 < if CONFIG_FS_STREAM
if CONFIG_FS_PAYLOAD 18a20,23
if CONFIG_SERIAL_PAYLOAD object serial_stream.o end diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/stream/rom_stream.c LinuxBIOSv2/src/stream/rom_stream.c 7c7,19 < #if CONFIG_COMPRESSED_ROM_STREAM || CONFIG_PRECOMPRESSED_ROM_STREAM
/* if they set the precompressed rom stream, they better have set a type */ #if CONFIG_PRECOMPRESSED_PAYLOAD && ((!CONFIG_COMPRESSED_PAYLOAD_NRV2B) && (!CONFIG_COMPRESSED_PAYLOAD_LZMA)) #error "You set CONFIG_PRECOMPRESSED_PAYLOAD but need to set CONFIG_COMPRESSED_PAYLOAD_NRV2B or CONFIG_COMPRESSED_PAYLOAD_LZMA" #endif
/* If they set ANY of these, then we're compressed */ #if ((CONFIG_COMPRESSED_PAYLOAD_NRV2B) || (CONFIG_COMPRESSED_PAYLOAD_LZMA)) #define UNCOMPRESSER 1 extern unsigned char _heap, _eheap; #endif
#if (CONFIG_COMPRESSED_PAYLOAD_NRV2B) #define HAVE_UNCOMPRESSER 1 10d21 < extern unsigned char _heap, _eheap; 13,14c24,34 < #ifndef CONFIG_ROM_STREAM_START < #define CONFIG_ROM_STREAM_START 0xffff0000UL
#if (CONFIG_COMPRESSED_PAYLOAD_LZMA) #if HAVE_UNCOMPRESSER #error "You're defining more than one compression type, which is not allowed (of course)" #endif #define HAVE_UNCOMPRESSER 1 // include generic nrv2b #include "../lib/lzma.c" #endif
#ifndef CONFIG_ROM_PAYLOAD_START #define CONFIG_ROM_PAYLOAD_START 0xffff0000UL 19,20c39,40 < * problem is, that on the sc520, ROM_STREAM_START has to be at 0x2000000. < * but if you set CONFIG_ROM_STREAM_START to that, then ld will try to
* problem is, that on the sc520, ROM_PAYLOAD_START has to be at 0x2000000. * but if you set CONFIG_ROM_PAYLOAD_START to that, then ld will try to 26,27c46,47 < /*static const */unsigned char *rom_start = (unsigned char *)CONFIG_ROM_STREAM_START; < /*static const */unsigned char *rom_end = (unsigned char *)(CONFIG_ROM_STREAM_START + PAYLOAD_SIZE - 1);
/*static const */unsigned char *rom_start = (unsigned char *)CONFIG_ROM_PAYLOAD_START; /*static const */unsigned char *rom_end = (unsigned char *)(CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE - 1); 31a52,64 #if UNCOMPRESSER unsigned long uncompress(uint8_t * rom_start, uint8_t *dest ) { #if (CONFIG_COMPRESSED_PAYLOAD_NRV2B) unsigned long ilen; // used compressed stream length return unrv2b(rom_start, dest, &ilen); #endif #if (CONFIG_COMPRESSED_PAYLOAD_LZMA) return ulzma(rom_start, dest); #endif } #endif 34c67 < #if CONFIG_COMPRESSED_ROM_STREAM || CONFIG_PRECOMPRESSED_ROM_STREAM
#if (UNCOMPRESSER) 43c76 < #if CONFIG_COMPRESSED_ROM_STREAM || CONFIG_PRECOMPRESSED_ROM_STREAM
#if (UNCOMPRESSER) 58a92,96 /* ALL of those settings are too smart and also unsafe. Set the dest to 16 MB: * known to be safe for LB for now, and mostly safe for all elf images we have tried. * long term, this has got to be fixed. */ dest = (unsigned char *) (16 * 1024 * 1024); 60c98 < olen = unrv2b((uint8_t *) rom_start, (uint8_t *)dest );
olen = uncompress((uint8_t *) rom_start, (uint8_t *)dest );
Only in LinuxBIOSv2/src/stream: serial_stream.c diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8661f/chip.h LinuxBIOSv2/src/superio/ite/it8661f/chip.h 1a2,3
* This file is part of the LinuxBIOS project. * 24c26 < /* #include <pc80/keyboard.h> */
#include <device/device.h> 27c29 < extern struct chip_operations superio_ITE_it8661f_ops;
extern struct chip_operations superio_ite_it8661f_ops; 29c31 < struct superio_ITE_it8661f_config {
struct superio_ite_it8661f_config { 31d32 < /* struct pc_keyboard keyboard; */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8661f/Config.lb LinuxBIOSv2/src/superio/ite/it8661f/Config.lb 0a1,20 ## ## This file is part of the LinuxBIOS project. ## ## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8661f/it8661f_early_serial.c LinuxBIOSv2/src/superio/ite/it8661f/it8661f_early_serial.c 1a2,3
* This file is part of the LinuxBIOS project. * 27c29 < /* Global Configuration Registers. */
/* Global configuration registers. */ 36c38 < * each line determine the address port, the last four are data. */
each line determine the address port, the last four are data. */ 45c47 < * LDN the register belongs to, before you can access the register. */
LDN the register belongs to, before you can access the register. */ 54c56 < /* Enable the peripheral devices on the IT8661F Super IO chip. */
/* Enable the peripheral devices on the IT8661F Super I/O chip. */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8661f/it8661f.h LinuxBIOSv2/src/superio/ite/it8661f/it8661f.h 1a2,3 * This file is part of the LinuxBIOS project. * 20c22 < /* Status: untested on real hardware, but it compiles. */
/* Status: Untested on real hardware, but it compiles. */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8661f/superio.c LinuxBIOSv2/src/superio/ite/it8661f/superio.c 1a2,3 * This file is part of the LinuxBIOS project. * 20a23,24 #include <device/device.h> #include <device/pnp.h> 22d25 < /* #include <pc80/keyboard.h> */ 28c31 < struct superio_ITE_it8661f_config *conf;
struct superio_ite_it8661f_config *conf; 75,76c78,79 < struct chip_operations superio_ITE_it8661f_ops = { < CHIP_NAME("ITE it8661f")
struct chip_operations superio_ite_it8661f_ops = { CHIP_NAME("ITE IT8661F Super I/O") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8671f/chip.h LinuxBIOSv2/src/superio/ite/it8671f/chip.h 1a2,3 * This file is part of the LinuxBIOS project. * 21a24 #include <device/device.h> 25c28 < extern struct chip_operations superio_ITE_it8671f_ops;
extern struct chip_operations superio_ite_it8671f_ops; 27c30 < struct superio_ITE_it8671f_config {
struct superio_ite_it8671f_config { diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8671f/Config.lb LinuxBIOSv2/src/superio/ite/it8671f/Config.lb 0a1,20 ## ## This file is part of the LinuxBIOS project. ## ## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8671f/it8671f_early_serial.c LinuxBIOSv2/src/superio/ite/it8671f/it8671f_early_serial.c 1a2,3
* This file is part of the LinuxBIOS project. * 27c29 < /* Global Configuration Registers. */
/* Global configuration registers. */ 36c38 < * each line determine the address port, the last four are data. */
each line determine the address port, the last four are data. */ 45c47 < * LDN the register belongs to, before you can access the register. */
LDN the register belongs to, before you can access the register. */ 54c56 < /* Enable the peripheral devices on the IT8671F Super IO chip. */
/* Enable the peripheral devices on the IT8671F Super I/O chip. */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8671f/it8671f.h LinuxBIOSv2/src/superio/ite/it8671f/it8671f.h 1a2,3 * This file is part of the LinuxBIOS project. * diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8671f/superio.c LinuxBIOSv2/src/superio/ite/it8671f/superio.c 1a2,3 * This file is part of the LinuxBIOS project. * 18a21,22 #include <device/device.h> #include <device/pnp.h> 26c30 < struct superio_ITE_it8671f_config *conf;
struct superio_ite_it8671f_config *conf; 79,80c83,84 < struct chip_operations superio_ITE_it8671f_ops = { < CHIP_NAME("ITE it8671f")
struct chip_operations superio_ite_it8671f_ops = { CHIP_NAME("ITE IT8671F Super I/O") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8673f/chip.h LinuxBIOSv2/src/superio/ite/it8673f/chip.h 1a2,3 * This file is part of the LinuxBIOS project. * 21a24 #include <device/device.h> 25c28 < extern struct chip_operations superio_ITE_it8673f_ops;
extern struct chip_operations superio_ite_it8673f_ops; 27c30 < struct superio_ITE_it8673f_config {
struct superio_ite_it8673f_config { diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8673f/Config.lb LinuxBIOSv2/src/superio/ite/it8673f/Config.lb 0a1,20 ## ## This file is part of the LinuxBIOS project. ## ## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8673f/it8673f_early_serial.c LinuxBIOSv2/src/superio/ite/it8673f/it8673f_early_serial.c 1a2,3
* This file is part of the LinuxBIOS project. * 27c29 < /* Global Configuration Registers. */
/* Global configuration registers. */ 36c38 < * each line determine the address port, the last four are data. */
each line determine the address port, the last four are data. */ 45c47 < * LDN the register belongs to, before you can access the register. */
LDN the register belongs to, before you can access the register. */ 54c56 < /* Enable the peripheral devices on the IT8673F Super IO chip. */
/* Enable the peripheral devices on the IT8673F Super I/O chip. */ 86c88 < /* Select 24MHz CLKIN (clear bit 0). TODO: is this really needed? */
/* Select 24MHz CLKIN (clear bit 0). */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8673f/it8673f.h LinuxBIOSv2/src/superio/ite/it8673f/it8673f.h 1a2,3 * This file is part of the LinuxBIOS project. * 20c22 < /* Status: untested on real hardware, but it compiles. */
/* Status: Untested on real hardware, but it compiles. */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8673f/superio.c LinuxBIOSv2/src/superio/ite/it8673f/superio.c 1a2,3 * This file is part of the LinuxBIOS project. * 18a21,22 #include <device/device.h> #include <device/pnp.h> 26c30 < struct superio_ITE_it8673f_config *conf;
struct superio_ite_it8673f_config *conf; 81,82c85,86 < struct chip_operations superio_ITE_it8673f_ops = { < CHIP_NAME("ITE it8673f")
struct chip_operations superio_ite_it8673f_ops = { CHIP_NAME("ITE IT8673F Super I/O") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8705f/chip.h LinuxBIOSv2/src/superio/ite/it8705f/chip.h 1a2,3 * This file is part of the LinuxBIOS project. * 23a26 #include <device/device.h> 26c29 < extern struct chip_operations superio_ITE_it8705f_ops;
extern struct chip_operations superio_ite_it8705f_ops; 28c31 < struct superio_ITE_it8705f_config {
struct superio_ite_it8705f_config { diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8705f/Config.lb LinuxBIOSv2/src/superio/ite/it8705f/Config.lb 0a1,20 ## ## This file is part of the LinuxBIOS project. ## ## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8705f/it8705f_early_serial.c LinuxBIOSv2/src/superio/ite/it8705f/it8705f_early_serial.c 1a2,3
* This file is part of the LinuxBIOS project. * 27c29 < /* Global Configuration Registers. */
/* Global configuration registers. */ 33,34c35,36 < #define IT8705F_CONFIG_REG_CLOCKSEL 0x24 /* Clock Selection. */ < #define IT8705F_CONFIG_REG_SWSUSP 0x23 /* Software Suspend, Flash I/F. */
#define IT8705F_CONFIG_REG_CLOCKSEL 0x24 /* Clock Selection, Flash I/F. */ #define IT8705F_CONFIG_REG_SWSUSP 0x23 /* Software Suspend. */ 39c41 < * LDN the register belongs to, before you can access the register. */
LDN the register belongs to, before you can access the register. */ 48c50 < /* Enable the peripheral devices on the IT8705F Super IO chip. */
/* Enable the peripheral devices on the IT8705F Super I/O chip. */ 64,65c66,67 < * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. < * If this register is not written, both chips are configured. */
Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. If this register is not written, both chips are configured. */
74d75 < /* GPIO */ 79,80c80,81 < /* Select 24MHz/48MHz CLKIN (set/clear bit 0). TODO: Needed? */ < /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CLOCKSEL, 0x00); */ ---
/* Select 24MHz CLKIN (set bit 0). */ it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CLOCKSEL, 0x01); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8705f/it8705f.h LinuxBIOSv2/src/superio/ite/it8705f/it8705f.h 1a2,3 * This file is part of the LinuxBIOS project. * 20c22 < /* Status: untested on real hardware, but it compiles. */
/* Status: Untested on real hardware, but it compiles. */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8705f/superio.c LinuxBIOSv2/src/superio/ite/it8705f/superio.c 1a2,3 * This file is part of the LinuxBIOS project. * 20a23,24 #include <device/device.h> #include <device/pnp.h> 27c31 < struct superio_ITE_it8705f_config *conf;
struct superio_ite_it8705f_config *conf; 82,83c86,87 < struct chip_operations superio_ITE_it8705f_ops = { < CHIP_NAME("ITE it8705f")
struct chip_operations superio_ite_it8705f_ops = { CHIP_NAME("ITE IT8705F Super I/O") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8712f/chip.h LinuxBIOSv2/src/superio/ite/it8712f/chip.h 1a2,3 * This file is part of the LinuxBIOS project. * 21a24 #include <device/device.h> 25c28 < extern struct chip_operations superio_ITE_it8712f_ops;
extern struct chip_operations superio_ite_it8712f_ops; 27c30 < struct superio_ITE_it8712f_config {
struct superio_ite_it8712f_config { diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8712f/Config.lb LinuxBIOSv2/src/superio/ite/it8712f/Config.lb 0a1,20 ## ## This file is part of the LinuxBIOS project. ## ## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8712f/it8712f_early_serial.c LinuxBIOSv2/src/superio/ite/it8712f/it8712f_early_serial.c 1a2,3
* This file is part of the LinuxBIOS project. * 27c29 < /* Global Configuration Registers. */
/* Global configuration registers. */ 37c39 < * LDN the register belongs to, before you can access the register. */
LDN the register belongs to, before you can access the register. */ 46c48 < /* Enable the peripheral devices on the IT8712F Super IO chip. */
/* Enable the peripheral devices on the IT8712F Super I/O chip. */ 62,63c64,65 < * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. < * If this register is not written, both chips are configured. */
Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. If this register is not written, both chips are configured. */
78,79c80,81 < /* Select 24MHz/48MHz CLKIN (set/clear bit 0). TODO: Needed? */ < /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x00); */ ---
/* Select 24MHz CLKIN (set bit 0). */ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x01); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8712f/it8712f.h LinuxBIOSv2/src/superio/ite/it8712f/it8712f.h 1a2,3 * This file is part of the LinuxBIOS project. * 20c22 < /* Status: untested on real hardware, but it compiles. */
/* Status: Com1 is tested and works. */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8712f/superio.c LinuxBIOSv2/src/superio/ite/it8712f/superio.c 1a2,3 * This file is part of the LinuxBIOS project. * 18a21,22 #include <device/device.h> #include <device/pnp.h> 26c30 < struct superio_ITE_it8712f_config *conf;
struct superio_ite_it8712f_config *conf; 87,88c91,92 < struct chip_operations superio_ITE_it8712f_ops = { < CHIP_NAME("ITE it8712f")
struct chip_operations superio_ite_it8712f_ops = { CHIP_NAME("ITE IT8712F Super I/O") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8716f/chip.h LinuxBIOSv2/src/superio/ite/it8716f/chip.h 1a2,3 * This file is part of the LinuxBIOS project. * 21a24 #include <device/device.h> 25c28 < extern struct chip_operations superio_ITE_it8716f_ops;
extern struct chip_operations superio_ite_it8716f_ops; 27c30 < struct superio_ITE_it8716f_config {
struct superio_ite_it8716f_config { diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8716f/Config.lb LinuxBIOSv2/src/superio/ite/it8716f/Config.lb 0a1,20 ## ## This file is part of the LinuxBIOS project. ## ## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8716f/it8716f_early_serial.c LinuxBIOSv2/src/superio/ite/it8716f/it8716f_early_serial.c 1a2,3
* This file is part of the LinuxBIOS project. * 27c29 < /* Global Configuration Registers. */
/* Global configuration registers. */ 37c39 < * LDN the register belongs to, before you can access the register. */
LDN the register belongs to, before you can access the register. */ 46c48 < /* Enable the peripheral devices on the IT8716F Super IO chip. */
/* Enable the peripheral devices on the IT8716F Super I/O chip. */ 62,63c64,65 < * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. < * If this register is not written, both chips are configured. */
Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. If this register is not written, both chips are configured. */
78,79c80,81 < /* Select 24MHz/48MHz CLKIN (set/clear bit 0). TODO: Needed? */ < /* it8716f_sio_write(0x00, IT8716F_CONFIG_REG_CLOCKSEL, 0x00); */ ---
/* Select 24MHz CLKIN (set bit 0). */ it8716f_sio_write(0x00, IT8716F_CONFIG_REG_CLOCKSEL, 0x01); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8716f/it8716f.h LinuxBIOSv2/src/superio/ite/it8716f/it8716f.h 1a2,3 * This file is part of the LinuxBIOS project. * 20c22 < /* Status: untested on real hardware, but it compiles. */
/* Status: Untested on real hardware, but it compiles. */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8716f/superio.c LinuxBIOSv2/src/superio/ite/it8716f/superio.c 1a2,3 * This file is part of the LinuxBIOS project. * 18a21,22 #include <device/device.h> #include <device/pnp.h> 26c30 < struct superio_ITE_it8716f_config *conf;
struct superio_ite_it8716f_config *conf; 87,88c91,92 < struct chip_operations superio_ITE_it8716f_ops = { < CHIP_NAME("ITE it8716f")
struct chip_operations superio_ite_it8716f_ops = { CHIP_NAME("ITE IT8716F Super I/O") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8718f/chip.h LinuxBIOSv2/src/superio/ite/it8718f/chip.h 1a2,3 * This file is part of the LinuxBIOS project. * 21a24 #include <device/device.h> 25c28 < extern struct chip_operations superio_ITE_it8718f_ops;
extern struct chip_operations superio_ite_it8718f_ops; 27c30 < struct superio_ITE_it8718f_config {
struct superio_ite_it8718f_config { diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8718f/Config.lb LinuxBIOSv2/src/superio/ite/it8718f/Config.lb 0a1,20 ## ## This file is part of the LinuxBIOS project. ## ## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8718f/it8718f_early_serial.c LinuxBIOSv2/src/superio/ite/it8718f/it8718f_early_serial.c 1a2,3
* This file is part of the LinuxBIOS project. * 27c29 < /* Global Configuration Registers. */
/* Global configuration registers. */ 37c39 < * LDN the register belongs to, before you can access the register. */
LDN the register belongs to, before you can access the register. */ 46c48 < /* Enable the peripheral devices on the IT8718F Super IO chip. */
/* Enable the peripheral devices on the IT8718F Super I/O chip. */ 62,63c64,65 < * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. < * If this register is not written, both chips are configured. */
Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. If this register is not written, both chips are configured. */
76,77c78,79 < /* Select 24MHz/48MHz CLKIN (set/clear bit 0). TODO: Needed? */ < /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x00); */ ---
/* Select 24MHz CLKIN (set bit 0). */ it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x01); diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8718f/it8718f.h LinuxBIOSv2/src/superio/ite/it8718f/it8718f.h 1a2,3 * This file is part of the LinuxBIOS project. * 20c22 < /* Status: untested on real hardware, but it compiles. */
/* Status: Untested on real hardware, but it compiles. */ diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/ite/it8718f/superio.c LinuxBIOSv2/src/superio/ite/it8718f/superio.c 1a2,3 * This file is part of the LinuxBIOS project. * 18a21,22 #include <device/device.h> #include <device/pnp.h> 26c30 < struct superio_ITE_it8718f_config *conf;
struct superio_ite_it8718f_config *conf; 83,84c87,88 < struct chip_operations superio_ITE_it8718f_ops = { < CHIP_NAME("ITE it8718f")
struct chip_operations superio_ite_it8718f_ops = { CHIP_NAME("ITE IT8718F Super I/O") Only in LinuxBIOSv2/src/superio: nsc Only in LinuxBios_mine/src/superio: NSC Only in LinuxBIOSv2/src/superio/smsc: fdc37m60x diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/smsc/lpc47b272/chip.h LinuxBIOSv2/src/superio/smsc/lpc47b272/chip.h 0a1,20 /* * This file is part of the LinuxBIOS project. * * Copyright (C) 2005 Digital Design Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/smsc/lpc47b272/Config.lb LinuxBIOSv2/src/superio/smsc/lpc47b272/Config.lb 0a1,20
## ## This file is part of the LinuxBIOS project. ## ## Copyright (C) 2005 Digital Design Corporation ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c LinuxBIOSv2/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c 2c2 < * lpc47b272_early_serial.c: Pre-RAM driver for SMSC LPC47B272 Super I/O chip ---
* This file is part of the LinuxBIOS project. 20a21,22 /* Pre-RAM driver for SMSC LPC47B272 Super I/O chip. */
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/smsc/lpc47b272/lpc47b272.h LinuxBIOSv2/src/superio/smsc/lpc47b272/lpc47b272.h 0a1,20
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 2005 Digital Design Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/smsc/lpc47b272/superio.c LinuxBIOSv2/src/superio/smsc/lpc47b272/superio.c 2c2 < * superio.c: RAM driver for SMSC LPC47B272 Super I/O chip ---
* This file is part of the LinuxBIOS project. 4,6c4,6 < * Copyright 2000 AG Electronics Ltd. < * Copyright 2003-2004 Linux Networx < * Copyright 2004 Tyan
* Copyright (C) 2000 AG Electronics Ltd. * Copyright (C) 2003-2004 Linux Networx * Copyright (C) 2004 Tyan 23a24,25 /* RAM driver for SMSC LPC47B272 Super I/O chip. */
50c52 < CHIP_NAME("smsc lpc47b272") ---
CHIP_NAME("SMSC LPC47B272 Super I/O") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/smsc/lpc47b397/superio.c LinuxBIOSv2/src/superio/smsc/lpc47b397/superio.c 214c214 < CHIP_NAME("smsc lpc47b397")
CHIP_NAME("SMSC LPC47B397 Super I/O") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/smsc/lpc47m10x/superio.c LinuxBIOSv2/src/superio/smsc/lpc47m10x/superio.c 51c51 < CHIP_NAME("smsc lpc47m10x")
CHIP_NAME("SMSC LPC47M10x Super I/O") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/smsc/lpc47n217/chip.h LinuxBIOSv2/src/superio/smsc/lpc47n217/chip.h 0a1,20 /* * This file is part of the LinuxBIOS project. * * Copyright (C) 2005 Digital Design Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/smsc/lpc47n217/Config.lb LinuxBIOSv2/src/superio/smsc/lpc47n217/Config.lb 0a1,20
## ## This file is part of the LinuxBIOS project. ## ## Copyright (C) 2005 Digital Design Corporation ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c LinuxBIOSv2/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c 2c2 < * lpc47n217_early_serial.c: Pre-RAM driver for SMSC LPC47N217 Super I/O chip ---
* This file is part of the LinuxBIOS project. 20a21,22 /* Pre-RAM driver for SMSC LPC47N217 Super I/O chip. */
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/smsc/lpc47n217/lpc47n217.h LinuxBIOSv2/src/superio/smsc/lpc47n217/lpc47n217.h 0a1,20
/* * This file is part of the LinuxBIOS project. * * Copyright (C) 2005 Digital Design Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/smsc/lpc47n217/superio.c LinuxBIOSv2/src/superio/smsc/lpc47n217/superio.c 2,7c2 < * superio.c: RAM-based driver for SMSC LPC47N217 Super I/O chip < * < * Based on LinuxBIOS code for SMSC 47B397: < * Copyright 2000 AG Electronics Ltd. < * Copyright 2003-2004 Linux Networx < * Copyright 2004 Tyan ---
* This file is part of the LinuxBIOS project. 8a4,6 * Copyright (C) 2000 AG Electronics Ltd. * Copyright (C) 2003-2004 Linux Networx * Copyright (C) 2004 Tyan 25a24,26 /* RAM-based driver for SMSC LPC47N217 Super I/O chip. */ /* Based on LinuxBIOS code for SMSC 47B397. */
56c57 < CHIP_NAME("smsc lpc47n217") ---
CHIP_NAME("SMSC LPC47N217 Super I/O") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/via/vt1211/vt1211.c LinuxBIOSv2/src/superio/via/vt1211/vt1211.c 220c220 < CHIP_NAME("VIA vt1211")
CHIP_NAME("VIA VT1211 Super I/O") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/winbond/w83627hf/superio.c LinuxBIOSv2/src/superio/winbond/w83627hf/superio.c 196c196 < CHIP_NAME("Winbond w83627hf")
CHIP_NAME("Winbond W83627HF Super I/O") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/winbond/w83627thf/superio.c LinuxBIOSv2/src/superio/winbond/w83627thf/superio.c 108c108 < CHIP_NAME("Winbond w83627thf")
CHIP_NAME("Winbond W83627THF Super I/O") diff -rbB --exclude=svn --exclude=.svn LinuxBios_mine/src/superio/winbond/w83977tf/superio.c LinuxBIOSv2/src/superio/winbond/w83977tf/superio.c 112c112 < CHIP_NAME("Winbond w83977tf")
CHIP_NAME("Winbond W83977TF Super I/O")
participants (3)
-
Ben Hewson -
ron minnich -
Stefan Reinauer