[PATCH] Athlon64 K8 fixes

[Robert Millan]

Hi,

My Athlon64 / K8 socket 939 setup needed the following adjustments to fix
memory read/write errors.  Thanks to Rudolf for hinting on which bits I
should check for.  Details:

- bit 9, mandated by spec to always be set on sodimm or socket 939 dual
   dimm.

- bit 28, enable 2T timing.  no idea why, but I get memory errors without
   it.

- bit 29, upper chip select.  mandated by spec on socket 939.

My patch also adds missing descriptions, based on the ones from the spec
(http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/2609...)

[Marc Jones]

On Wed, Nov 19, 2008 at 4:01 PM, Robert Millan  wrote:
> Hi,
>
> My Athlon64 / K8 socket 939 setup needed the following adjustments to fix
> memory read/write errors.  Thanks to Rudolf for hinting on which bits I
> should check for.  Details:
> bit 9, mandated by spec to always be set on sodimm or socket 939 dual
>
> dimm.
> bit 28, enable 2T timing.  no idea why, but I get memory errors without
>
> it.

I think that 2T timing is required when using an SO-DIMM. I did a
similar change for revf a few months ago.

Marc

[Rudolf Marek]

2T timmimg would slow things down. Registered memory 2T unbuffered 1T.
You need 2T if you have more then 2 modules, 10% of bandwidth will be wasted.

Other bits might be reserved for earlier CPU revisions. Did you check?

R.

[ron minnich]

On Wed, Nov 19, 2008 at 3:01 PM, Robert Millan  wrote:
> Hi,
>
> My Athlon64 / K8 socket 939 setup needed the following adjustments to fix
> memory read/write errors.  Thanks to Rudolf for hinting on which bits I
> should check for.  Details:
> bit 9, mandated by spec to always be set on sodimm or socket 939 dual
>
> dimm.
> bit 28, enable 2T timing.  no idea why, but I get memory errors without
>
> it.
> bit 29, upper chip select.  mandated by spec on socket 939.
>
> My patch also adds missing descriptions, based on the ones from the spec
> (http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/2609...)

Given that these settings are mainboard and socket dependent, we need
a way to do these settings that takes those factors into account.

It seems to me that setting 2T on very athlon64 platform is not the
way to do it.

Thanks for finding this and getting us this initial patch. Do you
think you can extend it in some way so we don't slow down all k8
platforms?

thanks

ron

[Robert Millan]

On Wed, Nov 19, 2008 at 03:32:26PM -0800, ron minnich wrote:
> On Wed, Nov 19, 2008 at 3:01 PM, Robert Millan  wrote:
> > Hi,
> >
> > My Athlon64 / K8 socket 939 setup needed the following adjustments to fix
> > memory read/write errors.  Thanks to Rudolf for hinting on which bits I
> > should check for.  Details:
> > bit 9, mandated by spec to always be set on sodimm or socket 939 dual
> >
> > dimm.
> > bit 28, enable 2T timing.  no idea why, but I get memory errors without
> >
> > it.
> > bit 29, upper chip select.  mandated by spec on socket 939.
> >
> > My patch also adds missing descriptions, based on the ones from the spec
> > (http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/2609...)
>
> Given that these settings are mainboard and socket dependent, we need
> a way to do these settings that takes those factors into account.
>
> It seems to me that setting 2T on very athlon64 platform is not the
> way to do it.
>
> Thanks for finding this and getting us this initial patch. Do you
> think you can extend it in some way so we don't slow down all k8
> platforms?

Okay.  Bit 29 is the easiest, as the spec reads "This bit should be set
if the 939 package is used."  This is enough for a single-DIMM setup to
work.

[Robert Millan]

On Thu, Nov 20, 2008 at 12:23:50AM +0100, Rudolf Marek wrote:
> 2T timmimg would slow things down. Registered memory 2T unbuffered 1T.
> You need 2T if you have more then 2 modules, 10% of bandwidth will be 
> wasted.

You mean 2 or more?  I have 2 and need it.  Do you know if this requirement
is specific to:

- socket 939 ?

- athlon64 ?

- non dual-channel setup ?

[Tiago Marques]

You do need to have a way to select between 1T and 2T timing and also
another timings for the memory chips, the more the better.

Best regards,
                                   Tiago Marques

On Wed, Nov 19, 2008 at 11:32 PM, ron minnich  wrote:
> On Wed, Nov 19, 2008 at 3:01 PM, Robert Millan  wrote:
> > Hi,
> >
> > My Athlon64 / K8 socket 939 setup needed the following adjustments to fix
> > memory read/write errors.  Thanks to Rudolf for hinting on which bits I
> > should check for.  Details:
> > bit 9, mandated by spec to always be set on sodimm or socket 939 dual
> >
> > dimm.
> > bit 28, enable 2T timing.  no idea why, but I get memory errors
>
> without
> > it.
> > bit 29, upper chip select.  mandated by spec on socket 939.
> >
> > My patch also adds missing descriptions, based on the ones from the spec
> > (
>
> http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/2609...
> )
> >
>
> Given that these settings are mainboard and socket dependent, we need
> a way to do these settings that takes those factors into account.
>
> It seems to me that setting 2T on very athlon64 platform is not the
> way to do it.
>
> Thanks for finding this and getting us this initial patch. Do you
> think you can extend it in some way so we don't slow down all k8
> platforms?
>
> thanks
>
> ron

[ron minnich]

On Thu, Nov 20, 2008 at 5:28 AM, Robert Millan  wrote:
> Okay.  Bit 29 is the easiest, as the spec reads "This bit should be set
> if the 939 package is used."  This is enough for a single-DIMM setup to
> work.

I like this patch. I'd like to see marc ack it but:
Acked-by: Ronald G. Minnich

[Marc Jones]

On Mon, Nov 24, 2008 at 8:48 PM, ron minnich  wrote:
> On Thu, Nov 20, 2008 at 5:28 AM, Robert Millan  wrote:
> > Okay.  Bit 29 is the easiest, as the spec reads "This bit should be set
> > if the 939 package is used."  This is enough for a single-DIMM setup to
> > work.
>
> I like this patch. I'd like to see marc ack it but:
> Acked-by: Ronald G. Minnich

I am a little hesitant to change this. Bit 28 and 29 were already
being set for all rev a-e processors. This will affect socket 754 and
940 platforms (which I assume are working) so we would need some
additional test coverage. I think that you will need to implement all
the settings in the bkdg section 4.1.3 Maximum DRAM Speed as a
Function of Loading for 2T settings.

I think that adding CPU_SOCKET_TYPE for the 754, 939 and 940 would be
a good. Maybe number them 0x07, 0x08, and 0x09. Update the
src\config\Options.lb to document the socket  numbers.

Marc