porting to GA-945GCM

[CTO of SPCTNC]

Hello. Dear Coreboot team.

Thank you for your effort for Coreboot.

I'm from China.

My name is Guangzhe Lee. and I'm new in Coreboot.

I'm porting Coreboot to Gigabyte GA-945GCM board( LGA775socket / i945GC /
ICH7 / IT8718F ).

Romstage passed successfully, but after jumping to Ramstage console message
don't appear any more.

I tried to debug by GDB (using ttyS0), but it also fail.

I try the POST code, but the post card always displays "2C"->"2D"->"2E" ->
"2F". My post codes don't appear on the post card.

Please help me.

- How can I fix the problem.

- How can I fix gdb problem.

I'm sending

-  gdb message   and

-  the console log of the booting.

Thanks and regards.

Guangzhe Lee

<<<<<<<<<<<<<<<<<<<< console message >>>>>>>>>>>>>>>>>>>

[root@localhost ~]# gdb

GNU gdb (GDB) Red Hat Enterprise Linux (7.0.1-23.el5)

Copyright (C) 2009 Free Software Foundation, Inc.

License GPLv3+: GNU GPL version 3 or later
http://gnu.org/licenses/gpl.html

This is free software: you are free to change and redistribute it.

There is NO WARRANTY, to the extent permitted by law.  Type "show copying"

and "show warranty" for details.

This GDB was configured as "i386-redhat-linux-gnu".

For bug reporting instructions, please see:

http://www.gnu.org/software/gdb/bugs/.

(gdb) file fallback/coreboot_ram.debug

Reading symbols from /root/fallback/coreboot_ram.debug...done.

(gdb) set remotebaud 115200

(gdb) target remote /dev/ttyS0

Remote debugging using /dev/ttyS0

Ignoring packet error, continuing...

warning: unrecognized item "timeout" in "qSupported" response

Ignoring packet error, continuing...

Ignoring packet error, continuing...

Ignoring packet error, continuing...

Ignoring packet error, continuing...

Quit

(gdb).

<<<<<<<<<<<<<<<<<<<< console message >>>>>>>>>>>>>>>>>>>

coreboot-4.0-3784-g1cc4737-dirty Fri Apr  5 22:44:35 BOT 2013 starting...

Intel(R) 82945GC Chipset

(G)MCH capable of up to DDR2-533

Setting up static southbridge registers... GPIOS... done.

Disabling Watchdog reboot... done.

Setting up static northbridge registers... done.

Waiting for MCHBAR to come up...ok

PM1_CNT: 00001c00

SMBus controller enabled.

Setting up RAM controller.

This mainboard supports Dual Channel Operation.

DDR II Channel 0 Socket 0: x8DDS

DDR II Channel 0 Socket 1: N/A

DDR II Channel 1 Socket 0: N/A

DDR II Channel 1 Socket 1: N/A

lowest common cas = 4

Probing Speed 2

DIMM: 0

Current CAS mask: 0070; idx=1, tCLK=30, tAC=45:    OK

DIMM: 1

DIMM: 2

DIMM: 3

freq_cas_mask for speed 2: 0030

Memory will be driven at 667MHz with CAS=4 clocks

tRAS = 15 cycles

tRP = 5 cycles

tRCD = 5 cycles

Refresh: 7.8us

tWR = 5 cycles

DIMM 0 side 0 = 1024 MB

DIMM 0 side 1 = 1024 MB

tRFC = 43 cycles

Setting Graphics Frequency...

FSB: 800 MHz Voltage: 1.05V Render: 250Mhz Display: 200MHz

Setting Memory Frequency... CLKCFG=0x20000002, CLKCFG=0x20000002, ok

Setting mode of operation for memory channels...Single Channel 0 only.

DCC=0x00000400

Programming Clock Crossing...MEM=memclk: unknown register value 0

memclk: unknown register value 0

RSVD ffffffffSetting RAM size...

C0DRB = 0x40404020

C1DRB = 0x40404040

TOLUD = 0x0080

Setting row attributes...

C0DRA = 0x0033

C1DRA = 0x0000

DIMM0 has 8 banks.

one dimm per channel config..

Initializing System Memory IO...

Programming Dual Channel RCOMP

Table Index: 19

Programming DLL Timings...

Enabling System Memory IO...

jedec enable sequence: bank 0

Apply NOP

Sending RAM command 0x00010400...done

ram read: 00000000

All Banks Precharge

Sending RAM command 0x00020400...done

ram read: 00000000

Extended Mode Register Set(2)

Sending RAM command 0x00240400...done

ram read: 00000000

Extended Mode Register Set(3)

Sending RAM command 0x00440400...done

ram read: 00000000

Extended Mode Register Set

Sending RAM command 0x00040400...done

ram read: 00000200

MRS: Reset DLLs

Sending RAM command 0x00030400...done

ram read: 00004a58

All Banks Precharge

Sending RAM command 0x00020400...done

ram read: 00000000

CAS before RAS

Sending RAM command 0x00060400...done

ram read: 00000000

ram read: 00000000

MRS: Enable DLLs

Sending RAM command 0x00030400...done

ram read: 00004258

Extended Mode Register Set: ODT/OCD

Sending RAM command 0x00040400...done

ram read: 00001e00

Extended Mode Register Set: OCD Exit

Sending RAM command 0x00040400...done

ram read: 00000200

jedec enable sequence: bank 1

bankaddr from bank size of rank 0

Apply NOP

Sending RAM command 0x00010400...done

ram read: 40000000

All Banks Precharge

Sending RAM command 0x00020400...done

ram read: 40000000

Extended Mode Register Set(2)

Sending RAM command 0x00240400...done

ram read: 40000000

Extended Mode Register Set(3)

Sending RAM command 0x00440400...done

ram read: 40000000

Extended Mode Register Set

Sending RAM command 0x00040400...done

ram read: 40000200

MRS: Reset DLLs

Sending RAM command 0x00030400...done

ram read: 40004a58

All Banks Precharge

Sending RAM command 0x00020400...done

ram read: 40000000

CAS before RAS

Sending RAM command 0x00060400...done

ram read: 40000000

ram read: 40000000

MRS: Enable DLLs

Sending RAM command 0x00030400...done

ram read: 40004258

Extended Mode Register Set: ODT/OCD

Sending RAM command 0x00040400...done

ram read: 40001e00

Extended Mode Register Set: OCD Exit

Sending RAM command 0x00040400...done

ram read: 40000200

Normal Operation

Sending RAM command 0x000f0400...done

receive_enable_autoconfig() for channel 0

find_strobes_low()

set_receive_enable() medium=0x3, coarse=0x4

set_receive_enable() medium=0x1, coarse=0x4

set_receive_enable() medium=0x1, coarse=0x4

find_strobes_edge()

set_receive_enable() medium=0x1, coarse=0x4

add_quarter_clock() mediumcoarse=11 fine=73

find_preamble()

set_receive_enable() medium=0x1, coarse=0x3

set_receive_enable() medium=0x1, coarse=0x2

add_quarter_clock() mediumcoarse=09 fine=f3

set_receive_enable() medium=0x3, coarse=0x2

normalize()

RAM initialization finished.

Setting up Egress Port RCRB

Loading port arbitration table ...ok

Wait for VC1 negotiation ...ok

Setting up DMI RCRB

Wait for VC1 negotiation ...done..

Internal graphics: enabled

Waiting for DMI hardware...ok

Enabling PCI Express x16 Link

SLOTSTS: 0000

Disabling PCI Express x16 Link

Wait for link to enter detect state... ok

Setting up Root Complex Topology

<-Setting up Root Complex Topology

high_ram_base: 0x        7f6e0000, 0x          120000

Loading image.

CBFS: CBFS_HEADER_ROM_ADDRESS: 0xffffefe0/0x80000

CBFS: CBFS location: 0x0~0x7f000, align: 64

CBFS: Looking for 'fallback/coreboot_ram' starting from 0x0.

CBFS:  - load entry 0x0 file name (16 bytes)...

CBFS:  (unmatched file @0x0: cmos_layout.bin)

CBFS:  - load entry 0x540 file name (32 bytes)...

CBFS:  (unmatched file @0x540: fallback/romstage)

CBFS:  - load entry 0xca00 file name (32 bytes)...

CBFS: Found file (offset=0xca38, len=367928).

CBFS: loading stage fallback/coreboot_ram @ 0x100000 (417880 bytes), entry @
0x1

00000

CBFS: cbfs_decompress, algo=0, src=fff8ca54, dst=100000, len=367900

CBFS: src=10f2efa, dst=10f2efa

CBFS: stage loaded.

Jumping to image.

[Paul Menzel]

Dear Guangzhe Lee,

Am Mittwoch, den 10.04.2013, 13:31 +0800 schrieb CTO of SPCTNC:

[…]
> I'm from China.
>
> My name is Guangzhe Lee. and I'm new in Coreboot.

welcome to coreboot! Could you please tell me, what your first name
(also known as given name) is. Is it Guangzhe? My first name is Paul.

Please note that coreboot is officially spelled all lowercase.y

As a side note, please adhere to the netiquette [1] and most importantly
configure your mail program, Microsoft Outlook, to just send plain text
messages and no HTML stuff.
> I'm porting Coreboot to Gigabyte GA-945GCM board( LGA775socket / i945GC /
> ICH7 / IT8718F ).

Awesome. Please always provide URLs to make looking up information easy.
On the GIGABYTE Web site I found not exactly the GA-945GCM but only some
boards with a suffix, like GA-945GCM-S2 [2].
> Romstage passed successfully, but after jumping to Ramstage console message
> don't appear any more.

That is strange. Could you also post your .config and upload your
current patch to our Gerrit instance for review [3]. (You can use your
Google Mail account for the OpenID login.)
> I tried to debug by GDB (using ttyS0), but it also fail.

I think GDB is not tested that much. Thanks for doing that. I am going
to split that problem into a separate thread though so that for example
the mailing list archive is easier to use.
> I try the POST code, but the post card always displays "2C"->"2D"->"2E" ->
> "2F". My post codes don't appear on the post card.

As we do not have your no code, we cannot say for sure where this hangs.
> Please help me.
>
> How can I fix the problem.
>
> How can I fix gdb problem.
>
> I'm sending
>
> gdb message   and
>
> the console log of the booting.

[… GDB log …]
> <<<<<<<<<<<<<<<<<<<< console message >>>>>>>>>>>>>>>>>>>
>
> coreboot-4.0-3784-g1cc4737-dirty Fri Apr  5 22:44:35 BOT 2013 starting...
>
> Intel(R) 82945GC Chipset
>
> (G)MCH capable of up to DDR2-533
>
> Setting up static southbridge registers... GPIOS... done.
>
> Disabling Watchdog reboot... done.
>
> Setting up static northbridge registers... done.
>
> Waiting for MCHBAR to come up...ok
>
> PM1_CNT: 00001c00
>
> SMBus controller enabled.
>
> Setting up RAM controller.
>
> This mainboard supports Dual Channel Operation.
>
> DDR II Channel 0 Socket 0: x8DDS
>
> DDR II Channel 0 Socket 1: N/A
>
> DDR II Channel 1 Socket 0: N/A
>
> DDR II Channel 1 Socket 1: N/A
>
> lowest common cas = 4
>
> Probing Speed 2
>
> DIMM: 0
> Current CAS mask: 0070; idx=1, tCLK=30, tAC=45:    OK
>
> DIMM: 1
>
> DIMM: 2
>
> DIMM: 3
>
> freq_cas_mask for speed 2: 0030
>
> Memory will be driven at 667MHz with CAS=4 clocks
>
> tRAS = 15 cycles
>
> tRP = 5 cycles
>
> tRCD = 5 cycles
>
> Refresh: 7.8us
>
> tWR = 5 cycles
>
> DIMM 0 side 0 = 1024 MB
>
> DIMM 0 side 1 = 1024 MB
>
> tRFC = 43 cycles
>
> Setting Graphics Frequency...
>
> FSB: 800 MHz Voltage: 1.05V Render: 250Mhz Display: 200MHz
>
> Setting Memory Frequency... CLKCFG=0x20000002, CLKCFG=0x20000002, ok
>
> Setting mode of operation for memory channels...Single Channel 0 only.
>
> DCC=0x00000400
>
> Programming Clock Crossing...MEM=memclk: unknown register value 0
>
> memclk: unknown register value 0

Not sure if the above is important.

[…]
> RAM initialization finished.

That is a good thing as RAM is the hardest part. Otherwise this was
suspected as the 945* chipset is one of the best supported and most
tested ones.
> Setting up Egress Port RCRB
>
> Loading port arbitration table ...ok
>
> Wait for VC1 negotiation ...ok
>
> Setting up DMI RCRB
>
> Wait for VC1 negotiation ...done..
>
> Internal graphics: enabled
>
> Waiting for DMI hardware...ok
>
> Enabling PCI Express x16 Link
>
> SLOTSTS: 0000
>
> Disabling PCI Express x16 Link
>
> Wait for link to enter detect state... ok
>
> Setting up Root Complex Topology
>
> <-Setting up Root Complex Topology
>
> high_ram_base: 0x        7f6e0000, 0x          120000
>
> Loading image.
>
> CBFS: CBFS_HEADER_ROM_ADDRESS: 0xffffefe0/0x80000
>
> CBFS: CBFS location: 0x0~0x7f000, align: 64
>
> CBFS: Looking for 'fallback/coreboot_ram' starting from 0x0.
>
> CBFS:  - load entry 0x0 file name (16 bytes)...
>
> CBFS:  (unmatched file @0x0: cmos_layout.bin)
>
> CBFS:  - load entry 0x540 file name (32 bytes)...
>
> CBFS:  (unmatched file @0x540: fallback/romstage)
>
> CBFS:  - load entry 0xca00 file name (32 bytes)...
>
> CBFS: Found file (offset=0xca38, len=367928).
>
> CBFS: loading stage fallback/coreboot_ram @ 0x100000 (417880 bytes), entry @
> 0x1
>
> 00000
>
> CBFS: cbfs_decompress, algo=0, src=fff8ca54, dst=100000, len=367900
>
> CBFS: src=10f2efa, dst=10f2efa
>
> CBFS: stage loaded.
>
> Jumping to image.

Normally at least the coreboot header should be printed, so jumping to
the image fails.

What upstream revision do you base your changes on? Do not forget to
post your Kconfig file `.config`. And lastly show us the content of your
ROM by pasting the output of the following command.

./build/cbfstool build/coreboot.rom print

Thanks,

Paul

[1] http://en.opensuse.org/openSUSE:Mailing_list_netiquette
[2] http://www.gigabyte.de/products/product-page.aspx?pid=2520#ov
[3] http://www.coreboot.org/Git

[Stefan Reinauer]

* CTO of SPCTNC  [130410 07:31]:
> Please help me.
> How can I fix the problem.

It sounds like you have a RAM init problem (e.g. your RAM is not
working) because the chipset (945GC) is slightly different than
the other 945 variations that we have supported (just a guess)
> How can I fix gdb problem.

GDB right now only works from ramstage, which you don't reach yet.
Hence you're out of luck. Try disabling GDB support in coreboot for
now.
> coreboot-4.0-3784-g1cc4737-dirty Fri Apr  5 22:44:35 BOT 2013 starting...
>
> Intel(R) 82945GC Chipset
> (G)MCH capable of up to DDR2-533

This is odd.. because the boards web page says it can do 667
> Setting up static southbridge registers... GPIOS... done.
> Disabling Watchdog reboot... done.
> Setting up static northbridge registers... done.
> Waiting for MCHBAR to come up...ok
> PM1_CNT: 00001c00
> SMBus controller enabled.
> Setting up RAM controller.
> This mainboard supports Dual Channel Operation.
> DDR II Channel 0 Socket 0: x8DDS
> DDR II Channel 0 Socket 1: N/A
> DDR II Channel 1 Socket 0: N/A
> DDR II Channel 1 Socket 1: N/A
> lowest common cas = 4
> Probing Speed 2
>   DIMM: 0
>     Current CAS mask: 0070; idx=1, tCLK=30, tAC=45:    OK
>   DIMM: 1
>   DIMM: 2
>   DIMM: 3
>   freq_cas_mask for speed 2: 0030
> Memory will be driven at 667MHz with CAS=4 clocks

So does this...
> FSB: 800 MHz Voltage: 1.05V Render: 250Mhz Display: 200MHz

... check if 800MHz FSB makes sense..
> Setting Memory Frequency... CLKCFG=0x20000002, CLKCFG=0x20000002, ok
> Setting mode of operation for memory channels...Single Channel 0 only.
> DCC=0x00000400
> Programming Clock Crossing...MEM=memclk: unknown register value 0
> memclk: unknown register value 0
> RSVD ffffffffSetting RAM size...

Definitely something is going wrong with the clock crossing.. you might
need a special set of clock crossing values for your chipset..

Looking at the code and the register values with the original bios might
help. Look at util/inteltool for a tool to dump those registers.
> CBFS: CBFS_HEADER_ROM_ADDRESS: 0xffffefe0/0x80000
> CBFS: CBFS location: 0x0~0x7f000, align: 64
> CBFS: Looking for 'fallback/coreboot_ram' starting from 0x0.
> CBFS:  - load entry 0x0 file name (16 bytes)...
> CBFS:  (unmatched file @0x0: cmos_layout.bin)
> CBFS:  - load entry 0x540 file name (32 bytes)...
> CBFS:  (unmatched file @0x540: fallback/romstage)
> CBFS:  - load entry 0xca00 file name (32 bytes)...
> CBFS: Found file (offset=0xca38, len=367928).
> CBFS: loading stage fallback/coreboot_ram @ 0x100000 (417880 bytes), entry @
> 0x1
> 00000
> CBFS: cbfs_decompress, algo=0, src=fff8ca54, dst=100000, len=367900
> CBFS: src=10f2efa, dst=10f2efa
> CBFS: stage loaded.
> Jumping to image.

This is usually a clear sign that RAM is not working because the code
coming after this point would run out of RAM.

You can try enabling a more comprehensive ram check here..

Stefan