It appears (from following the instructions) that I have a new board with unsupported cpu, chipset, and superIO.
00:00.0 Host bridge: Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller (rev 06) 00:1f.0 ISA bridge: Intel Corporation HM86 Express LPC Controller (rev 05)
From this page:
http://www.coreboot.org/Developer_Manual#Supporting_a_new_board_with_a_unsup...
It appears "If it is not supported by coreboot then you will have a lot of work in front of you."
What I need to find out is:
a) If it is even possible to get coreboot to work with this board? b) How much time would it take to get coreboot to work with this board? c) If there is any coreboot developers that would be willing to contract for hire to develop coreboot for this board?
It is a requirement to replace the bios with coreboot, so I am tasked with making sure it is possible (a), a rough idea of how long (b), and if we can hire somebody to develop it (c).
I appreciate any replies to any parts of the above, and I am hopeful somebody would be able to have the time needed to get paid to get coreboot onto this board.
Thank you!
Todd Weaver
Dear Todd,
It appears (from following the instructions) that I have a new board with unsupported cpu, chipset, and superIO.
00:00.0 Host bridge: Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller (rev 06) 00:1f.0 ISA bridge: Intel Corporation HM86 Express LPC Controller (rev 05)
We are interested in a BIOS for the same processor family, but a different PCH device.
c) If there is any coreboot developers that would be willing to contract for hire to develop coreboot for this board?
There is a company, Sage Engineering that ports coreboot to various processors. We are probably going to use them. See http://www.se-eng.com or to ask a question use: http://www.se-eng.com/contact/
From what I have been able to find out you need some binary "secret sauce"
that comes from Intel. This allows coreboot to do things like set up the DRAM controller and video. The problem is that Intel only lets a few people have access to this code.
For instance, for one of the people who could get this code, they claim the process is this simple: http://www.coreboot.org/pipermail/coreboot/2014-July/078275.html
It appears "If it is not supported by coreboot then you will have a lot of work in front of you."
This view, is based on not having the Intel code and writing your own code to set up the DRAM controllers. I imagine that it would be very difficult to write code for modern DRAM controllers, you have to read the EEPROMs on the DIMMs to determine the DRAM size and other characteristics, then set up the controller to match. Finally, DDR3 (used by this processor) has a training phase to get data accesses aligned in time. This might be implemented in hardware, or you might have to write code to do it. I don't know!
If you get a different story about this, I would love to hear it.
Thanks, Paul
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Paul Wilcox-Baker -
Todd Weaver