[flashrom] unusual SST39SF020 chip

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Re: [coreboot] [flashrom] flashrom...

Re: [coreboot] ram init help on...

Andriy Gapon

14 May 2008 14 May '08

8:30 p.m.

First of all, I have a very rough (and ugly!) patch that makes flashrom work on FreeBSD. I tried it for reading BIOS image and it worked.

I have an old system with MP2-BX-X, please see some description here: http://www.geocities.com/SiliconValley/3686/delta_mp2.html It is based on 440BX chipset.

Visually I was able to identify that BIOS flash chip is SST39SF020, but flashrom didn't initially recognize it. Some debugging showed that it has JEDEC ids 0x25 for vendor and 0xE5 for device. Very unusual. So I decided to let you know.

The data that flashrom read are very similar to the data in vendor provided bios .bin. There are differences in a chunk of about 12k size, I guess this is where bios stored some config data.

-- Andriy Gapon

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Carl-Daniel Hailfinger

15 May 15 May

2:32 a.m.

Hi Andriy,

On 14.05.2008 22:30, Andriy Gapon wrote:

...

First of all, I have a very rough (and ugly!) patch that makes flashrom work on FreeBSD. I tried it for reading BIOS image and it worked.

Can you mail the patch to the list? We want flashrom to be cross-platform and will try to merge the patch or at least a variant of it.

...

I have an old system with MP2-BX-X, please see some description here: http://www.geocities.com/SiliconValley/3686/delta_mp2.html It is based on 440BX chipset.

Visually I was able to identify that BIOS flash chip is SST39SF020, but flashrom didn't initially recognize it. Some debugging showed that it has JEDEC ids 0x25 for vendor and 0xE5 for device. Very unusual. So I decided to let you know.

The JEDEC vendor ID 0x25 can mean any of the following companies: - Tristar - Zarlink/Mitel - Chameleon systems - Kingmax Semiconductor - Phyworks - Power-One

None of the companies above are in the BIOS flash market AFAICS. Probably this is just a strange reading of real flash contents at ID offsets.

...

The data that flashrom read are very similar to the data in vendor provided bios .bin. There are differences in a chunk of about 12k size, I guess this is where bios stored some config data.

Can you hexdump the first 8 bytes of the bios.bin you read back from your chip?

Regards, Carl-Daniel

Andriy Gapon

8:49 a.m.

on 15/05/2008 05:32 Carl-Daniel Hailfinger said the following:

...

Hi Andriy,

On 14.05.2008 22:30, Andriy Gapon wrote:

...
First of all, I have a very rough (and ugly!) patch that makes flashrom work on FreeBSD. I tried it for reading BIOS image and it worked.

Can you mail the patch to the list? We want flashrom to be cross-platform and will try to merge the patch or at least a variant of it.

The diff is attached. But it is really very ugly and hackish. The most noisy change is that outb has different order of arguments on Linux and FreeBSD.

...

...
I have an old system with MP2-BX-X, please see some description here: http://www.geocities.com/SiliconValley/3686/delta_mp2.html It is based on 440BX chipset.

Visually I was able to identify that BIOS flash chip is SST39SF020, but flashrom didn't initially recognize it. Some debugging showed that it has JEDEC ids 0x25 for vendor and 0xE5 for device. Very unusual. So I decided to let you know.

The JEDEC vendor ID 0x25 can mean any of the following companies:

Tristar

Zarlink/Mitel

Chameleon systems

Kingmax Semiconductor

Phyworks

Power-One

None of the companies above are in the BIOS flash market AFAICS. Probably this is just a strange reading of real flash contents at ID offsets.

...
The data that flashrom read are very similar to the data in vendor provided bios .bin. There are differences in a chunk of about 12k size, I guess this is where bios stored some config data.

Can you hexdump the first 8 bytes of the bios.bin you read back from your chip?

Here it is (16 bytes): 00000000 25 e5 2d 6c 68 35 2d 52 16 00 00 9e 1f 00 00 02

It does include -lh5- signature. I was even able to split it into several chunks on that signature, decompress the chunks and even disassemble some pieces. Interestingly enough this BIOS contains original.tm1 file in addition to original.tmp and the former seems to be a trailer of the latter.

Hmm, I see that 25 e5 is present here. So it might mean that my ported code didn't properly enable flash chip communication?

-- Andriy Gapon Index: flash.h =================================================================== --- flash.h (revision 3225) +++ flash.h (working copy) @@ -286,13 +286,14 @@ void myusec_delay(int time); void myusec_calibrate_delay(); +#if 0 /* PCI handling for board/chipset_enable */ struct pci_access *pacc; struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device, uint16_t card_vendor, uint16_t card_device); +#endif - /* board_enable.c */ int board_flash_enable(const char *vendor, const char *part); void print_supported_boards(void); Index: spi.c =================================================================== --- spi.c (revision 3225) +++ spi.c (working copy) @@ -23,11 +23,13 @@ */ #include <stdio.h> -#include <pci/pci.h> #include <stdint.h> #include <string.h> #include "flash.h" +#include <machine/cpufunc.h> +#define lin_outb(x, y) outb((y), (x)) + #define ITE_SUPERIO_PORT1 0x2e #define ITE_SUPERIO_PORT2 0x4e @@ -102,14 +104,14 @@ /* Generic Super I/O helper functions */ uint8_t regval(uint16_t port, uint8_t reg) { - outb(reg, port); + lin_outb(reg, port); return inb(port + 1); } void regwrite(uint16_t port, uint8_t reg, uint8_t val) { - outb(reg, port); - outb(val, port + 1); + lin_outb(reg, port); + lin_outb(val, port + 1); } /* Helper functions for most recent ITE IT87xx Super I/O chips */ @@ -117,13 +119,13 @@ #define CHIP_ID_BYTE2_REG 0x21 static void enter_conf_mode_ite(uint16_t port) { - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); + lin_outb(0x87, port); + lin_outb(0x01, port); + lin_outb(0x55, port); if (port == ITE_SUPERIO_PORT1) - outb(0x55, port); + lin_outb(0x55, port); else - outb(0xaa, port); + lin_outb(0xaa, port); } static void exit_conf_mode_ite(uint16_t port) @@ -194,27 +199,27 @@ } switch (writecnt) { case 1: - outb(writearr[0], port + 1); + lin_outb(writearr[0], port + 1); writeenc = 0x0; break; case 2: - outb(writearr[0], port + 1); - outb(writearr[1], port + 7); + lin_outb(writearr[0], port + 1); + lin_outb(writearr[1], port + 7); writeenc = 0x1; break; case 4: - outb(writearr[0], port + 1); - outb(writearr[1], port + 4); - outb(writearr[2], port + 3); - outb(writearr[3], port + 2); + lin_outb(writearr[0], port + 1); + lin_outb(writearr[1], port + 4); + lin_outb(writearr[2], port + 3); + lin_outb(writearr[3], port + 2); writeenc = 0x2; break; case 5: - outb(writearr[0], port + 1); - outb(writearr[1], port + 4); - outb(writearr[2], port + 3); - outb(writearr[3], port + 2); - outb(writearr[4], port + 7); + lin_outb(writearr[0], port + 1); + lin_outb(writearr[1], port + 4); + lin_outb(writearr[2], port + 3); + lin_outb(writearr[3], port + 2); + lin_outb(writearr[4], port + 7); writeenc = 0x3; break; default: @@ -226,7 +231,7 @@ * Note: * We can't use writecnt directly, but have to use a strange encoding. */ - outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), port); + lin_outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), port); if (readcnt > 0) { do { @@ -454,12 +459,12 @@ int i; generic_spi_write_enable(); - outb(0x06 , it8716f_flashport + 1); - outb(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); + lin_outb(0x06 , it8716f_flashport + 1); + lin_outb(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); for (i = 0; i < 256; i++) { bios[256 * block + i] = buf[256 * block + i]; } - outb(0, it8716f_flashport); + lin_outb(0, it8716f_flashport); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-10 ms, so wait in 1 ms steps. */ @@ -529,7 +534,7 @@ myusec_delay(10); } /* resume normal ops... */ - outb(0x20, it8716f_flashport); + lin_outb(0x20, it8716f_flashport); return 0; } Index: Makefile =================================================================== --- Makefile (revision 3225) +++ Makefile (working copy) @@ -11,12 +11,12 @@ INSTALL = /usr/bin/install PREFIX = /usr/local #CFLAGS = -O2 -g -Wall -Werror -CFLAGS = -Os -Wall -Werror -DDISABLE_DOC # -DTS5300 +CFLAGS = -Os -Wall -DDISABLE_DOC # -DTS5300 OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), SunOS) -LDFLAGS = -lpci -lz +LDFLAGS = -lz else -LDFLAGS = -lpci -lz -static +LDFLAGS = -lz -static STRIP_ARGS = -s endif Index: chipset_enable.c =================================================================== --- chipset_enable.c (revision 3225) +++ chipset_enable.c (working copy) @@ -26,15 +26,154 @@ #define _LARGEFILE64_SOURCE #include <stdio.h> -#include <pci/pci.h> #include <stdlib.h> #include <sys/types.h> #include <sys/stat.h> #include <sys/mman.h> #include <fcntl.h> #include <unistd.h> +#include <string.h> #include "flash.h" +#include <sys/ioctl.h> +#include <sys/pciio.h> +#include <machine/cpufunc.h> + +#define lin_outb(x, y) outb((y), (x)) +#define pci_dev pcisel +static int pcifd; + +static struct pcisel * pci_dev_find(uint16_t vendor, uint16_t device) +{ + struct pci_conf match; + struct pci_match_conf pattern; + struct pci_conf_io confio; + struct pcisel * ret; + int rc; + + memset(&match, 0, sizeof(match)); + memset(&pattern, 0, sizeof(pattern)); + memset(&confio, 0, sizeof(confio)); + + pattern.pc_vendor = vendor; + pattern.pc_device = device; + pattern.flags = PCI_GETCONF_MATCH_VENDOR | PCI_GETCONF_MATCH_DEVICE; + + confio.pat_buf_len = sizeof(pattern); + confio.num_patterns = 1; + confio.patterns = &pattern; + confio.match_buf_len = sizeof(match); + confio.matches = &match; + + rc = ioctl(pcifd, PCIOCGETCONF, &confio); + if (rc != 0) + return NULL; + + if (confio.status == PCI_GETCONF_ERROR) + return NULL; + + if (confio.num_matches != 1) + return NULL; + + ret = (struct pcisel *)malloc(sizeof(*ret)); + *ret = match.pc_sel; + + printf("pci_dev_find success:\n"); + printf("pc_domain = %#x, pc_bus = %#x, pc_dev = %#x, pc_func = %#x\n", ret->pc_domain, ret->pc_bus, ret->pc_dev, ret->pc_func); + return ret; +} + +static uint8_t pci_read_byte(struct pcisel *dev, uint8_t reg) +{ + struct pci_io io; + + io.pi_sel = *dev; + io.pi_reg = reg; + io.pi_width = 1; + io.pi_data = 0; + + if (ioctl(pcifd, PCIOCREAD, &io) < 0) + printf("pci_read_byte failed\n"); + + return io.pi_data; +} + +static uint16_t pci_read_word(struct pcisel *dev, uint8_t reg) +{ + struct pci_io io; + + io.pi_sel = *dev; + io.pi_reg = reg; + io.pi_width = 2; + io.pi_data = 0; + + if (ioctl(pcifd, PCIOCREAD, &io) < 0) + printf("pci_read_word failed\n"); + + return io.pi_data; +} + +static uint32_t pci_read_long(struct pcisel *dev, uint8_t reg) +{ + struct pci_io io; + + io.pi_sel = *dev; + io.pi_reg = reg; + io.pi_width = 4; + io.pi_data = 0; + + if (ioctl(pcifd, PCIOCREAD, &io) < 0) + printf("pci_read_long failed\n"); + + return io.pi_data; +} + +static void pci_write_byte(struct pcisel *dev, uint8_t reg, uint8_t val) +{ + struct pci_io io; + + io.pi_sel = *dev; + io.pi_reg = reg; + io.pi_width = 1; + io.pi_data = val; + + if (ioctl(pcifd, PCIOCWRITE, &io) < 0) + printf("pci_write_byte failed\n"); + + return; +} + +static void pci_write_word(struct pcisel *dev, uint8_t reg, uint16_t val) +{ + struct pci_io io; + + io.pi_sel = *dev; + io.pi_reg = reg; + io.pi_width = 2; + io.pi_data = val; + + if (ioctl(pcifd, PCIOCWRITE, &io) < 0) + printf("pci_write_word failed\n"); + + return; +} + +static void pci_write_long(struct pcisel *dev, uint8_t reg, uint32_t val) +{ + struct pci_io io; + + io.pi_sel = *dev; + io.pi_reg = reg; + io.pi_width = 4; + io.pi_data = val; + + ioctl(pcifd, PCIOCWRITE, &io); + if (ioctl(pcifd, PCIOCWRITE, &io) < 0) + printf("pci_write_long failed\n"); + + return; +} + static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) { uint8_t tmp; @@ -65,37 +204,37 @@ /* The same thing on SiS 950 Super I/O side... */ /* First probe for Super I/O on config port 0x2e. */ - outb(0x87, 0x2e); - outb(0x01, 0x2e); - outb(0x55, 0x2e); - outb(0x55, 0x2e); + lin_outb(0x87, 0x2e); + lin_outb(0x01, 0x2e); + lin_outb(0x55, 0x2e); + lin_outb(0x55, 0x2e); if (inb(0x2f) != 0x87) { /* If that failed, try config port 0x4e. */ - outb(0x87, 0x4e); - outb(0x01, 0x4e); - outb(0x55, 0x4e); - outb(0xaa, 0x4e); + lin_outb(0x87, 0x4e); + lin_outb(0x01, 0x4e); + lin_outb(0x55, 0x4e); + lin_outb(0xaa, 0x4e); if (inb(0x4f) != 0x87) { printf("Can not access SiS 950\n"); return -1; } - outb(0x24, 0x4e); + lin_outb(0x24, 0x4e); b = inb(0x4f) | 0xfc; - outb(0x24, 0x4e); - outb(b, 0x4f); - outb(0x02, 0x4e); - outb(0x02, 0x4f); + lin_outb(0x24, 0x4e); + lin_outb(b, 0x4f); + lin_outb(0x02, 0x4e); + lin_outb(0x02, 0x4f); } - outb(0x24, 0x2e); + lin_outb(0x24, 0x2e); printf("2f is %#x\n", inb(0x2f)); b = inb(0x2f) | 0xfc; - outb(0x24, 0x2e); - outb(b, 0x2f); + lin_outb(0x24, 0x2e); + lin_outb(b, 0x2f); - outb(0x02, 0x2e); - outb(0x02, 0x2f); + lin_outb(0x02, 0x2e); + lin_outb(0x02, 0x2f); return 0; } @@ -309,8 +448,8 @@ return -1; } - if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) { - perror("lseek64"); + if (lseek(fd_msr, (off_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) { + perror("lseek"); printf("Cannot operate on MSR. Did you run 'modprobe msr'?\n"); close(fd_msr); return -1; @@ -324,8 +463,8 @@ if (buf[7] != 0x22) { buf[7] &= 0xfb; - if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) { - perror("lseek64"); + if (lseek(fd_msr, (off_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) { + perror("lseek"); close(fd_msr); return -1; } @@ -337,8 +476,8 @@ } } - if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) { - perror("lseek64"); + if (lseek(fd_msr, (off_t) MSR_NORF_CTL, SEEK_SET) == -1) { + perror("lseek"); close(fd_msr); return -1; } @@ -352,8 +491,8 @@ /* Raise WE_CS3 bit. */ buf[0] |= 0x08; - if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) { - perror("lseek64"); + if (lseek(fd_msr, (off_t) MSR_NORF_CTL, SEEK_SET) == -1) { + perror("lseek"); close(fd_msr); return -1; } @@ -461,7 +600,7 @@ return 0; } - +#if 0 /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */ static int enable_flash_sb400(struct pci_dev *dev, const char *name) { @@ -497,16 +636,16 @@ /* Now become a bit silly. */ tmp = inb(0xc6f); - outb(tmp, 0xeb); - outb(tmp, 0xeb); + lin_outb(tmp, 0xeb); + lin_outb(tmp, 0xeb); tmp |= 0x40; - outb(tmp, 0xc6f); - outb(tmp, 0xeb); - outb(tmp, 0xeb); + lin_outb(tmp, 0xc6f); + lin_outb(tmp, 0xeb); + lin_outb(tmp, 0xeb); return 0; } - +#endif static int enable_flash_mcp55(struct pci_dev *dev, const char *name) { uint8_t old, new, byte; @@ -618,7 +757,7 @@ {0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */ - {0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, +/* {0x1002, 0x4377, "ATI SB400", enable_flash_sb400},*/ {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000}, }; @@ -639,6 +778,12 @@ int ret = -2; /* Nothing! */ int i; + pcifd = open("/dev/pci", O_RDWR); + if (pcifd < 0) { + perror("/dev/pci"); + return ret; + } + /* Now let's try to find the chipset we have... */ for (i = 0; i < ARRAY_SIZE(enables); i++) { dev = pci_dev_find(enables[i].vendor, enables[i].device); Index: flashrom.c =================================================================== --- flashrom.c (revision 3225) +++ flashrom.c (working copy) @@ -30,7 +30,6 @@ #include <string.h> #include <stdlib.h> #include <getopt.h> -#include <pci/pci.h> /* for iopl */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) #include <strings.h> @@ -40,44 +39,155 @@ #endif #include "flash.h" -char *chip_to_probe = NULL; -struct pci_access *pacc; /* For board and chipset_enable */ -int exclude_start_page, exclude_end_page; -int force = 0, verbose = 0; -int fd_mem; -struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device) +#include <stdlib.h> +#include <sys/ioctl.h> +#include <sys/pciio.h> +#include <machine/cpufunc.h> + +#define lin_outb(x, y) outb((y), (x)) +#define pci_dev pcisel +static int pcifd; + +static struct pcisel * pci_dev_find(uint16_t vendor, uint16_t device) { - struct pci_dev *temp; - struct pci_filter filter; + struct pci_conf match; + struct pci_match_conf pattern; + struct pci_conf_io confio; + struct pcisel * ret; + int rc; - pci_filter_init(NULL, &filter); - filter.vendor = vendor; - filter.device = device; + memset(&match, 0, sizeof(match)); + memset(&pattern, 0, sizeof(pattern)); + memset(&confio, 0, sizeof(confio)); - for (temp = pacc->devices; temp; temp = temp->next) - if (pci_filter_match(&filter, temp)) - return temp; + pattern.pc_vendor = vendor; + pattern.pc_device = device; + pattern.flags = PCI_GETCONF_MATCH_VENDOR | PCI_GETCONF_MATCH_DEVICE; - return NULL; + confio.pat_buf_len = sizeof(pattern); + confio.num_patterns = 1; + confio.patterns = &pattern; + confio.match_buf_len = sizeof(match); + confio.matches = &match; + + rc = ioctl(pcifd, PCIOCGETCONF, &confio); + if (rc != 0) + return NULL; + + if (confio.status == PCI_GETCONF_ERROR) + return NULL; + + if (confio.num_matches != 1) + return NULL; + + ret = (struct pcisel *)malloc(sizeof(*ret)); + *ret = match.pc_sel; + return ret; } +static uint8_t pci_read_byte(struct pcisel *dev, uint8_t reg) +{ + struct pci_io io; + + io.pi_sel = *dev; + io.pi_reg = reg; + io.pi_width = 1; + io.pi_data = 0; + + ioctl(pcifd, PCIOCREAD, &io); + + return io.pi_data; +} + +static uint16_t pci_read_word(struct pcisel *dev, uint8_t reg) +{ + struct pci_io io; + + io.pi_sel = *dev; + io.pi_reg = reg; + io.pi_width = 2; + io.pi_data = 0; + + ioctl(pcifd, PCIOCREAD, &io); + + return io.pi_data; +} + +static uint32_t pci_read_long(struct pcisel *dev, uint8_t reg) +{ + struct pci_io io; + + io.pi_sel = *dev; + io.pi_reg = reg; + io.pi_width = 4; + io.pi_data = 0; + + ioctl(pcifd, PCIOCREAD, &io); + + return io.pi_data; +} + +static void pci_write_byte(struct pcisel *dev, uint8_t reg, uint8_t val) +{ + struct pci_io io; + + io.pi_sel = *dev; + io.pi_reg = reg; + io.pi_width = 1; + io.pi_data = val; + + ioctl(pcifd, PCIOCWRITE, &io); + + return; +} + +static void pci_write_word(struct pcisel *dev, uint16_t reg, uint16_t val) +{ + struct pci_io io; + + io.pi_sel = *dev; + io.pi_reg = reg; + io.pi_width = 2; + io.pi_data = val; + + ioctl(pcifd, PCIOCWRITE, &io); + + return; +} + +static void pci_write_long(struct pcisel *dev, uint32_t reg, uint32_t val) +{ + struct pci_io io; + + io.pi_sel = *dev; + io.pi_reg = reg; + io.pi_width = 4; + io.pi_data = val; + + ioctl(pcifd, PCIOCWRITE, &io); + + return; +} + +char *chip_to_probe = NULL; +struct pci_access *pacc; /* For board and chipset_enable */ +int exclude_start_page, exclude_end_page; +int force = 0, verbose = 0; +int fd_mem; + struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device, uint16_t card_vendor, uint16_t card_device) { struct pci_dev *temp; - struct pci_filter filter; + temp = pci_dev_find(vendor, device); - pci_filter_init(NULL, &filter); - filter.vendor = vendor; - filter.device = device; + if (temp == NULL) + return NULL; - for (temp = pacc->devices; temp; temp = temp->next) - if (pci_filter_match(&filter, temp)) { - if ((card_vendor == pci_read_word(temp, 0x2C)) && - (card_device == pci_read_word(temp, 0x2E))) - return temp; - } + if ((card_vendor == pci_read_word(temp, 0x2C)) && + (card_device == pci_read_word(temp, 0x2E))) + return temp; return NULL; } @@ -246,6 +356,7 @@ int option_index = 0; int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; int ret = 0; + int iofd; static struct option long_options[] = { {"read", 0, 0, 'r'}, @@ -358,22 +469,17 @@ if (optind < argc) filename = argv[optind++]; - /* First get full io access */ -#if defined (__sun) && (defined(__i386) || defined(__amd64)) - if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { -#else - if (iopl(3) != 0) { -#endif - fprintf(stderr, "ERROR: iopl failed: "%s"\n", - strerror(errno)); - exit(1); - } - /* Initialize PCI access for flash enables */ - pacc = pci_alloc(); /* Get the pci_access structure */ - /* Set all options you want -- here we stick with the defaults */ - pci_init(pacc); /* Initialize the PCI library */ - pci_scan_bus(pacc); /* We want to get the list of devices */ + iofd = open("/dev/io", O_RDWR); + if (iofd < 0) { + perror("/dev/io"); + exit(1); + } + pcifd = open("/dev/pci", O_RDWR); + if (pcifd < 0) { + perror("/dev/pci"); + exit(1); + } /* Open the memory device. A lot of functions need it */ if ((fd_mem = open(MEM_DEV, O_RDWR)) < 0) { Index: board_enable.c =================================================================== --- board_enable.c (revision 3225) +++ board_enable.c (working copy) @@ -25,48 +25,176 @@ */ #include <stdio.h> -#include <pci/pci.h> #include <stdint.h> #include <string.h> #include <fcntl.h> #include "flash.h" +#include <stdlib.h> +#include <sys/ioctl.h> +#include <sys/pciio.h> +#include <machine/cpufunc.h> + +#define lin_outb(x, y) outb((y), (x)) +#define pci_dev pcisel +static int pcifd; + +static struct pcisel * pci_dev_find(uint16_t vendor, uint16_t device) +{ + struct pci_conf match; + struct pci_match_conf pattern; + struct pci_conf_io confio; + struct pcisel * ret; + int rc; + + memset(&match, 0, sizeof(match)); + memset(&pattern, 0, sizeof(pattern)); + memset(&confio, 0, sizeof(confio)); + + pattern.pc_vendor = vendor; + pattern.pc_device = device; + pattern.flags = PCI_GETCONF_MATCH_VENDOR | PCI_GETCONF_MATCH_DEVICE; + + confio.pat_buf_len = sizeof(pattern); + confio.num_patterns = 1; + confio.patterns = &pattern; + confio.match_buf_len = sizeof(match); + confio.matches = &match; + + rc = ioctl(pcifd, PCIOCGETCONF, &confio); + if (rc != 0) + return NULL; + + if (confio.status == PCI_GETCONF_ERROR) + return NULL; + + if (confio.num_matches != 1) + return NULL; + + ret = (struct pcisel *)malloc(sizeof(*ret)); + *ret = match.pc_sel; + return ret; +} + +static uint8_t pci_read_byte(struct pcisel *dev, uint8_t reg) +{ + struct pci_io io; + + io.pi_sel = *dev; + io.pi_reg = reg; + io.pi_width = 1; + io.pi_data = 0; + + ioctl(pcifd, PCIOCREAD, &io); + + return io.pi_data; +} + +static uint16_t pci_read_word(struct pcisel *dev, uint8_t reg) +{ + struct pci_io io; + + io.pi_sel = *dev; + io.pi_reg = reg; + io.pi_width = 2; + io.pi_data = 0; + + ioctl(pcifd, PCIOCREAD, &io); + + return io.pi_data; +} + +static uint32_t pci_read_long(struct pcisel *dev, uint8_t reg) +{ + struct pci_io io; + + io.pi_sel = *dev; + io.pi_reg = reg; + io.pi_width = 4; + io.pi_data = 0; + + ioctl(pcifd, PCIOCREAD, &io); + + return io.pi_data; +} + +static void pci_write_byte(struct pcisel *dev, uint8_t reg, uint8_t val) +{ + struct pci_io io; + + io.pi_sel = *dev; + io.pi_reg = reg; + io.pi_width = 1; + io.pi_data = val; + + ioctl(pcifd, PCIOCWRITE, &io); + + return; +} + +static void pci_write_word(struct pcisel *dev, uint16_t reg, uint16_t val) +{ + struct pci_io io; + + io.pi_sel = *dev; + io.pi_reg = reg; + io.pi_width = 2; + io.pi_data = val; + + ioctl(pcifd, PCIOCWRITE, &io); + + return; +} + +static void pci_write_long(struct pcisel *dev, uint32_t reg, uint32_t val) +{ + struct pci_io io; + + io.pi_sel = *dev; + io.pi_reg = reg; + io.pi_width = 4; + io.pi_data = val; + + ioctl(pcifd, PCIOCWRITE, &io); + + return; +} /* * Helper functions for many Winbond Super I/Os of the W836xx range. */ /* Enter extended functions */ static void w836xx_ext_enter(uint16_t port) { - outb(0x87, port); - outb(0x87, port); + lin_outb(0x87, port); + lin_outb(0x87, port); } /* Leave extended functions */ static void w836xx_ext_leave(uint16_t port) { - outb(0xAA, port); + lin_outb(0xAA, port); } /* General functions for reading/writing Winbond Super I/Os. */ static unsigned char wbsio_read(uint16_t index, uint8_t reg) { - outb(reg, index); + lin_outb(reg, index); return inb(index + 1); } static void wbsio_write(uint16_t index, uint8_t reg, uint8_t data) { - outb(reg, index); - outb(data, index + 1); + lin_outb(reg, index); + lin_outb(data, index + 1); } static void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t mask) { uint8_t tmp; - outb(reg, index); + lin_outb(reg, index); tmp = inb(index + 1) & ~mask; - outb(tmp | (data & mask), index + 1); + lin_outb(tmp | (data & mask), index + 1); } /** @@ -174,7 +302,7 @@ /* Enable GPIO15 which is connected to write protect. */ val = inb(base + 0x4D); val |= 0x80; - outb(val, base + 0x4D); + lin_outb(val, base + 0x4D); return 0; } @@ -249,13 +377,13 @@ #define ASUSP5A_LOOP 5000 - outb(0x00, 0xE807); - outb(0xEF, 0xE803); + lin_outb(0x00, 0xE807); + lin_outb(0xEF, 0xE803); - outb(0xFF, 0xE800); + lin_outb(0xFF, 0xE800); for (i = 0; i < ASUSP5A_LOOP; i++) { - outb(0xE1, 0xFF); + lin_outb(0xE1, 0xFF); if (inb(0xE800) & 0x04) break; } @@ -265,10 +393,10 @@ return -1; } - outb(0x20, 0xE801); - outb(0x20, 0xE1); + lin_outb(0x20, 0xE801); + lin_outb(0x20, 0xE1); - outb(0xFF, 0xE802); + lin_outb(0xFF, 0xE802); for (i = 0; i < ASUSP5A_LOOP; i++) { tmp = inb(0xE800); @@ -284,18 +412,18 @@ tmp = inb(0xE804); tmp &= ~0x02; - outb(0x00, 0xE807); - outb(0xEE, 0xE803); + lin_outb(0x00, 0xE807); + lin_outb(0xEE, 0xE803); - outb(tmp, 0xE804); + lin_outb(tmp, 0xE804); - outb(0xFF, 0xE800); - outb(0xE1, 0xFF); + lin_outb(0xFF, 0xE800); + lin_outb(0xE1, 0xFF); - outb(0x20, 0xE801); - outb(0x20, 0xE1); + lin_outb(0x20, 0xE801); + lin_outb(0x20, 0xE1); - outb(0xFF, 0xE802); + lin_outb(0xFF, 0xE802); for (i = 0; i < ASUSP5A_LOOP; i++) { tmp = inb(0xE800); @@ -316,9 +444,9 @@ uint8_t byte; /* Set GPIO lines in the Broadcom HT-1000 southbridge. */ - outb(0x45, 0xcd6); + lin_outb(0x45, 0xcd6); byte = inb(0xcd7); - outb(byte | 0x20, 0xcd7); + lin_outb(byte | 0x20, 0xcd7); return 0; } @@ -332,12 +460,12 @@ /* Raise GPIO22. */ tmp = inb(0x4036); - outb(tmp, 0xEB); + lin_outb(tmp, 0xEB); tmp |= 0x40; - outb(tmp, 0x4036); - outb(tmp, 0xEB); + lin_outb(tmp, 0x4036); + lin_outb(tmp, 0xEB); return 0; } @@ -363,7 +491,7 @@ val = inb(port); val |= 0x80; /* Top Block Lock -- pin 8 of PLCC32 */ val |= 0x40; /* Lower Blocks Lock -- pin 7 of PLCC32 */ - outb(val, port); + lin_outb(val, port); return 0; } @@ -645,6 +773,12 @@ struct board_pciid_enable *board = NULL; int ret = 0; + pcifd = open("/dev/pci", O_RDWR); + if (pcifd < 0) { + perror("/dev/pci"); + return -1; + } + if (part) board = board_match_coreboot_name(vendor, part);

Stefan Reinauer

10:24 a.m.

Andriy Gapon wrote:

...

The diff is attached. But it is really very ugly and hackish. The most noisy change is that outb has different order of arguments on Linux and FreeBSD.

Oh this is part is really ugly, indeed but there is not much that can be done to make it really nice.

Why don't you use libpci from pciutils btw? It should work on FreeBSD ...

...

Hmm, I see that 25 e5 is present here. So it might mean that my ported code didn't properly enable flash chip communication?

What's the mainboard? Maybe the mainboard protects the chip with an additional GPIO line.

Stefan

-- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

Andriy Gapon

12:12 p.m.

on 15/05/2008 13:24 Stefan Reinauer said the following:

...

Andriy Gapon wrote:

...
The diff is attached. But it is really very ugly and hackish. The most noisy change is that outb has different order of arguments on Linux and FreeBSD.

Oh this is part is really ugly, indeed but there is not much that can be done to make it really nice.

Why don't you use libpci from pciutils btw? It should work on FreeBSD ...

Thank you for pointing me in this direction, I missed this one.

...

...
Hmm, I see that 25 e5 is present here. So it might mean that my ported code didn't properly enable flash chip communication?

What's the mainboard? Maybe the mainboard protects the chip with an additional GPIO line.

Really old one, MP2-BX-X (rev. D): http://www.geocities.com/SiliconValley/3686/delta_mp2.html

-- Andriy Gapon

Carl-Daniel Hailfinger

12:36 p.m.

On 15.05.2008 10:49, Andriy Gapon wrote:

...

on 15/05/2008 05:32 Carl-Daniel Hailfinger said the following:

...
Hi Andriy,

On 14.05.2008 22:30, Andriy Gapon wrote:

...
First of all, I have a very rough (and ugly!) patch that makes flashrom work on FreeBSD. I tried it for reading BIOS image and it worked.

Can you mail the patch to the list? We want flashrom to be cross-platform and will try to merge the patch or at least a variant of it.

The diff is attached. But it is really very ugly and hackish. The most noisy change is that outb has different order of arguments on Linux and FreeBSD.

I think we can merge the outb -> lin_outb change, though I we may want to call it outb_wrapper or somesuch. Can you send that as a separate patch?

...

...
...
I have an old system with MP2-BX-X, please see some description here: http://www.geocities.com/SiliconValley/3686/delta_mp2.html It is based on 440BX chipset.

Visually I was able to identify that BIOS flash chip is SST39SF020, but flashrom didn't initially recognize it. Some debugging showed that it has JEDEC ids 0x25 for vendor and 0xE5 for device. Very unusual. So I decided to let you know.

The JEDEC vendor ID 0x25 can mean any of the following companies:

Tristar

Zarlink/Mitel

Chameleon systems

Kingmax Semiconductor

Phyworks

Power-One

None of the companies above are in the BIOS flash market AFAICS. Probably this is just a strange reading of real flash contents at ID offsets.

...
The data that flashrom read are very similar to the data in vendor provided bios .bin. There are differences in a chunk of about 12k size, I guess this is where bios stored some config data.

Can you hexdump the first 8 bytes of the bios.bin you read back from your chip?

Here it is (16 bytes): 00000000 25 e5 2d 6c 68 35 2d 52 16 00 00 9e 1f 00 00 02

It does include -lh5- signature. I was even able to split it into several chunks on that signature, decompress the chunks and even disassemble some pieces. Interestingly enough this BIOS contains original.tm1 file in addition to original.tmp and the former seems to be a trailer of the latter.

Hmm, I see that 25 e5 is present here. So it might mean that my ported code didn't properly enable flash chip communication?

Yes, indeed. For details, see Stefan's answer. Oh, and the SST39 series are not really the ideal chips to test flashrom with. I have one of those chips which seemed to be damaged beyond repair after flashing it.

Regards, Carl-Daniel

Andriy Gapon

12:48 p.m.

on 15/05/2008 15:36 Carl-Daniel Hailfinger said the following:

...

I think we can merge the outb -> lin_outb change, though I we may want to call it outb_wrapper or somesuch. Can you send that as a separate patch?

Maybe call it "OUTB"? Will get back a little bit later with the change.

[snip]

...

Yes, indeed. For details, see Stefan's answer. Oh, and the SST39 series are not really the ideal chips to test flashrom with. I have one of those chips which seemed to be damaged beyond repair after flashing it.

I once re-flashed it in the past with official bios update using awdflash.exe. BTW, simply dd-ing from /dev/mem at the proper offset returns quite different data, so it seems that flashrom does get closer to the real bios, maybe just not close enough. I know, I am bubbling.

-- Andriy Gapon

Andriy Gapon

16 May 16 May

6:03 a.m.

on 15/05/2008 15:48 Andriy Gapon said the following:

...

on 15/05/2008 15:36 Carl-Daniel Hailfinger said the following:

...
I think we can merge the outb -> lin_outb change, though I we may want to call it outb_wrapper or somesuch. Can you send that as a separate patch?

Maybe call it "OUTB"? Will get back a little bit later with the change.

Here's a new FreeBSD porting patch. I put FreeBSD (re-)definitions into flash.h, so that they are visible in all .c files. outb is renamed to OUTB. Also, on FreeBSD for access to IO ports you have to have /dev/io open, this is added in flashrom.c. Changes in Makefile: /usr/local/include /usr/local/lib are needed in the paths for libpci. I also had to drop -Werror because compilation produced some warnings (in outb calls) that I couldn't fix: warning: comparison is always true due to limited range of data type

flashrom build obviously requires libpci (from devel/libpci port or package) and gmake.

-- Andriy Gapon Index: flash.h =================================================================== --- flash.h (revision 3322) +++ flash.h (working copy) @@ -30,6 +30,19 @@ #include <stdint.h> #include <stdio.h> +#ifdef __FreeBSD__ + #include <machine/cpufunc.h> + #define off64_t off_t + #define lseek64 lseek + #define OUTB(x, y) outb((u_int)(y), (u_char)(x)) + #define OUTW(x, y) outw((u_int)(y), (u_short)(x)) + #define OUTL(x, y) outl((u_int)(y), (u_int)(x)) +#else + #define OUTB outb + #define OUTW outw + #define OUTL outl +#endif + #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) struct flashchip { Index: it87spi.c =================================================================== --- it87spi.c (revision 3322) +++ it87spi.c (working copy) @@ -40,14 +40,14 @@ /* Generic Super I/O helper functions */ uint8_t regval(uint16_t port, uint8_t reg) { - outb(reg, port); + OUTB(reg, port); return inb(port + 1); } void regwrite(uint16_t port, uint8_t reg, uint8_t val) { - outb(reg, port); - outb(val, port + 1); + OUTB(reg, port); + OUTB(val, port + 1); } /* Helper functions for most recent ITE IT87xx Super I/O chips */ @@ -55,13 +55,13 @@ #define CHIP_ID_BYTE2_REG 0x21 static void enter_conf_mode_ite(uint16_t port) { - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); + OUTB(0x87, port); + OUTB(0x01, port); + OUTB(0x55, port); if (port == ITE_SUPERIO_PORT1) - outb(0x55, port); + OUTB(0x55, port); else - outb(0xaa, port); + OUTB(0xaa, port); } static void exit_conf_mode_ite(uint16_t port) @@ -132,27 +132,27 @@ } switch (writecnt) { case 1: - outb(writearr[0], it8716f_flashport + 1); + OUTB(writearr[0], it8716f_flashport + 1); writeenc = 0x0; break; case 2: - outb(writearr[0], it8716f_flashport + 1); - outb(writearr[1], it8716f_flashport + 7); + OUTB(writearr[0], it8716f_flashport + 1); + OUTB(writearr[1], it8716f_flashport + 7); writeenc = 0x1; break; case 4: - outb(writearr[0], it8716f_flashport + 1); - outb(writearr[1], it8716f_flashport + 4); - outb(writearr[2], it8716f_flashport + 3); - outb(writearr[3], it8716f_flashport + 2); + OUTB(writearr[0], it8716f_flashport + 1); + OUTB(writearr[1], it8716f_flashport + 4); + OUTB(writearr[2], it8716f_flashport + 3); + OUTB(writearr[3], it8716f_flashport + 2); writeenc = 0x2; break; case 5: - outb(writearr[0], it8716f_flashport + 1); - outb(writearr[1], it8716f_flashport + 4); - outb(writearr[2], it8716f_flashport + 3); - outb(writearr[3], it8716f_flashport + 2); - outb(writearr[4], it8716f_flashport + 7); + OUTB(writearr[0], it8716f_flashport + 1); + OUTB(writearr[1], it8716f_flashport + 4); + OUTB(writearr[2], it8716f_flashport + 3); + OUTB(writearr[3], it8716f_flashport + 2); + OUTB(writearr[4], it8716f_flashport + 7); writeenc = 0x3; break; default: @@ -164,7 +164,7 @@ * Note: * We can't use writecnt directly, but have to use a strange encoding. */ - outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport); + OUTB(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport); if (readcnt > 0) { do { @@ -184,12 +184,12 @@ int i; spi_write_enable(); - outb(0x06 , it8716f_flashport + 1); - outb(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); + OUTB(0x06 , it8716f_flashport + 1); + OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); for (i = 0; i < 256; i++) { bios[256 * block + i] = buf[256 * block + i]; } - outb(0, it8716f_flashport); + OUTB(0, it8716f_flashport); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-10 ms, so wait in 1 ms steps. */ @@ -215,7 +215,7 @@ myusec_delay(10); } /* resume normal ops... */ - outb(0x20, it8716f_flashport); + OUTB(0x20, it8716f_flashport); return 0; } Index: Makefile =================================================================== --- Makefile (revision 3322) +++ Makefile (working copy) @@ -11,12 +11,12 @@ INSTALL = /usr/bin/install PREFIX = /usr/local #CFLAGS = -O2 -g -Wall -Werror -CFLAGS = -Os -Wall -Werror -DDISABLE_DOC # -DTS5300 +CFLAGS = -I/usr/local/include -Os -Wall -DDISABLE_DOC # -DTS5300 OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), SunOS) LDFLAGS = -lpci -lz else -LDFLAGS = -lpci -lz +LDFLAGS = -L/usr/local/lib -lpci -lz STRIP_ARGS = -s endif Index: chipset_enable.c =================================================================== --- chipset_enable.c (revision 3322) +++ chipset_enable.c (working copy) @@ -65,37 +65,37 @@ /* The same thing on SiS 950 Super I/O side... */ /* First probe for Super I/O on config port 0x2e. */ - outb(0x87, 0x2e); - outb(0x01, 0x2e); - outb(0x55, 0x2e); - outb(0x55, 0x2e); + OUTB(0x87, 0x2e); + OUTB(0x01, 0x2e); + OUTB(0x55, 0x2e); + OUTB(0x55, 0x2e); if (inb(0x2f) != 0x87) { /* If that failed, try config port 0x4e. */ - outb(0x87, 0x4e); - outb(0x01, 0x4e); - outb(0x55, 0x4e); - outb(0xaa, 0x4e); + OUTB(0x87, 0x4e); + OUTB(0x01, 0x4e); + OUTB(0x55, 0x4e); + OUTB(0xaa, 0x4e); if (inb(0x4f) != 0x87) { printf("Can not access SiS 950\n"); return -1; } - outb(0x24, 0x4e); + OUTB(0x24, 0x4e); b = inb(0x4f) | 0xfc; - outb(0x24, 0x4e); - outb(b, 0x4f); - outb(0x02, 0x4e); - outb(0x02, 0x4f); + OUTB(0x24, 0x4e); + OUTB(b, 0x4f); + OUTB(0x02, 0x4e); + OUTB(0x02, 0x4f); } - outb(0x24, 0x2e); + OUTB(0x24, 0x2e); printf("2f is %#x\n", inb(0x2f)); b = inb(0x2f) | 0xfc; - outb(0x24, 0x2e); - outb(b, 0x2f); + OUTB(0x24, 0x2e); + OUTB(b, 0x2f); - outb(0x02, 0x2e); - outb(0x02, 0x2f); + OUTB(0x02, 0x2e); + OUTB(0x02, 0x2f); return 0; } @@ -517,12 +517,12 @@ /* Now become a bit silly. */ tmp = inb(0xc6f); - outb(tmp, 0xeb); - outb(tmp, 0xeb); + OUTB(tmp, 0xeb); + OUTB(tmp, 0xeb); tmp |= 0x40; - outb(tmp, 0xc6f); - outb(tmp, 0xeb); - outb(tmp, 0xeb); + OUTB(tmp, 0xc6f); + OUTB(tmp, 0xeb); + OUTB(tmp, 0xeb); return 0; } Index: flashrom.c =================================================================== --- flashrom.c (revision 3322) +++ flashrom.c (working copy) @@ -252,6 +252,9 @@ int option_index = 0; int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; int ret = 0, i; +#ifdef __FreeBSD__ + int io_fd; +#endif static struct option long_options[] = { {"read", 0, 0, 'r'}, @@ -367,6 +370,8 @@ /* First get full io access */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { +#elif defined(__FreeBSD__) + if ((io_fd = open("/dev/io", O_RDWR)) < 0) { #else if (iopl(3) != 0) { #endif @@ -559,5 +564,8 @@ if (verify_it) ret |= verify_flash(flash, buf); +#ifdef __FreeBSD__ + close(io_fd); +#endif return ret; } Index: board_enable.c =================================================================== --- board_enable.c (revision 3322) +++ board_enable.c (working copy) @@ -37,36 +37,36 @@ /* Enter extended functions */ static void w836xx_ext_enter(uint16_t port) { - outb(0x87, port); - outb(0x87, port); + OUTB(0x87, port); + OUTB(0x87, port); } /* Leave extended functions */ static void w836xx_ext_leave(uint16_t port) { - outb(0xAA, port); + OUTB(0xAA, port); } /* General functions for reading/writing Winbond Super I/Os. */ static unsigned char wbsio_read(uint16_t index, uint8_t reg) { - outb(reg, index); + OUTB(reg, index); return inb(index + 1); } static void wbsio_write(uint16_t index, uint8_t reg, uint8_t data) { - outb(reg, index); - outb(data, index + 1); + OUTB(reg, index); + OUTB(data, index + 1); } static void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t mask) { uint8_t tmp; - outb(reg, index); + OUTB(reg, index); tmp = inb(index + 1) & ~mask; - outb(tmp | (data & mask), index + 1); + OUTB(tmp | (data & mask), index + 1); } /** @@ -174,7 +174,7 @@ /* Enable GPIO15 which is connected to write protect. */ val = inb(base + 0x4D); val |= 0x80; - outb(val, base + 0x4D); + OUTB(val, base + 0x4D); return 0; } @@ -249,13 +249,13 @@ #define ASUSP5A_LOOP 5000 - outb(0x00, 0xE807); - outb(0xEF, 0xE803); + OUTB(0x00, 0xE807); + OUTB(0xEF, 0xE803); - outb(0xFF, 0xE800); + OUTB(0xFF, 0xE800); for (i = 0; i < ASUSP5A_LOOP; i++) { - outb(0xE1, 0xFF); + OUTB(0xE1, 0xFF); if (inb(0xE800) & 0x04) break; } @@ -265,10 +265,10 @@ return -1; } - outb(0x20, 0xE801); - outb(0x20, 0xE1); + OUTB(0x20, 0xE801); + OUTB(0x20, 0xE1); - outb(0xFF, 0xE802); + OUTB(0xFF, 0xE802); for (i = 0; i < ASUSP5A_LOOP; i++) { tmp = inb(0xE800); @@ -284,18 +284,18 @@ tmp = inb(0xE804); tmp &= ~0x02; - outb(0x00, 0xE807); - outb(0xEE, 0xE803); + OUTB(0x00, 0xE807); + OUTB(0xEE, 0xE803); - outb(tmp, 0xE804); + OUTB(tmp, 0xE804); - outb(0xFF, 0xE800); - outb(0xE1, 0xFF); + OUTB(0xFF, 0xE800); + OUTB(0xE1, 0xFF); - outb(0x20, 0xE801); - outb(0x20, 0xE1); + OUTB(0x20, 0xE801); + OUTB(0x20, 0xE1); - outb(0xFF, 0xE802); + OUTB(0xFF, 0xE802); for (i = 0; i < ASUSP5A_LOOP; i++) { tmp = inb(0xE800); @@ -316,9 +316,9 @@ uint8_t byte; /* Set GPIO lines in the Broadcom HT-1000 southbridge. */ - outb(0x45, 0xcd6); + OUTB(0x45, 0xcd6); byte = inb(0xcd7); - outb(byte | 0x20, 0xcd7); + OUTB(byte | 0x20, 0xcd7); return 0; } @@ -332,12 +332,12 @@ /* Raise GPIO22. */ tmp = inb(0x4036); - outb(tmp, 0xEB); + OUTB(tmp, 0xEB); tmp |= 0x40; - outb(tmp, 0x4036); - outb(tmp, 0xEB); + OUTB(tmp, 0x4036); + OUTB(tmp, 0xEB); return 0; } @@ -363,7 +363,7 @@ val = inb(port); val |= 0x80; /* Top Block Lock -- pin 8 of PLCC32 */ val |= 0x40; /* Lower Blocks Lock -- pin 7 of PLCC32 */ - outb(val, port); + OUTB(val, port); return 0; } @@ -462,7 +462,7 @@ */ val |= (1 << 2) | (1 << 3); - outl(val, gpiobar + ICH7_GPIO_LVL2); + OUTL(val, gpiobar + ICH7_GPIO_LVL2); return 0; }

Andriy Gapon

8:27 a.m.

on 15/05/2008 13:24 Stefan Reinauer said the following:

...

What's the mainboard? Maybe the mainboard protects the chip with an additional GPIO line.

Yes, this turned out to be the case. I glimpsed "somewhere" that on this motherboard value in IO register 0x4037 has to be and-ed with 0xef to enable writing to BIOS area (i.e. bit 4 has to be cleared). In my particular configuration 0x4000 is power-management IO base of PIIX4. And PIIX4 spec says that registers 0x34-37 control GPO signals (general purpose outputs). So this would make it, what, GPO28.

I did that and: $ ./flashrom -r -v -f bios.3.dd Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel PIIX4/4E/4M", enabling flash write... OK. SST39SF020A found at physical address 0xfffc0000. Flash part is SST39SF020A (256 KB). === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom@coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Reading Flash...done Verifying flash... VERIFIED.

-- Andriy Gapon

Carl-Daniel Hailfinger

11:22 p.m.

On 16.05.2008 10:27, Andriy Gapon wrote:

...

on 15/05/2008 13:24 Stefan Reinauer said the following:

...
What's the mainboard? Maybe the mainboard protects the chip with an additional GPIO line.

Yes, this turned out to be the case. I glimpsed "somewhere" that on this motherboard value in IO register 0x4037 has to be and-ed with 0xef to enable writing to BIOS area (i.e. bit 4 has to be cleared). In my particular configuration 0x4000 is power-management IO base of PIIX4. And PIIX4 spec says that registers 0x34-37 control GPO signals (general purpose outputs). So this would make it, what, GPO28.

I did that and: $ ./flashrom -r -v -f bios.3.dd Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel PIIX4/4E/4M", enabling flash write... OK. SST39SF020A found at physical address 0xfffc0000. Flash part is SST39SF020A (256 KB). === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom@coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Reading Flash...done Verifying flash... VERIFIED.

Very nice. Can you send a patch which adds a board enable routine for your board?

Regards, Carl-Daniel

Carl-Daniel Hailfinger

11:29 p.m.

On 16.05.2008 08:03, Andriy Gapon wrote:

...

on 15/05/2008 15:48 Andriy Gapon said the following:

...
on 15/05/2008 15:36 Carl-Daniel Hailfinger said the following:

...
I think we can merge the outb -> lin_outb change, though I we may want to call it outb_wrapper or somesuch. Can you send that as a separate patch?

Maybe call it "OUTB"? Will get back a little bit later with the change.

Here's a new FreeBSD porting patch. I put FreeBSD (re-)definitions into flash.h, so that they are visible in all .c files. outb is renamed to OUTB. Also, on FreeBSD for access to IO ports you have to have /dev/io open, this is added in flashrom.c. Changes in Makefile: /usr/local/include /usr/local/lib are needed in the paths for libpci. I also had to drop -Werror because compilation produced some warnings (in outb calls) that I couldn't fix: warning: comparison is always true due to limited range of data type

flashrom build obviously requires libpci (from devel/libpci port or package) and gmake.

Thanks for the patch! It looks quite nice and I think we can merge it, but you'll have to rework the Makefile changes. I suggest to rework the Makefile as a separate patch.

Please add a Signed-off-by statement to your patch, otherwise we can't commit. See http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure for details.

Regards, Carl-Daniel

Andriy Gapon

17 May 17 May

8:52 a.m.

on 17/05/2008 02:29 Carl-Daniel Hailfinger said the following:

...

On 16.05.2008 08:03, Andriy Gapon wrote:

...
on 15/05/2008 15:48 Andriy Gapon said the following:

...
on 15/05/2008 15:36 Carl-Daniel Hailfinger said the following:

...
I think we can merge the outb -> lin_outb change, though I we may want to call it outb_wrapper or somesuch. Can you send that as a separate patch?

Maybe call it "OUTB"? Will get back a little bit later with the change.

Here's a new FreeBSD porting patch. I put FreeBSD (re-)definitions into flash.h, so that they are visible in all .c files. outb is renamed to OUTB. Also, on FreeBSD for access to IO ports you have to have /dev/io open, this is added in flashrom.c. Changes in Makefile: /usr/local/include /usr/local/lib are needed in the paths for libpci. I also had to drop -Werror because compilation produced some warnings (in outb calls) that I couldn't fix: warning: comparison is always true due to limited range of data type

flashrom build obviously requires libpci (from devel/libpci port or package) and gmake.

Thanks for the patch! It looks quite nice and I think we can merge it, but you'll have to rework the Makefile changes. I suggest to rework the Makefile as a separate patch.

Please add a Signed-off-by statement to your patch, otherwise we can't commit. See http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure for details.

I've just done that. BTW, I've just also determined that the warning is because of the type used by flashrom for IO port number. It is uint16_t, and FreeBSD apparently supports uint32_t and has some checks for actual value. If I change type of variables/parameters used to store the port number to uint32_t the the warning goes away. Do you think it would be good to make this change in flashrom sources? Or is it better to write more elaborate wrappers that would use temporary variable of uint32_t type?

-- Andriy Gapon

Andriy Gapon

9:58 a.m.

Add support for Delta MP2-BX-X motherboard. http://www.geocities.com/SiliconValley/3686/delta_mp2.html

Signed-off-by: Andriy Gapon avg@icyb.net.ua

This board can not be uniquely identified by PCI devices, all of them are part of 440BX/PIIX4E chipset.

-- Andriy Gapon Index: board_enable.c =================================================================== --- board_enable.c (revision 3322) +++ board_enable.c (working copy) @@ -466,8 +466,38 @@ OUTL(val, gpiobar + ICH7_GPIO_LVL2); return 0; } +static int board_mp2_bx_x(const char *name) +{ + struct pci_dev *dev; + uint16_t gpiobar; + uint32_t val; + + /* On this board GPO28 has to be set to low, + * see PIIX4 specification for details. + */ + dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 */ + if (!dev) { + // This will never happen on this board + fprintf(stderr, "\nERROR: PIIX4 not found.\n"); + return -1; + } + + /* Use PMBA register for Power Management IO Base, + * GPO ports are in Power Management region. + */ + gpiobar = pci_read_word(dev, 0x40) & 0xfffc; + + /* GPO28 is bit 4 of port 0x37. */ + val = INL(gpiobar + 0x37); + printf_debug("\nGPIOBAR=0x%04x, port 0x37: 0x%08x\n", gpiobar, val); + val &= ~(1 << 4); + OUTL(val, gpiobar + 0x37); + + return 0; +} + /** * We use 2 sets of IDs here, you're free to choose which is which. This * is to provide a very high degree of certainty when matching a board on @@ -535,6 +565,8 @@ "artecgroup", "dbe62", "Artec Group DBE62", board_artecgroup_dbe6x}, {0x8086, 0x27b8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, "kontron", "986lcd-m", "Kontron 986LCD-M", board_kontron_986lcd_m}, + {0x8086, 0x7113, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + "delta", "mp2-bx-x", "Delta MP2-BX-X", board_mp2_bx_x}, {0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} /* Keep this */ };

Andriy Gapon

20 May 20 May

6:54 a.m.

on 17/05/2008 12:58 Andriy Gapon said the following:

...

Add support for Delta MP2-BX-X motherboard. http://www.geocities.com/SiliconValley/3686/delta_mp2.html

Signed-off-by: Andriy Gapon avg@icyb.net.ua

This board can not be uniquely identified by PCI devices, all of them are part of 440BX/PIIX4E chipset.

By the way this chip (SST39SF020) and this motherboard can be marked as tested. Past weekend I used (patched) flashrom to read bios and then to write a slightly modified version (cpu microcode updated) and that worked without any issue. Thank you!

-- Andriy Gapon

Andriy Gapon

29 May 29 May

8:58 a.m.

New subject: [flashrom] support for delta mp2-bx-x motherboard (tested)

Add support for Delta MP2-BX-X motherboard. It requires lowering of of PIIX4 GPO#28 for write access. http://www.geocities.com/SiliconValley/3686/delta_mp2.html

Signed-off-by: Andriy Gapon avg@icyb.net.ua

This board can not be uniquely identified by PCI devices, all of them are part of 440BX/PIIX4E chipset.

P.S. I sent this patch to the list before, but decided to re-send it again. I successfully tested the attached patch with flashrom on FreeBSD for both reading and writing. Flash RAM chip is SST39SF020.

Luc Verhaegen

1 Jun 1 Jun

9:10 a.m.

New subject: [flashrom] support for delta mp2-bx-x motherboard (tested)

On Thu, May 29, 2008 at 11:58:10AM +0300, Andriy Gapon wrote:

...

This board can not be uniquely identified by PCI devices, all of them are part of 440BX/PIIX4E chipset.

...

"artecgroup", "dbe62", "Artec Group DBE62", board_artecgroup_dbe6x},
{0x8086, 0x27b8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, "kontron", "986lcd-m", "Kontron 986LCD-M", board_kontron_986lcd_m},
{0x8086, 0x7113, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
"delta", "mp2-bx-x", "Delta MP2-BX-X", board_mp2_bx_x},
{0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} /* Keep this */
};

I see a lot of 0's in the pci-id list, same for the kontron board.

Surely at least one other set of main device ids can be put in there. Due to the lack of subsystem ids this will not give you unique identification, but this will provide an additional safeguard.

For the recent kontron board, though, nothing less than a full set seems acceptable. Unless kontron, as an embedded vendor, couldn't be bothered with card ids as usual.

Luc Verhaegen. SUSE/Novell X Driver Developer.

5838

days inactive

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coreboot@coreboot.org

15 comments

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participants (4)

Andriy Gapon
Carl-Daniel Hailfinger
Luc Verhaegen
Stefan Reinauer