Re: [coreboot] New patch to review for coreboot: fc29761 amdk8: Increase limits for MMIO to TOLM..MMCONF

[Patrick Georgi]

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Am 12.03.2013 22:28, schrieb yhlu:
> On Tue, Mar 12, 2013 at 7:04 AM, Patrick Georgi
>  wrote:
> > as in our case, a bug in the coreboot resource allocator that 
> > leaves devices unallocated.
>
> What is the bar address?

0 - thinking about it, there's the other possibility that the (custom)
hardware in question takes longer to enable its PCIe side which didn't
matter on the PCBIOS system it was developed on since that took long
enough to boot.
> Do you have kernel boot log that complains that?

Not at hand, sorry.
Essentially, the kernel determines a 0 BAR for the device and its
bridge and starts allocating them in the region given by ACPI.

ACPI reports the extended region, but the registers we modify in this
change don't cover it completely.

Patrick
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New patch to review for coreboot: fc29761 amdk8: Increase limits for MMIO to TOLM..MMCONF

[yhlu]

On Tue, Mar 12, 2013 at 4:16 PM, Patrick Georgi  wrote:
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> Hash: SHA1
>
> Am 12.03.2013 22:28, schrieb yhlu:
> > On Tue, Mar 12, 2013 at 7:04 AM, Patrick Georgi
> >  wrote:
> > > as in our case, a bug in the coreboot resource allocator that
> > > leaves devices unallocated.
> >
> > What is the bar address?
>
> 0 - thinking about it, there's the other possibility that the (custom)
> hardware in question takes longer to enable its PCIe side which didn't
> matter on the PCBIOS system it was developed on since that took long
> enough to boot.

I mean register index in pci config space.

is it in 0x10 to 0x30? or 0x184 or 0x190 etc?

Thanks

Yinghai