Hi,
I want to start a port on the Lenovo Carbon X1. I'm a BIOS newbie and don't know much about chipsets, so I'll need your support here. But I've enough C programming experience to get the job done with your help (I hope).
At the moment I'm collecting information about the hardware:
The mainboard has two flash chips: EN25QH64: 8MB Flash MX25L3206E: 4MB Flash
I know already from IRC that "Intel Corporation 3rd Gen Core processor" means Ivy bridge. That's all for now.
Hopefully somebody can help me with identifying all necessary chipset info from the lspci and dmidecode output below.
Then I've a lot of questions:
1.) What is the minimum configuration to get started and a linux kernel booted? northbridge, southbridge, RAM init? what else? Because the kernel can be a payload in the flash even SATA controller is not necessary, right? Advanced stuff as network boot is not necessary.
2.) From my basic understanding I believe as soon as the kernel gets executed everything else gets initialized by the kernel and the BIOS is not needed anymore. Is that right?
3.) For diagnostics I think VGA output is necessary. This board has no UART, only USB, and this would require initializing USB controller and communicating using a usb/serial converter. What do you think is the easier way for debug output?
I've already read this article here: http://www.coreboot.org/VGA_support%5B1] And it seems like extracting the VGA ROM via the kernel works here:
lspci -tv: -[0000:00]-+-00.0 Intel Corporation 3rd Gen Core processor DRAM Controller +-02.0 Intel Corporation 3rd Gen Core processor Graphics ...
ls -l /sys/devices/pci0000:00/0000:00:02.0/rom -rw------- 1 root root 131072 Dec 13 12:16 /sys/devices/pci0000:00/0000:00:02.0/rom
echo 1 > /sys/devices/pci0000:00/0000:00:02.0/rom cp /sys/devices/pci0000:00/0000:00:02.0/rom vgabios.bin hexdump -C vgabios.bin > vgabios.bin.hex
Here are the 1st 10 lines of the vgabios hexdump: 00000000 55 aa 80 e9 78 ea 30 30 30 30 30 30 30 30 30 30 | U...x.0000000000| 00000010 30 30 40 25 e9 59 24 97 40 00 b0 0a 30 30 49 42 | 00@%.Y$.@...00IB| 00000020 4d 20 56 47 41 20 43 6f 6d 70 61 74 69 62 6c 65 |M VGA Compatible| 00000030 20 42 49 4f 53 2e 20 03 6e 00 7e 00 8c 00 8b c0 | BIOS. .n.~.....| 00000040 50 43 49 52 86 80 06 01 1c 00 1c 00 03 00 00 03 | PCIR............| 00000050 80 00 00 00 00 80 80 00 00 00 00 00 06 01 16 01 |................| 00000060 26 01 56 01 66 01 76 01 86 01 00 00 6e 03 00 c0 | &.V.f.v.....n...| 00000070 00 00 00 00 00 00 00 00 00 00 00 00 88 00 00 c0 |................| 00000080 00 00 00 00 00 00 00 00 1a 00 37 03 00 c0 00 00 |..........7.....| 00000090 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
looks promising ;-)
More info about the HW comes here:
lspci output: 00:00.0 Host bridge: Intel Corporation 3rd Gen Core processor DRAM Controller (rev 09) 00:02.0 VGA compatible controller: Intel Corporation 3rd Gen Core processor Graphics Controller (rev 09) 00:14.0 USB controller: Intel Corporation 7 Series/C210 Series Chipset Family USB xHCI Host Controller (rev 04) 00:16.0 Communication controller: Intel Corporation 7 Series/C210 Series Chipset Family MEI Controller #1 (rev 04) 00:16.3 Serial controller: Intel Corporation 7 Series/C210 Series Chipset Family KT Controller (rev 04) 00:1a.0 USB controller: Intel Corporation 7 Series/C210 Series Chipset Family USB Enhanced Host Controller #2 (rev 04) 00:1b.0 Audio device: Intel Corporation 7 Series/C210 Series Chipset Family High Definition Audio Controller (rev 04) 00:1c.0 PCI bridge: Intel Corporation 7 Series/C210 Series Chipset Family PCI Express Root Port 1 (rev c4) 00:1c.1 PCI bridge: Intel Corporation 7 Series/C210 Series Chipset Family PCI Express Root Port 2 (rev c4) 00:1d.0 USB controller: Intel Corporation 7 Series/C210 Series Chipset Family USB Enhanced Host Controller #1 (rev 04) 00:1f.0 ISA bridge: Intel Corporation QS77 Express Chipset LPC Controller (rev 04) 00:1f.2 SATA controller: Intel Corporation 7 Series Chipset Family 6-port SATA Controller [AHCI mode] (rev 04) 00:1f.3 SMBus: Intel Corporation 7 Series/C210 Series Chipset Family SMBus Controller (rev 04) 02:00.0 System peripheral: Ricoh Co Ltd PCIe SDXC/MMC Host Controller (rev 07) 03:00.0 Network controller: Intel Corporation Centrino Advanced-N 6205 [Taylor Peak] (rev 96)
lsusb output: Bus 002 Device 003: ID 0bdb:1926 Ericsson Business Mobile Networks BV Bus 002 Device 002: ID 8087:0024 Intel Corp. Integrated Rate Matching Hub Bus 002 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub Bus 001 Device 005: ID 04f2:b315 Chicony Electronics Co., Ltd Bus 001 Device 004: ID 0a5c:21e6 Broadcom Corp. BCM20702 Bluetooth 4.0 [ThinkPad] Bus 001 Device 003: ID 147e:2020 Upek TouchChip Fingerprint Coprocessor (WBF advanced mode) Bus 001 Device 002: ID 8087:0024 Intel Corp. Integrated Rate Matching Hub Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
dmidecode output: # dmidecode 2.12 SMBIOS 2.7 present. 71 structures occupying 2762 bytes. Table at 0xDAE9D000.
Handle 0x0000, DMI type 134, 16 bytes OEM-specific Type Header and Data: 86 10 00 00 00 53 54 4D 20 01 01 00 00 03 01 02 Strings: TPM INFO System Reserved
Handle 0x0001, DMI type 4, 42 bytes Processor Information Socket Designation: CPU Socket - U3E1 Type: Central Processor Family: Core i7
Hi Gerhard,
Great idea, maybe some of the code can be recycled from the x230 port which features similar Ivy Bridge hardware? Would also be great if you could document your proceedings with the code and the flash procedure (e.g. on a blog article). There is still a severe lack of coreboot howtos imo - especially regarding newer, post-X200 Thinkpads.
greetings noq2
Hi noq2,
yes, I'll document my steps and progress. A soon as there is something to write about I'll put it on my blog.
For now I only have a simple note on how to get autoport working. All deps can be installed via package manager, except acpitool (on gentoo). You need to go into the kernel sources and build it there. su cd /usr/src/linux/tools make acpi
This could be mentioned in util/autoport/readme.md
Cheers.
On Sunday, December 13, 2015 01:59:57 PM NOQ2 Webmaster wrote:
Hi Gerhard,
Great idea, maybe some of the code can be recycled from the x230 port which features similar Ivy Bridge hardware? Would also be great if you could document your proceedings with the code and the flash
procedure
(e.g. on a blog article). There is still a severe lack of coreboot howtos imo - especially regarding newer, post-X200 Thinkpads.
greetings noq2
-
Gerhard Gappmeier -
NOQ2 Webmaster