[commit] r4997 - in trunk/src: . arch/i386 cpu/intel/model_106cx cpu/intel/model_6ex cpu/intel/model_6fx cpu/via/model_c7 cpu/x86 mainboard/kontron/986lcd-m

Author: oxygene
Date: 2010-01-04 21:09:27 +0100 (Mon, 04 Jan 2010)
New Revision: 4997

Modified:
   trunk/src/Kconfig
   trunk/src/arch/i386/Makefile.tinybootblock.inc
   trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
   trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c
   trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
   trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c
   trunk/src/cpu/intel/model_6fx/cache_as_ram.inc
   trunk/src/cpu/intel/model_6fx/cache_as_ram_disable.c
   trunk/src/cpu/via/model_c7/Kconfig
   trunk/src/cpu/x86/Kconfig
   trunk/src/mainboard/kontron/986lcd-m/Kconfig
   trunk/src/mainboard/kontron/986lcd-m/Makefile.inc
Log:
- Fix UDELAY options and HAVE_INIT_TIMER [kconfig]
  (defaults to UDELAY_IO again, like newconfig)
- Use UDELAY_TSC on Via C7 [kconfig]
- Support Tinybootblock on Intel CPUs
- set XIP location correctly for Tinybootblock on Intel
- provide correct XIP location in Tinybootblock configuration
- Make kontron/986lcd-m use Tinybootblock
- Some kconfig fixes to kontron/986lcd-m [kconfig]

Signed-off-by: Patrick Georgi 
Acked-by: Stefan Reinauer

Modified: trunk/src/Kconfig
===================================================================
--- trunk/src/Kconfig	2010-01-04 14:36:55 UTC (rev 4996)
+++ trunk/src/Kconfig	2010-01-04 20:09:27 UTC (rev 4997)
@@ -186,6 +186,7 @@

config HAVE_INIT_TIMER
    bool
+	default n if UDELAY_IO
    default y

config HAVE_MAINBOARD_RESOURCES

Modified: trunk/src/arch/i386/Makefile.tinybootblock.inc
===================================================================
--- trunk/src/arch/i386/Makefile.tinybootblock.inc	2010-01-04 14:36:55 UTC (rev 4996)
+++ trunk/src/arch/i386/Makefile.tinybootblock.inc	2010-01-04 20:09:27 UTC (rev 4997)
@@ -67,13 +67,13 @@
 # Build the romstage
 $(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $(initobjs) $(obj)/romstage/ldscript.ld
    @printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	printf "CONFIG_ROMBASE = 0x0;\n" > $(obj)/location.ld
+	printf "CONFIG_ROMBASE = 0x0;\nAUTO_XIP_ROM_BASE = 0x0;\n" > $(obj)/location.ld
    $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(initobjs)
    $(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin
    printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld
    $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin fallback/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt
    cat $(obj)/location.txt >> $(obj)/location.ld
-	printf ";\n" >> $(obj)/location.ld
+	printf ';\nAUTO_XIP_ROM_BASE = CONFIG_ROMBASE & ~(CONFIG_XIP_ROM_SIZE - 1);\n' >> $(obj)/location.ld
    $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(initobjs)
    $(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map
    $(OBJCOPY) -O binary $(obj)/romstage.elf $@

Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
===================================================================
--- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc	2010-01-04 14:36:55 UTC (rev 4996)
+++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc	2010-01-04 20:09:27 UTC (rev 4997)
@@ -114,7 +114,13 @@
    /* Enable cache for our code in Flash because we do XIP here */
         movl    $MTRRphysBase_MSR(1), %ecx
         xorl    %edx, %edx
-        movl    $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+#endif
+        movl    $REAL_XIP_ROM_BASE, %eax
+        orl     $MTRR_TYPE_WRBACK, %eax
         wrmsr

movl    $MTRRphysMask_MSR(1), %ecx

Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c
===================================================================
--- trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c	2010-01-04 14:36:55 UTC (rev 4996)
+++ trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c	2010-01-04 20:09:27 UTC (rev 4997)
@@ -25,6 +25,7 @@
 {
    unsigned int cpu_reset = 0;

+#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
 #if CONFIG_USE_FALLBACK_IMAGE == 1
         /* Is this a deliberate reset by the bios */
         if (bios_reset_detected() && last_boot_normal()) {
@@ -46,6 +47,7 @@
                 );
  fallback_image:
 #endif
+#endif

real_main(bist);

Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
===================================================================
--- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc	2010-01-04 14:36:55 UTC (rev 4996)
+++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc	2010-01-04 20:09:27 UTC (rev 4997)
@@ -104,7 +104,13 @@
    /* Enable cache for our code in Flash because we do XIP here */
         movl    $MTRRphysBase_MSR(1), %ecx
         xorl    %edx, %edx
-        movl    $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+#endif
+        movl    $REAL_XIP_ROM_BASE, %eax
+        orl     $MTRR_TYPE_WRBACK, %eax
         wrmsr

movl    $MTRRphysMask_MSR(1), %ecx

Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c
===================================================================
--- trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c	2010-01-04 14:36:55 UTC (rev 4996)
+++ trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c	2010-01-04 20:09:27 UTC (rev 4997)
@@ -27,6 +27,7 @@
 {
    unsigned int cpu_reset = 0;

+#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
 #if CONFIG_USE_FALLBACK_IMAGE == 1
         /* Is this a deliberate reset by the bios */
         if (bios_reset_detected() && last_boot_normal()) {
@@ -48,6 +49,7 @@
                 );
  fallback_image:
 #endif
+#endif

real_main(bist);

Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc
===================================================================
--- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc	2010-01-04 14:36:55 UTC (rev 4996)
+++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc	2010-01-04 20:09:27 UTC (rev 4997)
@@ -111,7 +111,13 @@
    /* Enable cache for our code in Flash because we do XIP here */
         movl    $MTRRphysBase_MSR(1), %ecx
         xorl    %edx, %edx
-        movl    $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+#endif
+        movl    $REAL_XIP_ROM_BASE, %eax
+        orl     $MTRR_TYPE_WRBACK, %eax
         wrmsr

movl    $MTRRphysMask_MSR(1), %ecx

Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram_disable.c
===================================================================
--- trunk/src/cpu/intel/model_6fx/cache_as_ram_disable.c	2010-01-04 14:36:55 UTC (rev 4996)
+++ trunk/src/cpu/intel/model_6fx/cache_as_ram_disable.c	2010-01-04 20:09:27 UTC (rev 4997)
@@ -27,6 +27,7 @@
 {
    unsigned int cpu_reset = 0;

+#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
 #if CONFIG_USE_FALLBACK_IMAGE == 1
         /* Is this a deliberate reset by the bios */
         if (bios_reset_detected() && last_boot_normal()) {
@@ -48,6 +49,7 @@
                 );
  fallback_image:
 #endif
+#endif

real_main(bist);

Modified: trunk/src/cpu/via/model_c7/Kconfig
===================================================================
--- trunk/src/cpu/via/model_c7/Kconfig	2010-01-04 14:36:55 UTC (rev 4996)
+++ trunk/src/cpu/via/model_c7/Kconfig	2010-01-04 20:09:27 UTC (rev 4997)
@@ -1,2 +1,3 @@
 config CPU_VIA_C7
    bool
+	select UDELAY_TSC

Modified: trunk/src/cpu/x86/Kconfig
===================================================================
--- trunk/src/cpu/x86/Kconfig	2010-01-04 14:36:55 UTC (rev 4996)
+++ trunk/src/cpu/x86/Kconfig	2010-01-04 20:09:27 UTC (rev 4997)
@@ -8,6 +8,7 @@

config UDELAY_IO
    bool
+	default y if !UDELAY_LAPIC && !UDELAY_TSC
    default n

config UDELAY_LAPIC

Modified: trunk/src/mainboard/kontron/986lcd-m/Kconfig
===================================================================
--- trunk/src/mainboard/kontron/986lcd-m/Kconfig	2010-01-04 14:36:55 UTC (rev 4996)
+++ trunk/src/mainboard/kontron/986lcd-m/Kconfig	2010-01-04 20:09:27 UTC (rev 4997)
@@ -21,7 +21,7 @@
    select IOAPIC
    select USE_DCACHE_RAM
    select GFXUMA
-	select HAVE_MOVNTI
+	select TINY_BOOTBLOCK

config MAINBOARD_DIR
    string
@@ -72,8 +72,3 @@
    string
    default "amipci_01.20"
    depends on BOARD_KONTRON_986LCD_M
-
-config HAVE_ACPI_SLIC
-	bool
-	default n
-	depends on BOARD_KONTRON_986LCD_M

Modified: trunk/src/mainboard/kontron/986lcd-m/Makefile.inc
===================================================================
--- trunk/src/mainboard/kontron/986lcd-m/Makefile.inc	2010-01-04 14:36:55 UTC (rev 4996)
+++ trunk/src/mainboard/kontron/986lcd-m/Makefile.inc	2010-01-04 20:09:27 UTC (rev 4997)
@@ -40,18 +40,12 @@

initobj-y += crt0.o
 # FIXME in $(top)/Makefile
-crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
-crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/cpu/intel/model_6ex/cache_as_ram.inc
 crt0-y += auto.inc

ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
-ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
-ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/arch/i386/lib/id.lds
-ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+ldscript-y += ../../../../src/cpu/x86/32bit/entry32.lds

ifdef POST_EVALUATION