Hello, Now that I got coreboot running on the IP1000, I finally am able to test out the so-dimm socket. I maxed out the slot with a big 512MB so-dimm. I don't think the "for" statement we came up with is working correctly:
/* NOTE: Dual-sided ready. */ read32(0 + addr_offset); for (i = 0; i < 4; i++) { reg8 = pci_read_config8(ctrl->d0, DRB + i); if (reg8 != reg8_2) read32(reg8 * 32 * 1024 * 1024); reg8_2 = reg8; }
The memory is detecting correctly, but I don't think coreboot can find the end of the side of the so-dimm, thus causing a lockup after Jumping to coreboot. I think I need to setup something more like the E7501 do_ram_command() but I want to keep it simple. Here is the bootlog, Help??
coreboot-2.0.0_IP1000 Tue May 27 21:18:23 EDT 2008 starting... Setting initial registers.... Initial registers have been set. Found DIMM in slot 00 DIMM is 0x0100 on side 1 DIMM is 0x0100 on side 2 DRB 0x60 has been set to 0x08 DRB1 0x61 has been set to 0x10 Found DIMM in slot 01 DIMM is 0x0040 on side 1 DIMM is 0x0000 on side 2 DRB2 0x62 has been set to 0x12 DRB3 0x63 has been set to 0x12 Found DIMM in slot 00, setting DRA... DRA 0x70 has been set to 0x08 Found DIMM in slot 01, setting DRA... DRA 0x71 has been set to 0xf1 RAM Enable 1: Apply NOP Sending RAM command 0x00000010 to 0x00000000 RAM Enable 2: Precharge all Sending RAM command 0x00000020 to 0x00000000 RAM Enable 3: CBR Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 RAM Enable 4: Mode register set Sending RAM command 0x00000030 to 0x000001d0 RAM Enable 5: Normal operation Sending RAM command 0x20000270 to 0x00000000 Northbridge following SDRAM init: PCI: 00:00.00 00: 86 80 75 35 06 00 10 20 04 00 00 06 00 00 00 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 01 00 00 00 00 00 00 00 00 02 28 00 0e 50: 72 a0 40 00 00 00 00 00 00 30 33 33 33 33 33 33 60: 08 10 12 12 12 12 00 00 00 00 00 00 00 00 00 00 70: 08 f1 ff ff 00 00 00 00 10 00 00 00 70 02 00 20 80: 00 00 00 00 00 00 00 00 80 60 33 09 00 00 00 00 90: 02 38 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 02 00 20 00 17 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 54 0e 41 a2 99 01 00 c0 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 1b 49 9b fc f0: 11 11 01 00 00 00 0b 05 35 d0 2c cf 22 cd 1d cc Copying coreboot to RAM. Jumping to coreboot.
<----LOCKS UP HERE---->
On Tue, May 27, 2008 at 10:27 PM, Joseph Smith joe@settoplinux.org wrote:
Hello, Now that I got coreboot running on the IP1000, I finally am able to test out the so-dimm socket. I maxed out the slot with a big 512MB so-dimm. I don't think the "for" statement we came up with is working correctly:
/* NOTE: Dual-sided ready. */ read32(0 + addr_offset); for (i = 0; i < 4; i++) { reg8 = pci_read_config8(ctrl->d0, DRB + i); if (reg8 != reg8_2) read32(reg8 * 32 * 1024 * 1024); reg8_2 = reg8; }The memory is detecting correctly, but I don't think coreboot can find the end of the side of the so-dimm, thus causing a lockup after Jumping to coreboot. I think I need to setup something more like the E7501 do_ram_command() but I want to keep it simple. Here is the bootlog, Help??
You're right, change
read32(reg8 * 32 * 1024 * 1024);
to
read32((reg8 * 32 * 1024 * 1024) + addr_offset);
also, make sure reg8_2 is 0'd before entering the for loop.
-Corey
Actually, lets get some more debugging info, in case that doesn't work. One quick question though:
60: 08 10 12 12 12 12 00 00 00 00 00 00 00 00 00 00
Are 0x64 and 0x65 also DRBs? Or they just happen to also be 0x12? Either way, this should work, but it will only work for up to 2 sticks. I've gotten rid of the dual sided junk, I'm about 98% sure it's not necessary, so it now just reads the start of the dimm (instead of row) and reads from that. Please try a memtest payload, if this boots, just to make sure it's working right.
read32(0 + addr_offset); /* See if there are 2 sticks */ reg8 = pci_read_config8(ctrl->d0, DRB + 1); reg8_2 = pci_read_config8(ctrl->d0, DRB + 2); if(reg8 != reg8_2) { PRINT_DEBUG("Sending command to DIMM1 at 0x"); PRINT_DEBUG_HEX32((reg8 * 32 * 1024 * 1024) + addr_offset); PRINT_DEBUG("/r/n); read32((reg8 * 32 * 1024 * 1024) + addr_offset); }
-Corey
On Tue, May 27, 2008 at 11:40 PM, Corey Osgood corey.osgood@gmail.com wrote:
On Tue, May 27, 2008 at 10:27 PM, Joseph Smith joe@settoplinux.org wrote:
Hello, Now that I got coreboot running on the IP1000, I finally am able to test out the so-dimm socket. I maxed out the slot with a big 512MB so-dimm. I don't think the "for" statement we came up with is working correctly:
/* NOTE: Dual-sided ready. */ read32(0 + addr_offset); for (i = 0; i < 4; i++) { reg8 = pci_read_config8(ctrl->d0, DRB + i); if (reg8 != reg8_2) read32(reg8 * 32 * 1024 * 1024); reg8_2 = reg8; }The memory is detecting correctly, but I don't think coreboot can find the end of the side of the so-dimm, thus causing a lockup after Jumping to coreboot. I think I need to setup something more like the E7501 do_ram_command() but I want to keep it simple. Here is the bootlog, Help??
You're right, change
read32(reg8 * 32 * 1024 * 1024);
to
read32((reg8 * 32 * 1024 * 1024) + addr_offset);
also, make sure reg8_2 is 0'd before entering the for loop.
-Corey
On Wed, 28 May 2008 00:04:14 -0400, "Corey Osgood" corey.osgood@gmail.com wrote:
Actually, lets get some more debugging info, in case that doesn't work.
One
quick question though:
60: 08 10 12 12 12 12 00 00 00 00 00 00 00 00 00 00
Are 0x64 and 0x65 also DRBs? Or they just happen to also be 0x12?
Ah, good catch. The datasheet says there is only 4 registers, and the i82830 only supports 2 dimms, but every northbridge dump (original bios's) I have done those two extra un-documented DRB registers are calculated. I think these were a design glitch, anyhow way back I discovered the system would not boot unless these were set. So in raminit I have this:
/* We need to set the highest DRB value to 0x64 and 0x65. * These are supposed to be "Reserved" but memory will * not initialize properly if we don't. */ value = pci_read_config8(ctrl->d0, DRB + 3); pci_write_config8(ctrl->d0, DRB + 4, value); pci_write_config8(ctrl->d0, DRB + 5, value);
Either way, this should work, but it will only work for up to 2 sticks.
I've gotten rid of the dual sided junk, I'm about 98% sure
it's not necessary, so it now just reads the start of the dimm (instead
of row) and reads from that. Please try a memtest payload, if this > boots, just to make sure it's working right.
I will try it out, and report back. Thanks for your help :-)
Is the mailing list working? If so why is everyone so quiet?
Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org
Well I changed it around a bit, here is what I came up with:
static void do_ram_command(const struct mem_controller *ctrl, uint32_t command, uint32_t addr_offset) { int i; uint8_t drb1, drb3; uint32_t reg32;
/* Configure the RAM command. */ reg32 = pci_read_config32(ctrl->d0, DRC); /* Clear bits 29, 10-8, 6-4. */ reg32 &= 0xdffff88f; reg32 |= command << 4;
drb1 = pci_read_config8(ctrl->d0, DRB + 1); drb3 = pci_read_config8(ctrl->d0, DRB + 3);
/* See if there are 2 sticks. */ if((drb1 != 0) && (drb3 != 0)) { /* If RAM_COMMAND_NORMAL set the refresh mode. */ if (command == RAM_COMMAND_NORMAL) reg32 |= (RAM_COMMAND_REFRESH << 8); pci_write_config32(ctrl->d0, DRC, reg32);
/* Send ram commands to DIMM0. */ read32(0 + addr_offset); PRINT_DEBUG(" Sending RAM command DIMM0 0x"); PRINT_DEBUG_HEX32(reg32); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32(0 + addr_offset); PRINT_DEBUG("\r\n");
/* If RAM_COMMAND_NORMAL set the IC bit. */ if (command == RAM_COMMAND_NORMAL) reg32 |= (RAM_COMMAND_IC << 29); pci_write_config32(ctrl->d0, DRC, reg32); /* Send ram commands to DIMM1. */ read32((drb1 * 32 * 1024 * 1024) + addr_offset); PRINT_DEBUG(" Sending RAM command DIMM1 0x"); PRINT_DEBUG_HEX32(reg32); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32((drb1 * 32 * 1024 * 1024) + addr_offset); PRINT_DEBUG("\r\n"); } else { /* If RAM_COMMAND_NORMAL set the refresh mode and IC bit. */ if (command == RAM_COMMAND_NORMAL) reg32 |= ((RAM_COMMAND_REFRESH << 8) | (RAM_COMMAND_IC << 29)); pci_write_config32(ctrl->d0, DRC, reg32);
read32(0 + addr_offset); PRINT_DEBUG(" Sending RAM command to DIMM at 0x"); PRINT_DEBUG_HEX32(reg32); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32(0 + addr_offset); PRINT_DEBUG("\r\n"); }
}
The process seems to do what it is supposed to but it is still craping out. HELP?? Here is the bootlog:
coreboot-2.0.0_IP1000 Thu May 29 00:58:25 EDT 2008 starting... Setting initial registers.... Initial registers have been set. Found DIMM in slot 00 DIMM is 0x0100 on side 1 DIMM is 0x0100 on side 2 DRB 0x60 has been set to 0x08 DRB1 0x61 has been set to 0x10 Found DIMM in slot 01 DIMM is 0x0040 on side 1 DIMM is 0x0000 on side 2 DRB2 0x62 has been set to 0x12 DRB3 0x63 has been set to 0x12 Found DIMM in slot 00, setting DRA... DRA 0x70 has been set to 0x08 Found DIMM in slot 01, setting DRA... DRA 0x71 has been set to 0xf1 RAM Enable 1: Apply NOP Sending RAM command DIMM0 0x00000010 to 0x00000000 Sending RAM command DIMM1 0x00000010 to 0x20000000 RAM Enable 2: Precharge all Sending RAM command DIMM0 0x00000020 to 0x00000000 Sending RAM command DIMM1 0x00000020 to 0x20000000 RAM Enable 3: CBR Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 RAM Enable 4: Mode register set Sending RAM command DIMM0 0x00000030 to 0x000001d0 Sending RAM command DIMM1 0x00000030 to 0x200001d0 RAM Enable 5: Normal operation Sending RAM command DIMM0 0x00000270 to 0x00000000 Sending RAM command DIMM1 0x20000270 to 0x20000000 Northbridge following SDRAM init: PCI: 00:00.00 00: 86 80 75 35 06 00 10 00 04 00 00 06 00 00 00 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 01 00 00 00 00 00 00 00 00 02 28 00 0e 50: 72 a0 40 00 00 00 00 00 00 30 33 33 33 33 33 33 60: 08 10 12 12 12 12 00 00 00 00 00 00 00 00 00 00 70: 08 f1 ff ff 00 00 00 00 10 00 00 00 70 02 00 20 80: 00 00 00 00 00 00 00 00 80 60 33 0b 00 00 00 00 90: 02 38 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 02 00 20 00 17 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 54 0e 41 a2 99 01 00 c0 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 1b 49 9b fc f0: 11 11 01 00 00 00 0b 05 35 d0 2c cf 1f cd 1d cc Copying coreboot to RAM. Jumping to coreboot.
####LOCKS UP HERE####
What am I doing wrong?
I'm not sure about the problem, try a ram_check just to confirm it's bum ram, and see if you can pinpoint where it's bad.
/* See if there are 2 sticks. */ if((drb1 != 0) && (drb3 != 0)) {
Should be:
if((drb1 != 0) && (drb3 != drb1))
-Corey
On Thu, May 29, 2008 at 1:29 AM, Joseph Smith joe@settoplinux.org wrote:
Well I changed it around a bit, here is what I came up with:
static void do_ram_command(const struct mem_controller *ctrl, uint32_t command, uint32_t addr_offset) { int i; uint8_t drb1, drb3; uint32_t reg32;
/* Configure the RAM command. */ reg32 = pci_read_config32(ctrl->d0, DRC); /* Clear bits 29, 10-8, 6-4. */ reg32 &= 0xdffff88f; reg32 |= command << 4; drb1 = pci_read_config8(ctrl->d0, DRB + 1); drb3 = pci_read_config8(ctrl->d0, DRB + 3); /* See if there are 2 sticks. */ if((drb1 != 0) && (drb3 != 0)) { /* If RAM_COMMAND_NORMAL set the refresh mode. */ if (command == RAM_COMMAND_NORMAL) reg32 |= (RAM_COMMAND_REFRESH << 8); pci_write_config32(ctrl->d0, DRC, reg32); /* Send ram commands to DIMM0. */ read32(0 + addr_offset); PRINT_DEBUG(" Sending RAM command DIMM0 0x"); PRINT_DEBUG_HEX32(reg32); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32(0 + addr_offset); PRINT_DEBUG("\r\n"); /* If RAM_COMMAND_NORMAL set the IC bit. */ if (command == RAM_COMMAND_NORMAL) reg32 |= (RAM_COMMAND_IC << 29); pci_write_config32(ctrl->d0, DRC, reg32); /* Send ram commands to DIMM1. */ read32((drb1 * 32 * 1024 * 1024) + addr_offset); PRINT_DEBUG(" Sending RAM command DIMM1 0x"); PRINT_DEBUG_HEX32(reg32); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32((drb1 * 32 * 1024 * 1024) + addr_offset); PRINT_DEBUG("\r\n"); } else { /* If RAM_COMMAND_NORMAL set the refresh mode and IC bit. */ if (command == RAM_COMMAND_NORMAL) reg32 |= ((RAM_COMMAND_REFRESH << 8) | (RAM_COMMAND_IC << 29)); pci_write_config32(ctrl->d0, DRC, reg32); read32(0 + addr_offset); PRINT_DEBUG(" Sending RAM command to DIMM at 0x"); PRINT_DEBUG_HEX32(reg32); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32(0 + addr_offset); PRINT_DEBUG("\r\n"); }}
The process seems to do what it is supposed to but it is still craping out. HELP?? Here is the bootlog:
coreboot-2.0.0_IP1000 Thu May 29 00:58:25 EDT 2008 starting... Setting initial registers.... Initial registers have been set. Found DIMM in slot 00 DIMM is 0x0100 on side 1 DIMM is 0x0100 on side 2 DRB 0x60 has been set to 0x08 DRB1 0x61 has been set to 0x10 Found DIMM in slot 01 DIMM is 0x0040 on side 1 DIMM is 0x0000 on side 2 DRB2 0x62 has been set to 0x12 DRB3 0x63 has been set to 0x12 Found DIMM in slot 00, setting DRA... DRA 0x70 has been set to 0x08 Found DIMM in slot 01, setting DRA... DRA 0x71 has been set to 0xf1 RAM Enable 1: Apply NOP Sending RAM command DIMM0 0x00000010 to 0x00000000 Sending RAM command DIMM1 0x00000010 to 0x20000000 RAM Enable 2: Precharge all Sending RAM command DIMM0 0x00000020 to 0x00000000 Sending RAM command DIMM1 0x00000020 to 0x20000000 RAM Enable 3: CBR Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 RAM Enable 4: Mode register set Sending RAM command DIMM0 0x00000030 to 0x000001d0 Sending RAM command DIMM1 0x00000030 to 0x200001d0 RAM Enable 5: Normal operation Sending RAM command DIMM0 0x00000270 to 0x00000000 Sending RAM command DIMM1 0x20000270 to 0x20000000 Northbridge following SDRAM init: PCI: 00:00.00 00: 86 80 75 35 06 00 10 00 04 00 00 06 00 00 00 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 01 00 00 00 00 00 00 00 00 02 28 00 0e 50: 72 a0 40 00 00 00 00 00 00 30 33 33 33 33 33 33 60: 08 10 12 12 12 12 00 00 00 00 00 00 00 00 00 00 70: 08 f1 ff ff 00 00 00 00 10 00 00 00 70 02 00 20 80: 00 00 00 00 00 00 00 00 80 60 33 0b 00 00 00 00 90: 02 38 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 02 00 20 00 17 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 54 0e 41 a2 99 01 00 c0 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 1b 49 9b fc f0: 11 11 01 00 00 00 0b 05 35 d0 2c cf 1f cd 1d cc Copying coreboot to RAM. Jumping to coreboot.
####LOCKS UP HERE####
What am I doing wrong?
Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org
Oh yeah, did you try leaving the dual sided stuff in there, and just changing that one line (per my original fix)? Might be I was wrong (it does happen, all too often).
-Corey
On Thu, May 29, 2008 at 1:46 AM, Corey Osgood corey.osgood@gmail.com wrote:
I'm not sure about the problem, try a ram_check just to confirm it's bum ram, and see if you can pinpoint where it's bad.
/* See if there are 2 sticks. */ if((drb1 != 0) && (drb3 != 0)) {Should be:
if((drb1 != 0) && (drb3 != drb1))
-Corey
On Thu, May 29, 2008 at 1:29 AM, Joseph Smith joe@settoplinux.org wrote:
Well I changed it around a bit, here is what I came up with:
static void do_ram_command(const struct mem_controller *ctrl, uint32_t command, uint32_t addr_offset) { int i; uint8_t drb1, drb3; uint32_t reg32;
/* Configure the RAM command. */ reg32 = pci_read_config32(ctrl->d0, DRC); /* Clear bits 29, 10-8, 6-4. */ reg32 &= 0xdffff88f; reg32 |= command << 4; drb1 = pci_read_config8(ctrl->d0, DRB + 1); drb3 = pci_read_config8(ctrl->d0, DRB + 3); /* See if there are 2 sticks. */ if((drb1 != 0) && (drb3 != 0)) { /* If RAM_COMMAND_NORMAL set the refresh mode. */ if (command == RAM_COMMAND_NORMAL) reg32 |= (RAM_COMMAND_REFRESH << 8); pci_write_config32(ctrl->d0, DRC, reg32); /* Send ram commands to DIMM0. */ read32(0 + addr_offset); PRINT_DEBUG(" Sending RAM command DIMM0 0x"); PRINT_DEBUG_HEX32(reg32); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32(0 + addr_offset); PRINT_DEBUG("\r\n"); /* If RAM_COMMAND_NORMAL set the IC bit. */ if (command == RAM_COMMAND_NORMAL) reg32 |= (RAM_COMMAND_IC << 29); pci_write_config32(ctrl->d0, DRC, reg32); /* Send ram commands to DIMM1. */ read32((drb1 * 32 * 1024 * 1024) + addr_offset); PRINT_DEBUG(" Sending RAM command DIMM1 0x"); PRINT_DEBUG_HEX32(reg32); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32((drb1 * 32 * 1024 * 1024) + addr_offset); PRINT_DEBUG("\r\n"); } else { /* If RAM_COMMAND_NORMAL set the refresh mode and IC bit. */ if (command == RAM_COMMAND_NORMAL) reg32 |= ((RAM_COMMAND_REFRESH << 8) | (RAM_COMMAND_IC << 29)); pci_write_config32(ctrl->d0, DRC, reg32); read32(0 + addr_offset); PRINT_DEBUG(" Sending RAM command to DIMM at 0x"); PRINT_DEBUG_HEX32(reg32); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32(0 + addr_offset); PRINT_DEBUG("\r\n"); }}
The process seems to do what it is supposed to but it is still craping out. HELP?? Here is the bootlog:
coreboot-2.0.0_IP1000 Thu May 29 00:58:25 EDT 2008 starting... Setting initial registers.... Initial registers have been set. Found DIMM in slot 00 DIMM is 0x0100 on side 1 DIMM is 0x0100 on side 2 DRB 0x60 has been set to 0x08 DRB1 0x61 has been set to 0x10 Found DIMM in slot 01 DIMM is 0x0040 on side 1 DIMM is 0x0000 on side 2 DRB2 0x62 has been set to 0x12 DRB3 0x63 has been set to 0x12 Found DIMM in slot 00, setting DRA... DRA 0x70 has been set to 0x08 Found DIMM in slot 01, setting DRA... DRA 0x71 has been set to 0xf1 RAM Enable 1: Apply NOP Sending RAM command DIMM0 0x00000010 to 0x00000000 Sending RAM command DIMM1 0x00000010 to 0x20000000 RAM Enable 2: Precharge all Sending RAM command DIMM0 0x00000020 to 0x00000000 Sending RAM command DIMM1 0x00000020 to 0x20000000 RAM Enable 3: CBR Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 Sending RAM command DIMM0 0x00000060 to 0x00000000 Sending RAM command DIMM1 0x00000060 to 0x20000000 RAM Enable 4: Mode register set Sending RAM command DIMM0 0x00000030 to 0x000001d0 Sending RAM command DIMM1 0x00000030 to 0x200001d0 RAM Enable 5: Normal operation Sending RAM command DIMM0 0x00000270 to 0x00000000 Sending RAM command DIMM1 0x20000270 to 0x20000000 Northbridge following SDRAM init: PCI: 00:00.00 00: 86 80 75 35 06 00 10 00 04 00 00 06 00 00 00 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 01 00 00 00 00 00 00 00 00 02 28 00 0e 50: 72 a0 40 00 00 00 00 00 00 30 33 33 33 33 33 33 60: 08 10 12 12 12 12 00 00 00 00 00 00 00 00 00 00 70: 08 f1 ff ff 00 00 00 00 10 00 00 00 70 02 00 20 80: 00 00 00 00 00 00 00 00 80 60 33 0b 00 00 00 00 90: 02 38 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 02 00 20 00 17 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 54 0e 41 a2 99 01 00 c0 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 1b 49 9b fc f0: 11 11 01 00 00 00 0b 05 35 d0 2c cf 1f cd 1d cc Copying coreboot to RAM. Jumping to coreboot.
####LOCKS UP HERE####
What am I doing wrong?
Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org
On Thu, 29 May 2008 01:50:16 -0400, "Corey Osgood" corey.osgood@gmail.com wrote:
Oh yeah, did you try leaving the dual sided stuff in there, and just changing that one line (per my original fix)? Might be I was wrong (it does happen, all too often).
I will give that a shot, thanks again Corey.
-- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org
-- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Ok, I adapted the E7501 code, I think this will work great. I will test tonight, and get back.
dimm_start = 0;
for (i = 0; i < DIMM_SOCKETS; ++i) { if (i == 0) { dimm_end = pci_read_config8(ctrl->d0, DRB + 1); } else if (i == 1) { dimm_end = pci_read_config8(ctrl->d0, DRB + 3); }
if (dimm_end > dimm_start) {
/* Convert to a 32 bit address. NOTE: 2^25 == 32 MB */ dimm_start_address = dimm_start << 25;
RAM_DEBUG_MESSAGE(" Sending RAM command to 0x"); RAM_DEBUG_HEX32(dimm_start_address + addr_offset); RAM_DEBUG_MESSAGE("\r\n"); read32(dimm_start_address + addr_offset);
/* Set the start of the next DIMM. */ dimm_start = dimm_end; } }
On Thu, 29 May 2008 10:35:09 -0400, Joseph Smith joe@settoplinux.org wrote:
Ok, I adapted the E7501 code, I think this will work great. I will test tonight, and get back.
dimm_start = 0;
for (i = 0; i < DIMM_SOCKETS; ++i) { if (i == 0) { dimm_end = pci_read_config8(ctrl->d0, DRB + 1); } else if (i == 1) { dimm_end = pci_read_config8(ctrl->d0, DRB + 3); }
if (dimm_end > dimm_start) { /* Convert to a 32 bit address. NOTE: 2^25 == 32 MB */ dimm_start_address = dimm_start << 25; PRINT_DEBUG(" Sending RAM command to 0x"); PRINT_DEBUG_HEX32(dimm_start_address + addr_offset); PRINT_DEBUG("\r\n"); read32(dimm_start_address + addr_offset); /* Set the start of the next DIMM. */ dimm_start = dimm_end; }}
Nope it doesn't even make it to this part???? It craps out right after "coreboot-2.0.0_IP1000 Thu May 29 00:58:25 EDT 2008 starting..." and just locks up???? This is making me crazy!! This little box would scream, if I could this 512MB so-dimm to work, HELP!!!
/* See if there are 2 sticks. */ if((drb1 != 0) && (drb3 != 0)) {Should be:
if((drb1 != 0) && (drb3 != drb1))
In theory this would not work. If you have a so-dimm in slot0 drb3 would == drb1. The register would look something like this:
04 04 04 04
for a 128MB single sidded so-dimm in the first slot.
On Mon, 02 Jun 2008 23:41:11 -0400, Joseph Smith joe@settoplinux.org wrote:
/* See if there are 2 sticks. */ if((drb1 != 0) && (drb3 != 0)) {Should be:
if((drb1 != 0) && (drb3 != drb1))
In theory this would not work. If you have a so-dimm in slot0 drb3 would
drb1. The register would look something like this:
04 04 04 04
for a 128MB single sidded so-dimm in the first slot.
Actually, this should work:
if((drb1 != 0) && (drb3 > drb1)) {
This way if drb1 is not zero, you know you have a so-dimm in slot0. And if drb3 is greater than drb1, you know you have a so-dimm in slot1.
Well, I got everything working now :-) But I am still getting a crazy kernel crash :-(
Checking 'hlt' instruction... OK. SMP alternatives: switching to UP code Freeing SMP alternatives: 14k freed BUG: unable to handle kernel paging request at virtual address 7c142450 printing eip: c047d698 *pde = 00000000 Oops: 0000 [#1] SMP Modules linked in: CPU: 0 EIP: 0060:[<c047d698>] Not tainted VLI EFLAGS: 00010006 (2.6.23.15-80.fc7 #1) EIP is at kmem_cache_alloc+0x36/0x99 eax: 00000000 ebx: 00000000 ecx: c043af87 edx: 7c142444 esi: dfd36000 edi: 00000286 ebp: 000000d0 esp: c0738ef0 ds: 007b es: 007b fs: 00d8 gs: 0000 ss: 0068 Process swapper (pid: 0, ti=c0738000 task=c06f5340 task.ti=c0738000) Stack: c042dea8 00000000 00000000 00800b00 00800b00 c0738f80 c043af87 00000206 00000046 c042dea8 00000000 00000046 c0738fc8 00000000 00800b00 00800b00 c0738f80 c042c969 00000000 00000046 00cf9000 fffb6c73 00000000 c100e798 Call Trace: [<c042dea8>] vprintk+0x2a5/0x2e0 [<c043af87>] alloc_pid+0x16/0x243 [<c042dea8>] vprintk+0x2a5/0x2e0 [<c042c969>] do_fork+0x12/0x17e [<c073d3e0>] kernel_init+0x0/0x360 [<c0403358>] kernel_thread+0x8e/0x96 [<c073d3e0>] kernel_init+0x0/0x360 [<c0405db4>] kernel_thread_helper+0x0/0x10 [<c061b775>] rest_init+0x11/0x4a [<c073da6c>] start_kernel+0x32c/0x334 [<c073d177>] unknown_bootoption+0x0/0x195 ======================= Code: 8b 4c 24 18 9c 58 90 8d b4 26 00 00 00 00 89 c7 fa 90 8d b4 26 00 00 00 00 90 64 a1 08 c0 77 c0 8b 94 86 90 00 00 00 85 d2 74 06 <83> 7a 0c 00 75 17 89 54 24 04 89 f0 89 ea 89 0c 24 83 c9 ff e8 EIP: [<c047d698>] kmem_cache_alloc+0x36/0x99 SS:ESP 0068:c0738ef0 Kernel panic - not syncing: Attempted to kill the idle task!
Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org
Good News!!! I think I got it working :-) I am running memtest86 right now and if all goes well I build it again with filo and test it.
First I tried with initializing each dimm socket. I booted to memtest and it kept erroring out at 256mb. Because this is a double sidded 512MB so-dimm, I figured out that each side of each dimm needs to be initialized. So I came up with this:
for (i = 0; i < MAX_DIMM_SIDES; i++) { dimm_end = pci_read_config8(ctrl->d0, DRB + i); if (dimm_end > dimm_start) { PRINT_DEBUG(" Sending RAM command 0x"); PRINT_DEBUG_HEX32(reg32); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32((dimm_start * 32 * 1024 * 1024) + addr_offset); PRINT_DEBUG("\r\n"); read32((dimm_start * 32 * 1024 * 1024) + addr_offset); } /* Set the start of the next DIMM. */ dimm_start = dimm_end; }
It seems to work good so far, hopefully I will be submitting a patch soon. Output from bootlog:
coreboot-2.0.0_IP1000 Tue Jun 3 21:56:32 EDT 2008 starting... Setting initial registers.... Initial registers have been set. Found DIMM in slot 00 DIMM is 0x0100 on side 1 DIMM is 0x0100 on side 2 DRB 0x60 has been set to 0x08 DRB1 0x61 has been set to 0x10 Found DIMM in slot 01 DIMM is 0x0040 on side 1 DIMM is 0x0000 on side 2 DRB2 0x62 has been set to 0x12 DRB3 0x63 has been set to 0x12 Found DIMM in slot 00, setting DRA... DRA 0x70 has been set to 0x22 Found DIMM in slot 01, setting DRA... DRA 0x71 has been set to 0xf1 RAM Enable 1: Apply NOP Sending RAM command 0x00000010 to 0x00000000 Sending RAM command 0x00000010 to 0x10000000 Sending RAM command 0x00000010 to 0x20000000 RAM Enable 2: Precharge all Sending RAM command 0x00000020 to 0x00000000 Sending RAM command 0x00000020 to 0x10000000 Sending RAM command 0x00000020 to 0x20000000 RAM Enable 3: CBR Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x10000000 Sending RAM command 0x00000060 to 0x20000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x10000000 Sending RAM command 0x00000060 to 0x20000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x10000000 Sending RAM command 0x00000060 to 0x20000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x10000000 Sending RAM command 0x00000060 to 0x20000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x10000000 Sending RAM command 0x00000060 to 0x20000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x10000000 Sending RAM command 0x00000060 to 0x20000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x10000000 Sending RAM command 0x00000060 to 0x20000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x10000000 Sending RAM command 0x00000060 to 0x20000000 RAM Enable 4: Mode register set Sending RAM command 0x00000030 to 0x000001d0 Sending RAM command 0x00000030 to 0x100001d0 Sending RAM command 0x00000030 to 0x200001d0 RAM Enable 5: Normal operation Sending RAM command 0x00000070 to 0x00000000 Sending RAM command 0x00000070 to 0x10000000 Sending RAM command 0x00000070 to 0x20000000 RAM Enable 6: Enable Refresh and IC
On 04.06.2008 04:59, Joseph Smith wrote:
Good News!!! I think I got it working :-)
Great!
I am running memtest86 right now and if all goes well I build it again with filo and test it.
First I tried with initializing each dimm socket. I booted to memtest and it kept erroring out at 256mb. Because this is a double sidded 512MB so-dimm, I figured out that each side of each dimm needs to be initialized. So I came up with this:
for (i = 0; i < MAX_DIMM_SIDES; i++) { dimm_end = pci_read_config8(ctrl->d0, DRB + i); if (dimm_end > dimm_start) { PRINT_DEBUG(" Sending RAM command 0x"); PRINT_DEBUG_HEX32(reg32); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32((dimm_start * 32 * 1024 * 1024) + addr_offset); PRINT_DEBUG("\r\n"); read32((dimm_start * 32 * 1024 * 1024) + addr_offset); } /* Set the start of the next DIMM. */ dimm_start = dimm_end; }
It seems to work good so far, hopefully I will be submitting a patch soon.
Please submit a patch now, regardless of how ugly/polluted/unclean it is. We had too many losses of great patches in the past because computers died and an early not-ready patch is better than nothing.
Regards, Carl-Daniel
On Wed, 04 Jun 2008 14:14:49 +0200, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
On 04.06.2008 04:59, Joseph Smith wrote:
Good News!!! I think I got it working :-)
Great!
I am running memtest86 right now and if all goes well I build it again
with
filo and test it.
First I tried with initializing each dimm socket. I booted to memtest
and
it kept erroring out at 256mb. Because this is a double sidded 512MB so-dimm, I figured out that each side of each dimm needs to be
initialized.
So I came up with this:
for (i = 0; i < MAX_DIMM_SIDES; i++) { dimm_end = pci_read_config8(ctrl->d0, DRB + i); if (dimm_end > dimm_start) { PRINT_DEBUG(" Sending RAM command 0x"); PRINT_DEBUG_HEX32(reg32); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32((dimm_start * 32 * 1024 * 1024) + addr_offset); PRINT_DEBUG("\r\n"); read32((dimm_start * 32 * 1024 * 1024) + addr_offset); } /* Set the start of the next DIMM. */ dimm_start = dimm_end; }
It seems to work good so far, hopefully I will be submitting a patch
soon.
Please submit a patch now, regardless of how ugly/polluted/unclean it is. We had too many losses of great patches in the past because computers died and an early not-ready patch is better than nothing.
Oh, don't worry all be submitting a patch. I just want to make sure I have my bases covered first. I hope You don't think the code above is in any way "ugly/polluted/unclean". I think it is a very clean, fast, and great way to acomplish memory initialization.
On 05.06.2008 17:44, Joseph Smith wrote:
On Wed, 04 Jun 2008 14:14:49 +0200, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
Please submit a patch now, regardless of how ugly/polluted/unclean it is. We had too many losses of great patches in the past because computers died and an early not-ready patch is better than nothing.
Oh, don't worry all be submitting a patch. I just want to make sure I have my bases covered first. I hope You don't think the code above is in any way "ugly/polluted/unclean". I think it is a very clean, fast, and great way to acomplish memory initialization.
Sure, the code looks nice. I wanted to say something along the lines of "if you have any leftover unrelated changes in the tree, don't worry about them and submit the state of your tree anyway". I wish to apologize if my statement caused any irritation. As a non-native speaker I occassionally miss subtle meanings in a sentence.
Regards, Carl-Daniel
On Thu, 05 Jun 2008 21:00:01 +0200, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
On 05.06.2008 17:44, Joseph Smith wrote:
On Wed, 04 Jun 2008 14:14:49 +0200, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
Please submit a patch now, regardless of how ugly/polluted/unclean it is. We had too many losses of great patches in the past because computers died and an early not-ready patch is better than nothing.
Oh, don't worry all be submitting a patch. I just want to make sure I
have
my bases covered first. I hope You don't think the code above is in any way "ugly/polluted/unclean". I think it is a very clean, fast, and great way
to
acomplish memory initialization.
Sure, the code looks nice. I wanted to say something along the lines of "if you have any leftover unrelated changes in the tree, don't worry about them and submit the state of your tree anyway". I wish to apologize if my statement caused any irritation. As a non-native speaker I occassionally miss subtle meanings in a sentence.
No worries, Carl-Daniel. I know what you meant. I just want to be sure this is going to work first. I have been very busy with other life things the past few days, that is why I have not submitted it yet. This should be a great advance though, it will allow mutiple dimm (dual and single sided) support for many of the intel northbridges, including the i810, and possibly the 440bx(which it is not currently working for).
-
Carl-Daniel Hailfinger -
Corey Osgood -
Joseph Smith