Hi List,
this patch series is a generic cleanup of the pci1x2x driver. Basically it does:
- move register config from Kconfig to devicetree.cb - use the generic pci/cardbus functions - add proper subsystemid configuration - remove latency. cacheline size, bridge control register settings, as such register should be configured by the pci/cardbus code.
Sven.
Signed-off-by: Sven Schnelle svens@stackframe.org --- src/mainboard/nokia/ip530/Kconfig | 25 --------------------- src/mainboard/nokia/ip530/devicetree.cb | 9 +++++++ src/southbridge/ti/pci1x2x/pci1x2x.c | 36 +++++++++++++----------------- 3 files changed, 25 insertions(+), 45 deletions(-)
diff --git a/src/mainboard/nokia/ip530/Kconfig b/src/mainboard/nokia/ip530/Kconfig index 0eac00a..b5abb89 100644 --- a/src/mainboard/nokia/ip530/Kconfig +++ b/src/mainboard/nokia/ip530/Kconfig @@ -45,29 +45,4 @@ config IRQ_SLOT_COUNT int default 22
-## Configuration for the PCMCIA-Cardbus controller. -config TI_PCMCIA_CARDBUS_CMDR - hex - default 0x0107 - -config TI_PCMCIA_CARDBUS_CLSR - hex - default 0x00 - -config TI_PCMCIA_CARDBUS_CLTR - hex - default 0x40 - -config TI_PCMCIA_CARDBUS_BCR - hex - default 0x07C0 - -config TI_PCMCIA_CARDBUS_SCR - hex - default 0x08449060 - -config TI_PCMCIA_CARDBUS_MRR - hex - default 0x00007522 - endif # BOARD_NOKIA_IP530 diff --git a/src/mainboard/nokia/ip530/devicetree.cb b/src/mainboard/nokia/ip530/devicetree.cb index 3cfbc8f..54ebb1a 100644 --- a/src/mainboard/nokia/ip530/devicetree.cb +++ b/src/mainboard/nokia/ip530/devicetree.cb @@ -28,6 +28,15 @@ chip northbridge/intel/i440bx # Northbridge device pci 0.0 on end # Host bridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge + device pci f.0 on + chip southbridge/ti/pci1x2x + device pci 00.0 on + + end + register "scr" = "0x08449060" + register "mrr" = "0x00007522" + end + end device pci 7.0 on # ISA bridge chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37B787) device pnp 3f0.0 off end # Floppy (No connector) diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index 63a0646..121b9ef 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -23,28 +23,20 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <console/console.h> - -#if (!defined(CONFIG_TI_PCMCIA_CARDBUS_CMDR) || \ - !defined(CONFIG_TI_PCMCIA_CARDBUS_CLSR) || \ - !defined(CONFIG_TI_PCMCIA_CARDBUS_CLTR) || \ - !defined(CONFIG_TI_PCMCIA_CARDBUS_BCR) || \ - !defined(CONFIG_TI_PCMCIA_CARDBUS_SCR) || \ - !defined(CONFIG_TI_PCMCIA_CARDBUS_MRR)) -#error "you must supply these values in your mainboard-specific Kconfig file" -#endif +#include "chip.h"
static void ti_pci1x2y_init(struct device *dev) { + printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n"); + struct southbridge_ti_pci1x2x_config *conf = dev->chip_info;
- /* Command (offset 04) */ - pci_write_config16(dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR); /* Cache Line Size (offset 0x0C) */ - pci_write_config8(dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR); + pci_write_config8(dev, 0x0C, conf->clsr); /* CardBus latency timer (offset 0x1B) */ - pci_write_config8(dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR); + pci_write_config8(dev, 0x1B, conf->cltr); /* Bridge control (offset 0x3E) */ - pci_write_config16(dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR); + pci_write_config16(dev, 0x3E, conf->bcr); /* * Enable change sub-vendor ID. Clear the bit 5 to enable to write * to the sub-vendor/device ids at 40 and 42. @@ -53,14 +45,14 @@ static void ti_pci1x2y_init(struct device *dev) pci_write_config32(dev, 0x40, PCI_VENDOR_ID_NOKIA); /* Now write the correct value for SCR. */ /* System control (offset 0x80) */ - pci_write_config32(dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR); + pci_write_config32(dev, 0x80, conf->scr); /* Multifunction routing */ - pci_write_config32(dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR); + pci_write_config32(dev, 0x8C, conf->mrr); /* Set the device control register (0x92) accordingly. */ pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02); }
-static struct device_operations ti_pci1x2y_ops = { +struct device_operations southbridge_ti_pci1x2x_pciops = { .read_resources = NULL, //pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, @@ -69,19 +61,23 @@ static struct device_operations ti_pci1x2y_ops = { };
static const struct pci_driver ti_pci1225_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, + .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1225, };
static const struct pci_driver ti_pci1420_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, + .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1420, };
static const struct pci_driver ti_pci1520_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, + .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1520, }; + +struct chip_operations southbridge_ti_pci1x2x_ops = { + CHIP_NAME("TI PCI1x2x Cardbus controller") +};
* Sven Schnelle svens@stackframe.org [110419 21:47]:
Signed-off-by: Sven Schnelle svens@stackframe.org
static void ti_pci1x2y_init(struct device *dev) {
- printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n");
- struct southbridge_ti_pci1x2x_config *conf = dev->chip_info;
You should check if dev or conf is actually set before accessing it. I believe if the device is not mentioned in devicetree.cb conf will be NULL.
See some i82801gx drivers for an example.
Other than that:
Acked-by: Stefan Reinauer stefan.reinauer@coreboot.org
Signed-off-by: Sven Schnelle svens@stackframe.org --- src/include/device/pci_ids.h | 1 + src/southbridge/ti/pci1x2x/pci1x2x.c | 6 ++++++ 2 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 6286cd6..03896c5 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -737,6 +737,7 @@ #define PCI_DEVICE_ID_TI_4451 0xac42 #define PCI_DEVICE_ID_TI_1420 0xac51 #define PCI_DEVICE_ID_TI_1520 0xac55 +#define PCI_DEVICE_ID_TI_1510 0xac56
#define PCI_VENDOR_ID_SONY 0x104d #define PCI_DEVICE_ID_SONY_CXD3222 0x8039 diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index 121b9ef..0628f1f 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -72,6 +72,12 @@ static const struct pci_driver ti_pci1420_driver __pci_driver = { .device = PCI_DEVICE_ID_TI_1420, };
+static const struct pci_driver ti_pci1510_driver __pci_driver = { + .ops = &southbridge_ti_pci1x2x_pciops, + .vendor = PCI_VENDOR_ID_TI, + .device = PCI_DEVICE_ID_TI_1510, +}; + static const struct pci_driver ti_pci1520_driver __pci_driver = { .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI,
* Sven Schnelle svens@stackframe.org [110419 21:47]:
Signed-off-by: Sven Schnelle svens@stackframe.org
Acked-by: Stefan Reinauer stefan.reinauer@coreboot.org
Signed-off-by: Sven Schnelle svens@stackframe.org --- src/southbridge/ti/pci1x2x/pci1x2x.c | 25 ++++++++++++++++++------- 1 files changed, 18 insertions(+), 7 deletions(-)
diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index 0628f1f..a3ec35c 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -23,6 +23,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <console/console.h> +#include <arch/io.h> #include "chip.h"
static void ti_pci1x2y_init(struct device *dev) @@ -37,13 +38,6 @@ static void ti_pci1x2y_init(struct device *dev) pci_write_config8(dev, 0x1B, conf->cltr); /* Bridge control (offset 0x3E) */ pci_write_config16(dev, 0x3E, conf->bcr); - /* - * Enable change sub-vendor ID. Clear the bit 5 to enable to write - * to the sub-vendor/device ids at 40 and 42. - */ - pci_write_config32(dev, 0x80, 0x10); - pci_write_config32(dev, 0x40, PCI_VENDOR_ID_NOKIA); - /* Now write the correct value for SCR. */ /* System control (offset 0x80) */ pci_write_config32(dev, 0x80, conf->scr); /* Multifunction routing */ @@ -52,12 +46,29 @@ static void ti_pci1x2y_init(struct device *dev) pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02); }
+static void ti_pci1x2y_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + /* + * Enable change sub-vendor ID. Clear the bit 5 to enable to write + * to the sub-vendor/device ids at 40 and 42. + */ + pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x080) & ~0x10); + pci_write_config16(dev, 0x40, vendor); + pci_write_config16(dev, 0x42, device); + pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x80) | 0x10); +} + +static struct pci_operations ti_pci1x2y_pci_ops = { + .set_subsystem = ti_pci1x2y_set_subsystem, +}; + struct device_operations southbridge_ti_pci1x2x_pciops = { .read_resources = NULL, //pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ti_pci1x2y_init, .scan_bus = 0, + .ops_pci = &ti_pci1x2y_pci_ops, };
static const struct pci_driver ti_pci1225_driver __pci_driver = {
* Sven Schnelle svens@stackframe.org [110419 21:47]:
Signed-off-by: Sven Schnelle svens@stackframe.org
Will that also need a change in the nokia IP530 board's devicetree.cb?
Acked-by: Stefan Reinauer stefan.reinauer@coreboot.org
Hi Stefan, Stefan Reinauer stefan.reinauer@coreboot.org writes:
- Sven Schnelle svens@stackframe.org [110419 21:47]:
Signed-off-by: Sven Schnelle svens@stackframe.org
Will that also need a change in the nokia IP530 board's devicetree.cb?
Of course. Added the neccessary subsystemid statement to devicetree.cb.
Sven.
Signed-off-by: Sven Schnelle svens@stackframe.org --- src/southbridge/ti/pci1x2x/pci1x2x.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index a3ec35c..bc4ee89 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -22,6 +22,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <device/cardbus.h> #include <console/console.h> #include <arch/io.h> #include "chip.h" @@ -63,9 +64,9 @@ static struct pci_operations ti_pci1x2y_pci_ops = { };
struct device_operations southbridge_ti_pci1x2x_pciops = { - .read_resources = NULL, //pci_dev_read_resources, + .read_resources = cardbus_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, + .enable_resources = cardbus_enable_resources, .init = ti_pci1x2y_init, .scan_bus = 0, .ops_pci = &ti_pci1x2y_pci_ops,
* Sven Schnelle svens@stackframe.org [110419 21:47]:
Signed-off-by: Sven Schnelle svens@stackframe.org
What's the difference?
Acked-by: Stefan Reinauer stefan.reinauer@coreboot.org
-
Stefan Reinauer -
Sven Schnelle