Author: mjones Date: Sun May 15 23:01:42 2011 New Revision: 6570 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6570
Log: 1) Initialize BSP fixed MTRRs to match AP fixed MTRR initialization. 2) Remove coreboot variable MTRR initialization because AMD reference code handles it.
Signed-off-by: Scott Duplichan scott@notabs.org Acked-by: Marc Jones marcj303@gmail.com
Modified: trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c
Modified: trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c ============================================================================== --- trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c Fri May 13 08:25:16 2011 (r6569) +++ trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c Sun May 15 23:01:42 2011 (r6570) @@ -62,6 +62,7 @@
u8 i; msr_t msr; + int msrno; struct node_core_id id; #if CONFIG_LOGICAL_CPUS == 1 u32 siblings; @@ -70,12 +71,24 @@ // id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */ // printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
- /* Turn on caching if we haven't already */ - x86_enable_cache(); - amd_setup_mtrrs(); - x86_mtrr_check(); - - disable_cache(); + disable_cache (); + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + + // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs + msr.lo = msr.hi = 0; + wrmsr (0x259, msr); + msr.lo = msr.hi = 0x1e1e1e1e; + for (msrno = 0x268; msrno <= 0x26f; msrno++) + wrmsr (msrno, msr); + + /* disable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + enable_cache ();
/* zero the machine check error status registers */ msr.lo = 0; @@ -84,8 +97,6 @@ wrmsr(MCI_STATUS + (i * 4), msr); }
- enable_cache(); - /* Enable the local cpu apics */ setup_lapic();