Alex Mauer did some looking into the changelog and came up with some possibilities for when the Epia vt8601 may have actually worked.
Since the epia is _long_ overdue for some maintaince I spent a bit of time pulling those versions and trying to make them compile for him.
Compililng old versions of V2 on a new toolchain is an exercise in frustration.
I'm going to have to pull my suggestion that someone pull versions until they find the one that broke it. Its a non-trivial exercise.
I had to resort to forward porting the raminit code from 1176 into the latest rev. But alas it did not work.
We need a confirmed working Linuxbios rom and a dump of the northbridge settings to verify against.
If anyone has machines around with older toolchains ( or machines you can install older toolchains on) we could really use some help trying to get an older rev to compile.
If anyone has a toolchain that will compile anthing from r1176 to r1258 then please compile a rom for the epia and send it to Alex Mauer for testing.
Please do a clean pull for each rev you try. That way we can rule out any wierdness that my happen from a rev to rev switch.
Thanks.
On Wed, Sep 06, 2006 at 11:31:42AM -0500, Richard Smith wrote:
If anyone has machines around with older toolchains ( or machines you can install older toolchains on) we could really use some help trying to get an older rev to compile.
Just an idea - you could use QEMU to install an older (virtual) Linux distro which has the required tools and build everything in QEMU, then copy the files to you host OS...
HTH, Uwe.
Just an idea - you could use QEMU to install an older (virtual) Linux distro which has the required tools and build everything in QEMU, then copy the files to you host OS...
My idea for Alex exactly but I thought I'd put out a larger call. I don't currently have the cycles available. I went a bit overbudget last night.
So all you folks asking about epia vt8601 support. Here's your chance.
there's one other nasty possibility here. If the chips have been changed in some way, then it could be not linuxbios, but the chip.
oh boy oh boy.
ron
I have been going over the vt8601 code, although only the stuff in raminit.c as I assume that is probably where the problem lies. I did pull off rev 1179 (not 100% sure) managed to build it ok, but when I booted it, it was coming up with smbus errors. Then tries version 1159, this wouldn't build, there were files missing.
Yea! A hacker who has the hardware.
I have found a slight problem, maybe stack related ( what does linuxbios do for a stack before ram is initialised ? )
Just like the matrix.. There is no stack. oh wait, that was spoon. sorry.
Seriously. Thats waht romcc does. It compiles code that runs only with CPU registers. No stack. No RAM of any kind.
At this point register 0x64 has 0xec in it, which it shouldn't. The extra bit(b3) is not used and should be 0. Now no where in the code is this set so whats happening ?
Thats actually a good sign. Perhaps you are finding some of the problems.
I put a print at the end of the sdram_set_registers() function and it is wrong there also. However putting in that extra print hangs the code. So I am thinking maybe its a stack issue.
print_* uses a lot of resources. You may be running out of registers or the romcc maybe corrupting the register that has the return address.
Try to be much simpler about things. Like hook up a serial terminal that can display hex values and just out() the value directly.
romcc does amazing things but its still pretty easy to trip it up.
Have been through the vt8601 datasheet quite a few times now, must be one of the worst I have seen, anyway does anyone have any idea what the "DRAM Controller Command Register Output" bit is used for ?
Ron said that the datasheet is also incorrect in some places. If you do it like the data sheet says then it doesn't work. Thats why we need to find a working version so we can figure what the magic incantation is.
Also are the any utilities to dump the northbridge register contents on a running system ?
'lspci -s 0:0.0 -xxx' will dump the entire northbridge pci space. man lspci for more details.
What sort of tools are we talking about to compile the earlier stuff ?
Older toolchains. gcc-2.95, gcc-3.x, and the various binutils that came with them. Basically grabbing some older distributions and using their toolchain.
Newer toolchains have issues with older romcc. Newer romcc's have issues with the constructs in older revs.
I will attempt to get you a rom image of a working linuxbios rom tonight. I have one.
ron
On 9/6/06, Ronald G Minnich rminnich@lanl.gov wrote:
I will attempt to get you a rom image of a working linuxbios rom tonight. I have one.
That would be a magic bullet. If we can boot that, dump the northbridge settings and compare vs what LB is currently doing then we know a _lot_. If they are the same then I think we have strong evidence that something in the newer chips is different.
Please send it to "Alex Mauer" hawke42@gmail.com and cc me.
Hello Richard, Ben, Uwe, et all
I've been following this thread for a little while, and have this 2 pence ( or 2 cents for the US/rest of Europe) to add.
Based on the conversations, I've pulled the following rev's (based on changes to the raminit.c) and tried building using the gcc 3.4.4 toolset.
*REV* *Build* *linuxbios.rom* *Reason for Failure* 1131 Failed No Target !! - looks like the via/epia target directory only exists from rev 1138 1138 no src/arc/i386/config/crt0.bast 1151 1154 1155 1156 1157 1159 1177 1179 1180 1227 1228 1259 Couldn't Parse Config file 1618 compile error - unsigned long long no supported 1619 1726 Success 1808 1952 Failed No rule to make target src/southbrigde/via/vt8231/vt8231_lpc.c needed by vt8321_lpc.o 1954 Success 1978
Output from Manufacturers Bios :-
00:00.0 Host bridge: VIA Technologies, Inc. VT8601 [Apollo ProMedia] (rev 05) 00: 06 11 01 06 06 00 90 a2 05 00 00 06 00 08 00 00 10: 08 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 10 60 30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: fe df c8 98 00 00 10 10 80 00 08 10 10 10 10 10 60: 3f 2a 00 20 e6 95 95 c4 42 ac 65 0d 08 7f 00 00 70: c0 88 ec 0c 0e 81 52 00 01 f4 01 00 00 00 00 00 80: 0f 40 00 00 00 00 00 00 03 00 68 07 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 02 00 20 00 07 02 00 07 00 00 00 00 6e 02 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 01 01 22 42 00 b0 00 08 00 00
Out of the 4 successes, I've trued the first 2 and have only gotten as far as the 'vt8601 done'
I've not modified the code to dump the registers yet, and the problem could be that the default config of PC100 and CL3 doesn't work for my ram which is causing it to hang after the raminit.
Hope this helps.
I'm going to try and get my system here install with serveral version of the gcc toolchain if I can
If there's anything you want me to try, or a particular version of gcc to try, I'll give it a go if I can as I'd love to see this board (I have both an epia 800 and epia 5000 ) working on LBv2 just as it did uner LBv1
Regards Mark Wilkinson.
Ben Hewson wrote:
Richard Smith wrote:
On 9/6/06, Ronald G Minnich rminnich@lanl.gov wrote:
I will attempt to get you a rom image of a working linuxbios rom tonight. I have one.
That would be a magic bullet. If we can boot that, dump the northbridge settings and compare vs what LB is currently doing then we know a _lot_. If they are the same then I think we have strong evidence that something in the newer chips is different.
Please send it to "Alex Mauer" hawke42@gmail.com and cc me.
when I get another PSU I'll boot my board up with the original bios and dump the northbridge settings. The board I am working on is rev D. I have another board in use as a firewall and that is a rev A so I could possibly see if that works any better or if there are any details.
There are a couple of bits in the code I don't quite get. Also the VT8601A datasheet mentions a BIOS porting guide. Does anyone have a copy of that. The actual VT8601A datasheet doesn't go into any detail on configuring ram.
Have also been looking at an SDRAM datasheet to see how that gets initialised. One of the bits I don't quite get is writing the SDRAM mode register (either 0x150 or 0x1d0 ). Can't see how that matches up to the SDRAM mode register bits and would'nt the MA mapping have an effect on that. The MA mapping register doesn't get written until later.
Currently using v3 something of gcc will need to check, again when I get a PSU.
Ben
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Ben Hewson -
Mark Wilkinson -
Richard Smith -
Ronald G Minnich -
Uwe Hermann