Hello everyone.
I have my hands on a piece of hardware here using the Super I/O device listed in the subject; that is:
Winbond LPC Super I/O WPCN381U
- My first question is, has anyone else encountered this device?
- SVN trunk of superiotool detects this device as:
Found NSC PC87382 (sid=0xf4, srid=0x04) at 0x2e
...and I know from the manufacturer that the device is actually the one mentioned previously. However, I know from the specsheet that the hardware is pin-compatible with the Winbond PC87381, which has a very similar name to the device it "thinks" it is.
http://www.winbond-usa.com/products/winbond_products/pdfs/APC/WPCN381U_pba.p...
Does this mean that superiotool is actually detecting it properly?
- Finally, the device I want to use waits for input via the serial port, but before this can be initiated the device must be powered on via the Super I/O module. According to the manufacturer, I do this by activating the GPIO03 pin. I know superiotool is a read-only tool, given I know these pieces of data, is there an easy way to ping this particular bit?
- My first approach to enable this device was to write a small kernel module that would call gpio_request(3); however, this always returns -ENOSYS or -EINVAL. This clearly isn't the right approach. :)
I realize this is probably a question for LKML proper, but I figured I'd ask here first and see what the Fates have in store. :)
Hey guys--I hate to bump this so soon, but my current project is pretty much stalled without being able to approach this issue one way or another.
Does anyone have any good documentation I can read to learn how to interact with (either in userspace or kernel-level) LPC devices, specifically the PC87381 Super I/O device? Perhaps there's some code in coreboot demonstrating how GPIO ports are manipulated?
On Mon, 2011-04-04 at 19:07 -0400, Jeremy Moles wrote:
Hello everyone.
I have my hands on a piece of hardware here using the Super I/O device listed in the subject; that is:
Winbond LPC Super I/O WPCN381U
My first question is, has anyone else encountered this device?
SVN trunk of superiotool detects this device as:
Found NSC PC87382 (sid=0xf4, srid=0x04) at 0x2e
...and I know from the manufacturer that the device is actually the one mentioned previously. However, I know from the specsheet that the hardware is pin-compatible with the Winbond PC87381, which has a very similar name to the device it "thinks" it is.
http://www.winbond-usa.com/products/winbond_products/pdfs/APC/WPCN381U_pba.p...
Does this mean that superiotool is actually detecting it properly?
- Finally, the device I want to use waits for input via the serial port,
but before this can be initiated the device must be powered on via the Super I/O module. According to the manufacturer, I do this by activating the GPIO03 pin. I know superiotool is a read-only tool, given I know these pieces of data, is there an easy way to ping this particular bit?
- My first approach to enable this device was to write a small kernel
module that would call gpio_request(3); however, this always returns -ENOSYS or -EINVAL. This clearly isn't the right approach. :)
I realize this is probably a question for LKML proper, but I figured I'd ask here first and see what the Fates have in store. :)
Jeremy Moles wrote:
Does anyone have any good documentation I can read to learn how to interact with (either in userspace or kernel-level) LPC devices,
LPC is directly accessible to the CPU, so you use outb and inb to make IO accesses.
specifically the PC87381 Super I/O device? Perhaps there's some code in coreboot demonstrating how GPIO ports are manipulated?
Look at what superiotool does, and/or use isaset from lm-sensors.
//Peter
Peter Stuge wrote:
specifically the PC87381 Super I/O device? Perhaps there's some code in coreboot demonstrating how GPIO ports are manipulated?
Look at what superiotool does
To clarify, superiotool has functions internally for writing to registers in superios, because they are needed by the program. There's just no user interface for writing, and there hasn't been much discussion on how it would look.
//Peter
On Thu, 2011-04-07 at 17:27 +0200, Peter Stuge wrote:
Peter Stuge wrote:
specifically the PC87381 Super I/O device? Perhaps there's some code in coreboot demonstrating how GPIO ports are manipulated?
Look at what superiotool does
To clarify, superiotool has functions internally for writing to registers in superios, because they are needed by the program. There's just no user interface for writing, and there hasn't been much discussion on how it would look.
Okay, thanks. :)
As a further question: as I mentioned in the first post, the information given to me (which is all we can get under our current NDA) is that to "power up" this device (unfortunately, the person giving us this information was certainly not a Linux engineer) we should manipulate the GPIO03 port.
Aren't these pins that simply accept a single bit (I see the terms HIGH/LOW used frequently in GPIO documentation). This means I will need to find whatever register corresponds to GPIO03 and set just that particular HIGH bit?
(Other keywords in their email were things like "GPIO:0x2" and GPIO:0x18", but I haven't been able to get any additional clarification from them...)
At any rate, thanks for your help. Hopefully I can use isaset, and if not I'll try using regwrite() in superiotool directrly (which just wraps OUTB anyways)...
//Peter
Jeremy Moles wrote:
To clarify, superiotool has functions internally for writing to registers in superios,
..
I will need to find whatever register corresponds to GPIO03 and set just that particular HIGH bit?
Yes. Look at the data sheet and maybe as a help you can step through superiotool as well.
(Other keywords in their email were things like "GPIO:0x2" and GPIO:0x18", but I haven't been able to get any additional clarification from them...)
Superios are easier to program than many other components, and are well documented, so you shouldn't have too much trouble. GPIO 3 is what you need to know about how the hardware is built.
//Peter
On Thu, 2011-04-07 at 17:39 +0200, Peter Stuge wrote:
Jeremy Moles wrote:
To clarify, superiotool has functions internally for writing to registers in superios,
..
I will need to find whatever register corresponds to GPIO03 and set just that particular HIGH bit?
Yes. Look at the data sheet and maybe as a help you can step through superiotool as well.
(Other keywords in their email were things like "GPIO:0x2" and GPIO:0x18", but I haven't been able to get any additional clarification from them...)
Superios are easier to program than many other components, and are well documented, so you shouldn't have too much trouble. GPIO 3 is what you need to know about how the hardware is built.
I do have a document describing the hardware pretty thoroughly, but I am unfamiliar with the terminology it uses and how I would map that into something I AM familiar with in Linux.
When you say well-documented: is there a particular document you can think of offhand?
At any rate, I'm sure I'm close to the edge of how much this list is willing to tolerate. :) Thanks for the help, hopefully I can make something out of this...
//Peter
On Thu, Apr 7, 2011 at 12:07 PM, Jeremy Moles cubicool@gmail.com wrote:
On Thu, 2011-04-07 at 17:39 +0200, Peter Stuge wrote:
Jeremy Moles wrote:
To clarify, superiotool has functions internally for writing to registers in superios,
..
I will need to find whatever register corresponds to GPIO03 and set just that particular HIGH bit?
Yes. Look at the data sheet and maybe as a help you can step through superiotool as well.
(Other keywords in their email were things like "GPIO:0x2" and GPIO:0x18", but I haven't been able to get any additional clarification from them...)
Superios are easier to program than many other components, and are well documented, so you shouldn't have too much trouble. GPIO 3 is what you need to know about how the hardware is built.
I do have a document describing the hardware pretty thoroughly, but I am unfamiliar with the terminology it uses and how I would map that into something I AM familiar with in Linux.
When you say well-documented: is there a particular document you can think of offhand?
At any rate, I'm sure I'm close to the edge of how much this list is willing to tolerate. :) Thanks for the help, hopefully I can make something out of this...
Perhaps this will help:
http://www.coreboot.org/Developer_Manual/Super_IO
Try looking at a datasheet for just about any Winbond super IO that does have a public datasheet, they all work generally the same way, just the LDNs and registers vary.
Also, have you tried contacting Winbond/Nuvoton for the datasheet? I've never had them deny me a datasheet, and never had to sign an NDA for one either. And have you inspected the board to find the Super IO and confirm that it is a Winbond? Sometimes designs change, it wouldn't surprise me to find that it really is the NSC chip.
-Corey
On Thu, 2011-04-07 at 13:15 -0400, Corey Osgood wrote:
On Thu, Apr 7, 2011 at 12:07 PM, Jeremy Moles cubicool@gmail.com wrote:
On Thu, 2011-04-07 at 17:39 +0200, Peter Stuge wrote:
Jeremy Moles wrote:
To clarify, superiotool has functions internally for writing to registers in superios,
..
I will need to find whatever register corresponds to GPIO03 and set just that particular HIGH bit?
Yes. Look at the data sheet and maybe as a help you can step through superiotool as well.
(Other keywords in their email were things like "GPIO:0x2" and GPIO:0x18", but I haven't been able to get any additional clarification from them...)
Superios are easier to program than many other components, and are well documented, so you shouldn't have too much trouble. GPIO 3 is what you need to know about how the hardware is built.
I do have a document describing the hardware pretty thoroughly, but I am unfamiliar with the terminology it uses and how I would map that into something I AM familiar with in Linux.
When you say well-documented: is there a particular document you can think of offhand?
At any rate, I'm sure I'm close to the edge of how much this list is willing to tolerate. :) Thanks for the help, hopefully I can make something out of this...
Perhaps this will help:
http://www.coreboot.org/Developer_Manual/Super_IO
Try looking at a datasheet for just about any Winbond super IO that does have a public datasheet, they all work generally the same way, just the LDNs and registers vary.
I do have the datasheet for the hardware in question:
http://jeremymoles.com/WPCN381U.pdf
(This was downloaded from a public URL, though I cannot remember it now...)
Also, have you tried contacting Winbond/Nuvoton for the datasheet? I've never had them deny me a datasheet, and never had to sign an NDA for one either. And have you inspected the board to find the Super IO and confirm that it is a Winbond? Sometimes designs change, it wouldn't surprise me to find that it really is the NSC chip.
It's not that the hardware specs are unvailable, it's simply that I lack the knowledge to be able to translate the information form the hardware vendor (i.e., their engineer telling me to simply ping GPIO-03 on the SuperI/O controller and the hardware lights up) into Linux code. :) In Windows, apparently, it's as easy as that...
I tried running isaset to set every single register to 0xFF, but this doesn't do anything except turn the serial port off. Besides, I don't expect this would work anyways, as the GPIO registers I need are abstracted away in an LDN (7, in my case), and I think you need to inform the hardware of that FIRST before writing any bits.
-Corey
Jeremy Moles wrote:
It's not that the hardware specs are unvailable, it's simply that I lack the knowledge to be able to translate the information form the hardware vendor (i.e., their engineer telling me to simply ping GPIO-03 on the SuperI/O controller and the hardware lights up) into Linux code. :) In Windows, apparently, it's as easy as that...
If anything I'd say it's more difficult in Windows.
the GPIO registers I need are abstracted away in an LDN (7, in my case), and I think you need to inform the hardware of that FIRST before writing any bits.
Correct. Looking at chapter 5 it's also clear that actual data for GPIO pins is written using registers offset from an IO base address configured in the logical device. So steps are:
set gpio ldn: regwrite(7,7) read io base address: regread(60h)<<8 | regread(61h) read current GPIO-0 value: inb(base address) set bit 3 in value (1<<3) write new GPIO-0 value: outb(base,newval)
//Peter
On Thu, 2011-04-07 at 19:52 +0200, Peter Stuge wrote:
Jeremy Moles wrote:
It's not that the hardware specs are unvailable, it's simply that I lack the knowledge to be able to translate the information form the hardware vendor (i.e., their engineer telling me to simply ping GPIO-03 on the SuperI/O controller and the hardware lights up) into Linux code. :) In Windows, apparently, it's as easy as that...
If anything I'd say it's more difficult in Windows.
the GPIO registers I need are abstracted away in an LDN (7, in my case), and I think you need to inform the hardware of that FIRST before writing any bits.
Correct. Looking at chapter 5 it's also clear that actual data for GPIO pins is written using registers offset from an IO base address configured in the logical device. So steps are:
set gpio ldn: regwrite(7,7) read io base address: regread(60h)<<8 | regread(61h) read current GPIO-0 value: inb(base address) set bit 3 in value (1<<3) write new GPIO-0 value: outb(base,newval
With this lists help and Tom Sylla's help, I was able to get the device working. :) If our contractors permit, I will release the code as OSS. At the very least I'm trying to authorize donations...
Thanks a ton, a great resource here!
//Peter
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Corey Osgood -
Jeremy Moles -
Peter Stuge