New patch to review for coreboot: 6b3747f i945: fix tsc udelay()

[Sven Schnelle]

Sven Schnelle ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/530

-gerrit

commit 6b3747fcc1a57223a25b60e391dc9c1db9ddbbdd
Author: Sven Schnelle 
Date:   Tue Jan 10 12:16:38 2012 +0100

i945: fix tsc udelay()

The comparision is the wrong way round: as long as tsc
    is below tsc1, the timeout is not reached

Change-Id: I75de74ef750b5a45be0156efaf10d7239a0b1136
    Signed-off-by: Sven Schnelle 
---
 src/northbridge/intel/i945/udelay.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c
index 6b3882b..9170335 100644
--- a/src/northbridge/intel/i945/udelay.c
+++ b/src/northbridge/intel/i945/udelay.c
@@ -78,7 +78,7 @@ void udelay(u32 us)

do {
    	tsc = rdtsc();
-	} while ((tsc.hi > tsc1.hi)
-		 || ((tsc.hi == tsc1.hi) && (tsc.lo > tsc1.lo)));
+	} while ((tsc.hi < tsc1.hi)
+		 || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));

}