Author: uwe Date: Wed Oct 20 22:21:27 2010 New Revision: 5978 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5978
Log: Revert sblk/sblink change, use sblk like the rest of the codebase does.
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c
Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_gfx.c Wed Oct 20 21:23:22 2010 (r5977) +++ trunk/src/southbridge/amd/rs780/rs780_gfx.c Wed Oct 20 22:21:27 2010 (r5978) @@ -304,7 +304,7 @@ volatile u32 * pointer; int i; u16 command; - u32 value, sblink; + u32 value, sblk; u16 deviceid, vendorid; device_t nb_dev = dev_find_slot(0, 0); device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2)); @@ -455,13 +455,13 @@
/* Get SBLink value (HyperTransport I/O Hub Link ID). */ value = pci_read_config32(k8_f0, 0x64); - sblink = (value >> 8) & 0x3; - printk(BIOS_DEBUG, "SBLINK = %d.\n", sblink); + sblk = (value >> 8) & 0x3; + printk(BIOS_DEBUG, "SBLINK = %d.\n", sblk);
/* HT speed */ value = pci_read_config32(nb_dev, 0xd0); printk(BIOS_DEBUG, "NB HT speed = %x.\n", value); - value = pci_read_config32(k8_f0, 0x88 + (sblink * 0x20)); + value = pci_read_config32(k8_f0, 0x88 + (sblk * 0x20)); printk(BIOS_DEBUG, "CPU HT speed = %x.\n", value); vgainfo.ulHTLinkFreq = 100 * 100; /* set HT speed. */