r3197 - in trunk/coreboot-v2: src/mainboard src/mainboard/televideo src/mainboard/televideo/tc7020 targets targets/televideo targets/televideo/tc7020
Author: uwe Date: 2008-03-29 18:24:58 +0100 (Sat, 29 Mar 2008) New Revision: 3197 Added: trunk/coreboot-v2/src/mainboard/televideo/ trunk/coreboot-v2/src/mainboard/televideo/tc7020/ trunk/coreboot-v2/src/mainboard/televideo/tc7020/Config.lb trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb trunk/coreboot-v2/src/mainboard/televideo/tc7020/auto.c trunk/coreboot-v2/src/mainboard/televideo/tc7020/chip.h trunk/coreboot-v2/src/mainboard/televideo/tc7020/irq_tables.c trunk/coreboot-v2/src/mainboard/televideo/tc7020/mainboard.c trunk/coreboot-v2/targets/televideo/ trunk/coreboot-v2/targets/televideo/tc7020/ trunk/coreboot-v2/targets/televideo/tc7020/Config.lb Log: Add support for the TeleVideo TC7020. Signed-off-by: Kenji Noguchi <tokyo246@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Added: trunk/coreboot-v2/src/mainboard/televideo/tc7020/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/televideo/tc7020/Config.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/Config.lb 2008-03-29 17:24:58 UTC (rev 3197) @@ -0,0 +1,138 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Kenji Noguchi <tokoy246@gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) +else + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) + default ROM_SECTION_OFFSET = 0 +end +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +default XIP_ROM_SIZE = 64 * 1024 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +arch i386 end +driver mainboard.o +if HAVE_PIRQ_TABLE + object irq_tables.o +end +makerule ./failover.E + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./failover.inc + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./auto.E + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end +mainboardinit arch/i386/lib/cpu_reset.inc +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/amd/model_gx1/cpu_setup.inc +mainboardinit cpu/amd/model_gx1/gx_setup.inc +mainboardinit ./auto.inc + +dir /pc80 +config chip.h + +chip northbridge/amd/gx1 # Northbridge + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + chip southbridge/amd/cs5530 # Southbridge + device pci 12.0 on # ISA bridge + chip superio/nsc/pc97317 # Super I/O + device pnp 2e.0 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.1 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.2 on # RTC, Advanced power control (APC) + io 0x60 = 0x70 + irq 0x70 = 8 + end + device pnp 2e.3 off # Floppy (N/A on this board) + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.4 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.5 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.6 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0xe0 + end + device pnp 2e.8 on # Power management + io 0x60 = 0xe8 + end + end + end + device pci 12.1 off end # SMI + device pci 12.2 on end # IDE + device pci 12.3 on end # Audio + device pci 12.4 on end # VGA (onboard) + device pci 13.0 on end # USB + device pci 14.0 on end # MiniPCI slot + device pci 15.0 on end # Ethernet (onboard) + register "ide0_enable" = "1" + register "ide1_enable" = "0" # Not available/needed on this board + end + end + chip cpu/amd/model_gx1 # CPU + end +end Added: trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb 2008-03-29 17:24:58 UTC (rev 3197) @@ -0,0 +1,106 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Kenji Noguchi <tokyo246@gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses COREBOOT_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_VIDEO_MB +uses CONFIG_SPLASH_GRAPHIC +uses CONFIG_GX1_VIDEO +uses CONFIG_GX1_VIDEOMODE +uses PIRQ_ROUTE + +## Enable VGA with a splash screen (only 640x480 to run on most monitors). +## We want to support up to 1024x768@16 so we need 2MiB video memory. +## Note: Higher resolutions might need faster SDRAM speed. +default CONFIG_GX1_VIDEO = 1 +default CONFIG_GX1_VIDEOMODE = 0 +default CONFIG_SPLASH_GRAPHIC = 1 +default CONFIG_VIDEO_MB = 2 +default HAVE_PIRQ_TABLE=0 +default PIRQ_ROUTE=1 + +default ROM_SIZE = 256 * 1024 +default MAINBOARD_VENDOR = "TeleVideo" +default MAINBOARD_PART_NUMBER = "TC7020" +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default HAVE_HARD_RESET = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 3 # Soldered NIC, internal USB, mini PCI slot +default HAVE_OPTION_TABLE = 0 +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +default USE_OPTION_TABLE = 0 +default _RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc " +default HOSTCC = "gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 # 8n1 +default DEFAULT_CONSOLE_LOGLEVEL = 6 +default MAXIMUM_CONSOLE_LOGLEVEL = 6 + +end Added: trunk/coreboot-v2/src/mainboard/televideo/tc7020/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/televideo/tc7020/auto.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/auto.c 2008-03-29 17:24:58 UTC (rev 3197) @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "northbridge/amd/gx1/raminit.c" +#include "superio/nsc/pc97317/pc97317_early_serial.c" +#include "cpu/x86/bist.h" + +#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) + +static void main(unsigned long bist) +{ + /* Initialize the serial console. */ + pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + /* Initialize RAM. */ + sdram_init(); + + /* Check whether RAM works. */ + /* ram_check(0, 640 * 1024); */ +} Added: trunk/coreboot-v2/src/mainboard/televideo/tc7020/chip.h =================================================================== --- trunk/coreboot-v2/src/mainboard/televideo/tc7020/chip.h (rev 0) +++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/chip.h 2008-03-29 17:24:58 UTC (rev 3197) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Kenji Noguchi <tokyo246@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_televideo_tc7020_ops; + +struct mainboard_televideo_tc7020_config { + int nothing; +}; Added: trunk/coreboot-v2/src/mainboard/televideo/tc7020/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/televideo/tc7020/irq_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/irq_tables.c 2008-03-29 17:24:58 UTC (rev 3197) @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com> + * Copyright (C) 2007 Kenji Noguchi <tokyo246@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <device/pci.h> + +/* Platform IRQs */ +#define PIRQA 11 +#define PIRQB 10 +#define PIRQC 9 +#define PIRQD 12 + +/* Link */ +#define LINK_PIRQA 1 +#define LINK_PIRQB 2 +#define LINK_PIRQC 3 +#define LINK_PIRQD 4 +#define LINK_NONE 0 + +/* Map */ +#define IRQ_BITMAP_LINKA (1 << PIRQA) +#define IRQ_BITMAP_LINKB (1 << PIRQB) +#define IRQ_BITMAP_LINKC (1 << PIRQC) +#define IRQ_BITMAP_LINKD (1 << PIRQD) +#define IRQ_BITMAP_NOLINK 0x0 + +#define EXCLUSIVE_PCI_IRQS (IRQ_BITMAP_LINKA | IRQ_BITMAP_LINKB | IRQ_BITMAP_LINKC | IRQ_BITMAP_LINKD) + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*IRQ_SLOT_COUNT, /* There can be a total of IRQ_SLOT_COUNT devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ + EXCLUSIVE_PCI_IRQS, /* IRQs devoted exclusively to PCI usage */ + 0x1078, /* Vendor */ + 0x1, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x60, /* u8 checksum. This has to be set to some + value that would give 0 after the sum of all + bytes for this structure (including checksum) */ + + .slots = { + [0] = { + .slot = 0x0, /* means also "on board" */ + .bus = 0x00, + .devfn = (0x13<<3)|0x0, /* 0x13 is USB OHCI */ + .irq = { + [0] = { /* <-- 0 means this is INTA# output from the device or slot */ + .link = LINK_PIRQA, + .bitmap = IRQ_BITMAP_LINKA + }, + [1] = { /* <-- 1 means this is INTB# output from the device or slot */ + .link = LINK_NONE, + .bitmap = IRQ_BITMAP_NOLINK + }, + [2] = { /* <-- 2 means this is INTC# output from the device or slot */ + .link = LINK_NONE, + .bitmap = IRQ_BITMAP_NOLINK + }, + [3] = { /* <-- 3 means this is INTD# output from the device or slot */ + .link = LINK_NONE, + .bitmap = IRQ_BITMAP_NOLINK + } + } + }, + + [1] = { + .slot = 0x0, /* means also "on board" */ + .bus = 0x00, + .devfn = (0x15<<3)|0x0, /* 0x15 is NSC Network device */ + .irq = { + [0] = { /* <-- 0 means this is INTA# output from the device or slot */ + .link = LINK_PIRQB, + .bitmap = IRQ_BITMAP_LINKB + }, + [1] = { /* <-- 1 means this is INTB# output from the device or slot */ + .link = LINK_NONE, + .bitmap = IRQ_BITMAP_NOLINK + }, + [2] = { /* <-- 2 means this is INTC# output from the device or slot */ + .link = LINK_NONE, + .bitmap = IRQ_BITMAP_NOLINK + }, + [3] = { /* <-- 3 means this is INTD# output from the device or slot */ + .link = LINK_NONE, + .bitmap = IRQ_BITMAP_NOLINK + } + } + }, + + [2] = { + .slot = 0x1, /* This is a Mini PCI slot */ + .bus = 0x00, + .devfn = (0x14<<3)|0x0, + .irq = { + [0] = { /* <-- 0 means this is INTA# output from the device or slot */ + .link = LINK_PIRQC, + .bitmap = IRQ_BITMAP_LINKC + }, + [1] = { /* <-- 1 means this is INTB# output from the device or slot */ + /* NEEDSWORK: not confirmed. No device to test which uses both INTA and INTB */ + .link = LINK_PIRQD, + .bitmap = IRQ_BITMAP_LINKD + }, + [2] = { /* No INTC# for Mini PCI */ + .link = LINK_NONE, + .bitmap = IRQ_BITMAP_NOLINK + }, + [3] = { /* No INTD# for Mini PCI */ + .link = LINK_NONE, + .bitmap = IRQ_BITMAP_NOLINK + } + } + }, + } +}; + +/** + * Copy the IRQ routing table to memory. + * + * @param addr Destination address (between 0xF0000...0x100000). + * @return The end address of the pirq routing table in memory. + */ +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/coreboot-v2/src/mainboard/televideo/tc7020/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/televideo/tc7020/mainboard.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/mainboard.c 2008-03-29 17:24:58 UTC (rev 3197) @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Kenji Noguchi <tokyo246@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_televideo_tc7020_ops = { + CHIP_NAME("TeleVideo TC7020 Mainboard") +}; + Added: trunk/coreboot-v2/targets/televideo/tc7020/Config.lb =================================================================== --- trunk/coreboot-v2/targets/televideo/tc7020/Config.lb (rev 0) +++ trunk/coreboot-v2/targets/televideo/tc7020/Config.lb 2008-03-29 17:24:58 UTC (rev 3197) @@ -0,0 +1,51 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Kenji Noguchi <tokyo246@gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target tc7020 +mainboard televideo/tc7020 + +option ROM_SIZE = 256 * 1024 + +## Enable VGA with a splash screen (only 640x480 to run on most monitors). +## We want to support up to 1024x768@16 so we need 2MiB video memory. +## Note: Higher resolutions might need faster SDRAM speed. +option CONFIG_GX1_VIDEO = 1 +option CONFIG_GX1_VIDEOMODE = 0 +option CONFIG_SPLASH_GRAPHIC = 1 +option CONFIG_VIDEO_MB = 2 + +option DEFAULT_CONSOLE_LOGLEVEL = 6 +option MAXIMUM_CONSOLE_LOGLEVEL = 6 + +romimage "normal" + option USE_FALLBACK_IMAGE = 0 + option ROM_IMAGE_SIZE = 64 * 1024 + option COREBOOT_EXTRA_VERSION = ".0Normal" + payload /tmp/filo.elf +end + +romimage "fallback" + option USE_FALLBACK_IMAGE = 1 + option ROM_IMAGE_SIZE = 64 * 1024 + option COREBOOT_EXTRA_VERSION = ".0Fallback" + payload /tmp/filo.elf +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
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