In case ya'll are curious, here is a typical startup for the Eden/vt8601/vt8231. Debugging messages are a bit verbose, because I have POST codes redirected to the serial port. Yay! LinuxBIOS-1.0.0 Tue Oct 29 10:35:58 PST 2002 starting... <35><36>Copying LinuxBIOS to ram. <11><12><fe>Jumping to LinuxBIOS. <fd>POST: 0x39 LinuxBIOS-1.0.0 Tue Oct 29 10:35:58 PST 2002 booting... POST: 0x40 Finding PCI configuration type. PCI: Using configuration type 1 POST: 0x5f Scanning PCI bus...PCI: pci_scan_bus for bus 0 POST: 0x24 PCI: 00:00.0 [1106/0601] PCI: 00:01.0 [1106/8601] PCI: 00:11.0 [1106/8231] PCI: 00:11.1 [1106/0571] PCI: 00:11.2 [1106/3038] PCI: 00:11.3 [1106/3038] PCI: 00:11.4 [1106/8235] PCI: 00:11.5 [1106/3058] PCI: 00:11.6 [1106/3068] PCI: 00:12.0 [1106/3065] PCI: 00:14.0 [1033/0035] PCI: 00:14.1 [1033/0035] PCI: 00:14.2 [1033/00e0] POST: 0x25 PCI: pci_scan_bus for bus 1 POST: 0x24 POST: 0x25 PCI: pci_scan_bus returning with max=01 POST: 0x55 PCI: pci_scan_bus returning with max=01 POST: 0x55 done POST: 0x66 Allocating PCI resources... PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it ASSIGN RESOURCES, bus 0 PCI: 00:01.0 1c <- [0x00001000 - 0x00000fff] bus 1 ÿÿÿÿÿÿ°io PCI: 00:01.0 24 <- [0xfeb00000 - 0xfeafffff] bus 1 ÿÿÿÿÿÿ°prefmem PCI: 00:01.0 20 <- [0xfeb00000 - 0xfeafffff] bus 1 ÿÿÿÿÿÿ°mem PCI: 00:11.1 10 <- [0x00001c50 - 0x00001c57] io PCI: 00:11.1 14 <- [0x00001c70 - 0x00001c73] io PCI: 00:11.1 18 <- [0x00001c60 - 0x00001c67] io PCI: 00:11.1 1c <- [0x00001c80 - 0x00001c83] io PCI: 00:11.1 20 <- [0x00001c40 - 0x00001c4f] io PCI: 00:11.2 20 <- [0x00001c00 - 0x00001c1f] io PCI: 00:11.3 20 <- [0x00001c20 - 0x00001c3f] io PCI: 00:11.5 10 <- [0x00001000 - 0x000010ff] io PCI: 00:11.5 14 <- [0x00001c90 - 0x00001c93] io PCI: 00:11.5 18 <- [0x00001ca0 - 0x00001ca3] io PCI: 00:11.6 10 <- [0x00001400 - 0x000014ff] io PCI: 00:12.0 10 <- [0x00001800 - 0x000018ff] io PCI: 00:12.0 14 <- [0xfeb02000 - 0xfeb020ff] mem PCI: 00:14.0 10 <- [0xfeb00000 - 0xfeb00fff] mem PCI: 00:14.1 10 <- [0xfeb01000 - 0xfeb01fff] mem PCI: 00:14.2 10 <- [0xfeb03000 - 0xfeb030ff] mem done. POST: 0x88 Enabling PCI resourcess...PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 cmd <- 07 PCI: 00:11.0 cmd <- 87 PCI: 00:11.1 cmd <- 81 PCI: 00:11.2 cmd <- 01 PCI: 00:11.3 cmd <- 01 PCI: 00:11.4 cmd <- 00 PCI: 00:11.5 cmd <- 01 PCI: 00:11.6 cmd <- 01 PCI: 00:12.0 cmd <- 83 PCI: 00:14.0 cmd <- 02 PCI: 00:14.1 cmd <- 02 PCI: 00:14.2 cmd <- 02 done. Initializing PCI devices... PCI devices initialized POST: 0x89 sizeram: returning 0xfc00 KB sizeram: NOT returning 0xfc00 KB sizeram: there are still some SPD problems ... sizeram: SO we return only 0x10000 KB POST: 0x70 totalram: 64M Initializing CPU #0 POST: 0x60 Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 64MB, type WB DONE variable MTRRs Clear out the extra MTRR's call intel_enable_fixed_mtrr() call intel_enable_var_mtrr() Leave setup_mtrrs POST: 0x6a done. Max cpuid index : 1 Vendor ID : CentaurHauls Processor Type : 0x00 Processor Family : 0x06 Processor Model : 0x07 Processor Mask : 0x00 Processor Stepping : 0x03 Feature flags : 0x00803035 POST: 0x92 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Disabling local apic...done. POST: 0x9b CPU #0 Initialized POST: 0x75 POST: 0x77 IDE enable in reg. 50 is 0x7 set IDE reg. 50 to 0x7 IRQs in reg. 4c are 0x4 setting reg. 4c to 0x4 enables in reg 0x40 0x8 enables in reg 0x40 read back as 0xb enables in reg 0x9 0x8f enables in reg 0x9 read back as 0x8f command in reg 0x4 0x81 command in reg 0x4 reads back as 0x85 Mainboard fixup POST: 0x91 POST: 0x92 POST: 0x05 POST: 0x05 POST: 0x05 POST: 0x06 POST: 0x95 POST: 0xec POST: 0x9a Copying IRQ routing tables to 0xf0000...done. POST: 0x96 Wrote linuxbios table at: 00000500 - 00000670 checksum bcd2 Jumping to linuxbiosmain()... POST: 0xed Welcome to start32, the open sourced starter. This space will eventually hold more diagnostic information. January 2000, James Hendricks, Dale Webster, and Ron Minnich. Version 0.1 POST: 0xf1 37:init_bytes() - zkernel_start:0xfff80000 zkernel_mask:0x0000ffff Gunzip setup gunzip_setup output data is 0x00100000 Gunzipping boot code flush 0x00100000 count 0x00008000 flush 0x00108000 count 0x00008000 flush 0x00110000 count 0x00008000 flush 0x00118000 count 0x00008000 flush 0x00120000 count 0x00008000 flush 0x00128000 count 0x00008000 flush 0x00130000 count 0x00008000 flush 0x00138000 count 0x00008000 flush 0x00140000 count 0x00008000 flush 0x00148000 count 0x00008000 flush 0x00150000 count 0x00008000 flush 0x00158000 count 0x00008000 flush 0x00160000 count 0x00008000 flush 0x00168000 count 0x00008000 flush 0x00170000 count 0x00008000 flush 0x00178000 count 0x00008000 flush 0x00180000 count 0x00008000 flush 0x00188000 count 0x00008000 flush 0x00190000 count 0x00008000 flush 0x00198000 count 0x00008000 flush 0x001a0000 count 0x00008000 flush 0x001a8000 count 0x00008000 flush 0x001b0000 count 0x00008000 flush 0x001b8000 count 0x00008000 flush 0x001c0000 count 0x00005670 <973> POST: 0xf8 POST: 0xf9 POST: 0xfa command line - [root=/dev/hda1 single console=ttyS0,115200n8] Jumping to boot code POST: 0xfe Linux version 2.4.17 (kevinh@bumpy) (gcc version 2.95.4 20011002 (Debian prerelease)) #1 Tue Oct 29 10:15:10 PST 2002 BIOS-provided physical RAM map: BIOS-e801: 0000000000000000 - 000000000009f000 (usable) BIOS-e801: 0000000000100000 - 0000000003f00000 (usable) On node 0 totalpages: 16128 zone(0): 4096 pages. zone(1): 12032 pages. zone(2): 0 pages. Kernel command line: root=/dev/hda1 single console=ttyS0,115200n8 Initializing CPU#0 Detected 533.359 MHz processor. Calibrating delay loop... 1064.96 BogoMIPS Memory: 62104k/64512k available (530k kernel code, 2020k reserved, 167k data, 68k init, 0k highmem) Checking if this processor honours the WP bit even in supervisor mode... Ok. Dentry-cache hash table entries: 8192 (order: 4, 65536 bytes) Inode-cache hash table entries: 4096 (order: 3, 32768 bytes) Mount-cache hash table entries: 1024 (order: 1, 8192 bytes) Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes) Page-cache hash table entries: 16384 (order: 4, 65536 bytes) CPU: L1 I Cache: 64K (32 bytes/line), D cache 64K (32 bytes/line) CPU: L2 Cache: 64K (32 bytes/line) CPU: Centaur VIA Samuel 2 stepping 03 Checking 'hlt' instruction... OK. Checking for popad bug... OK. POSIX conformance testing by UNIFIX PCI: Using configuration type 1 PCI: Probing PCI hardware Scanning bus 00 Found 00:00 [1106/0601] 000600 00 Found 00:08 [1106/8601] 000604 01 Found 00:88 [1106/8231] 000601 00 Found 00:89 [1106/0571] 000101 00 Found 00:8c [1106/8235] 000000 00 Found 00:8d [1106/3058] 000401 00 Found 00:8e [1106/3068] 000780 00 Found 00:90 [1106/3065] 000200 00 Found 00:a0 [1033/0035] 000c03 00 Found 00:a1 [1033/0035] 000c03 00 Found 00:a2 [1033/00e0] 000c03 00 Fixups for bus 00 Scanning behind PCI bridge 00:01.0, config 010100, pass 0 Scanning bus 01 Fixups for bus 01 Unknown bridge resource 0: assuming transparent Unknown bridge resource 1: assuming transparent Unknown bridge resource 2: assuming transparent Bus scan for 01 returning with max=01 Scanning behind PCI bridge 00:01.0, config 010100, pass 1 Bus scan for 00 returning with max=01 PCI: Using IRQ router default [1106/0601] at 00:00.0 isapnp: Scanning for PnP cards... isapnp: No Plug & Play device found Linux NET4.0 for Linux 2.4 Based upon Swansea University Computer Society NET3.039 Starting kswapd Journalled Block Device driver loaded Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI ISAPNP enabled ttyS00 at 0x03f8 (irq = 4) is a 16550A block: 128 slots per queue, batch=32 Uniform Multi-Platform E-IDE driver Revision: 6.31 ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx VP_IDE: IDE controller on PCI bus 00 dev 89 VP_IDE: chipset revision 6 ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx VP_IDE: VIA vt8231 (rev 10) IDE UDMA100 controller on pci00:11.1 VP_IDE: 100% native mode on irq 14 VP_IDE: LINUXBIOS, so Jammed the enable on! ide0: BM-DMA at 0x0cc0-0x0cc7, BIOS settings: hda:pio, hdb:pio ide_init_via82cxxx: c01ae4d4 VP_IDE: LINUXBIOS, so Jammed the enable on! ide1: BM-DMA at 0x0cc8-0x0ccf, BIOS settings: hdc:pio, hdd:pio ide_init_via82cxxx: c01ae4d4 hda: C/H/S=0/0/0 from BIOS ignored jamming drive present for hda hda: WDC WD800BB-75CAA0, ATA DISK drive ide0 at 0x1f0-0x1f7,0x3f6 on irq 14 hda: 156250000 sectors (80000 MB) w/2048KiB Cache, CHS=155009/16/63, UDMA(33) Partition check: hda: hda1 hda2 hda3 hda4 < hda5 hda6 > kjournald starting. Commit interval 5 seconds EXT3-fs: mounted filesystem with ordered data mode. VFS: Mounted root (ext3 filesystem) readonly. Freeing unused kernel memory: 68k freed INIT: version 2.84 booting mount: proc has wrong device number or fs type proc not supported Loading /etc/console/boottime.kmap.gz Couldnt get a file descriptor referring to the console mount: proc has wrong device number or fs type proc not supported Activating swap. Adding Swap: 980268k swap-space (priority -1) Checking root file system... fsck 1.27 (8-Mar-2002) /dev/hda1: clean, 21565/488640 files, 99406/976247 blocks EXT3 FS 2.4-0.9.16, 02 Dec 2001 on ide0(3,1), internal journal System time was Tue Oct 29 18:23:17 UTC 2002. Setting the System Clock using the Hardware Clock as reference... System Clock set. System local time is now Tue Oct 29 18:23:18 UTC 2002. Checking all file systems... fsck 1.27 (8-Mar-2002) /dev/hda2: clean, 21548/488640 files, 98781/976248 blocks /dev/hda3: clean, 2009/122624 files, 45566/245070 blocks /dev/hda6: clean, 2461/8552448 files, 406944/17088497 blocks Setting kernel variables. Loading the saved-state of the serial devices... /dev/ttyS0 at 0x03f8 (irq = 4) is a 16550A grep: /proc/filesystems: No such file or directory grep: /proc/mounts: No such file or directory grep: /proc/mounts: No such file or directory /etc/init.d/rcS: [: =: unary operator expected Mounting local filesystems... kjournald starting. Commit interval 5 seconds EXT3 FS 2.4-0.9.16, 02 Dec 2001 on ide0(3,2), internal journal EXT3-fs: mounted filesystem with ordered data mode. /dev/hda2 on /altroot type ext3 (rw) kjournald starting. Commit interval 5 seconds EXT3 FS 2.4-0.9.16, 02 Dec 2001 on ide0(3,3), internal journal EXT3-fs: mounted filesystem with ordered data mode. /dev/hda3 on /var type ext3 (rw) kjournald starting. Commit interval 5 seconds EXT3 FS 2.4-0.9.16, 02 Dec 2001 on ide0(3,6), internal journal EXT3-fs: mounted filesystem with ordered data mode. /dev/hda6 on /user type ext3 (rw) Starting hotplug subsystem: usb. Running 0dns-down to make sure resolv.conf is ok...done. Cleaning: /etc/network/ifstate. No usable address families found. socket: Address family not supported by protocol Setting up IP spoofing protection: FAILED Configuring network interfaces: No usable address families found. socket: Address family not supported by protocol done. grep: /proc/filesystems: No such file or directory Setting the System Clock using the Hardware Clock as reference... System Clock set. Local time: Tue Oct 29 18:23:25 UTC 2002 Recovering jove files ... Done. Running ntpdate to synchronize clock. Cleaning: /tmp /var/lock /var/run. Initializing random number generator... done. Recovering nvi editor sessions... done. Give root password for maintenance (or type Control-D for normal startup): hardlife:~#
Are you using a eeprom burner for the bios on the via?
I've used an ICE and also a burner to write the FLASH. I haven't yet tried to burn the flash "in system" from some linux app, but it should be pretty straightforard MTD futzing. (On Tuesday 29 October 2002 14:08, Randall Craig wrote:
Are you using a eeprom burner for the bios on the via?
This is the ROMICE I used: http://www.romtools.com/romtools/p116045.html However it is pricy. The following smaller model would also work: http://www.romtools.com/romtools/p104045.html If you are not futzing with the internals of the BIOS a lot, then using a MTD driver and burning from a PC is fine. I only used the romICE because I had it laying around and it makes things very quick (i.e. when the build is done, the device downloads for two seconds and automatically hits reset on the board). Kevin On Tuesday 29 October 2002 15:27, Kevin Hester wrote:
I've used an ICE and also a burner to write the FLASH. I haven't yet tried to burn the flash "in system" from some linux app, but it should be pretty straightforard MTD futzing.
(On Tuesday 29 October 2002 14:08, Randall Craig wrote:
Are you using a eeprom burner for the bios on the via?
From " belkajm"@aardvark-ss.com Tue Oct 29 18:53:53 2002 Received: from hosting33.com ([203.194.209.173]) by nwn.definitive.org (8.11.6/8.11.6) with SMTP id g9TNrqI12304 for <linuxbios@clustermatic.org>; Tue, 29 Oct 2002 18:53:53 -0500 Message-Id: <200210292353.g9TNrqI12304@nwn.definitive.org> Received: (qmail 31059 invoked from network); 29 Oct 2002 23:01:32 -0000 Received: from unknown (HELO WebMail) (203.194.209.173) by hosting33.com with SMTP; 29 Oct 2002 23:01:32 -0000 From: belkajm <belkajm@aardvark-ss.com> To: <linuxbios@clustermatic.org> Reply-to: belkajm <belkajm@aardvark-ss.com> Subject: bios size X-Priority: 3 X-Mailer: WebMail 2.1 Content-Transfer-Encoding: 8bit X-MSMail-Priority: Medium Importance: Medium Content-Type: text/plain; charset="iso-8859-1"; MIME-Version: 1.0 Sender: linuxbios-admin@clustermatic.org Errors-To: linuxbios-admin@clustermatic.org X-BeenThere: linuxbios@clustermatic.org X-Mailman-Version: 2.0.11 Precedence: bulk List-Help: <mailto:linuxbios-request@clustermatic.org?subject=help> List-Post: <mailto:linuxbios@clustermatic.org> List-Subscribe: <http://www.clustermatic.org/mailman/listinfo/linuxbios>, <mailto:linuxbios-request@clustermatic.org?subject=subscribe> List-Id: Discussions regarding the LinuxBIOS project <linuxbios.clustermatic.org> List-Unsubscribe: <http://www.clustermatic.org/mailman/listinfo/linuxbios>, <mailto:linuxbios-request@clustermatic.org?subject=unsubscribe> List-Archive: <http://www.clustermatic.org/pipermail/linuxbios/> Date: Tue Oct 29 18:54:01 2002 X-Original-Date: Wed, 30 Oct 2002 7:01:32 Status: O Content-Length: 154 Lines: 7
Hi, How big is the linuxbios? and how much space is available on the epia boards? if it's not enough, what is the cheapest chip that can be used? Jody
Randall,
Are you using a eeprom burner for the bios on the via? flash_rom, from the linuxbios project, supports quite a few flash. To turn on epia flash write, you can
$ setpci -s 0:11.0 40.b=54 After this you can run $ flash_rom romimage -Andrew -- Andrew Ip Email: aip@cwlinux.com Tel: (852) 2542 2046 Fax: (852) 2542 2036 Mobile: (852) 9201 9866 Cwlinux Limited Unit 202B 2/F Lai Cheong Factory Building, 479-479A Castle Peak Road, Lai Chi Kok, Kowloon, Hong Kong. Tel: (852)2542 2046 Fax: (852)2542 2036 For public pgp key, please obtain it from http://www.keyserver.net/en.
After this you can run
$ flash_rom romimage
Aren't the bios chips soldered down on some of these boards? I was wondering what alternatives you have, short of unsoldering the chip and finding a programmer, if something goes wrong in the flashing process or the linuxbios code has a bug. -Steve
Aren't the bios chips soldered down on some of these boards? I was wondering what alternatives you have, short of unsoldering the chip and finding a programmer, if something goes wrong in the flashing process or the linuxbios code has a bug. The one I have doesn't soldered on board, so I can use Bios Savior to do development.
-Andrew -- Andrew Ip Email: aip@cwlinux.com Tel: (852) 2542 2046 Fax: (852) 2542 2036 Mobile: (852) 9201 9866 Cwlinux Limited Unit 202B 2/F Lai Cheong Factory Building, 479-479A Castle Peak Road, Lai Chi Kok, Kowloon, Hong Kong. Tel: (852)2542 2046 Fax: (852)2542 2036 For public pgp key, please obtain it from http://www.keyserver.net/en.
On Tue, 29 Oct 2002, Steve M. Gehlbach wrote:
Aren't the bios chips soldered down on some of these boards? I was wondering what alternatives you have, short of unsoldering the chip and finding a programmer, if something goes wrong in the flashing process or the linuxbios code has a bug.
you really should not buy a board with a bios soldered down ... there are very few of them because failed bios flashes in essence destroy a board. ron
Aren't the bios chips soldered down on some of these boards? I was wondering what alternatives you have, short of unsoldering the chip and finding a programmer, if something goes wrong in the flashing process or the linuxbios code has a bug.
you really should not buy a board with a bios soldered down ... there are very few of them because failed bios flashes in essence destroy a board.
ron
A number of the Giga-byte boards seem to have the bios soldered, in particular the the GA-6VEML (the Walmart $199 computer). The Via Eden appears to also but I am just looking at the photo. For the EPIA, if you bongo the PLCC (socketed), you'll need another PLCC bios mobo to fix it and hot swapping a PLCC has got to require a deft touch. Personally I prefer to use my Needham's programmer and I have never flashed on the mobo. In the case of the GA-6VEML, I intend to install an SM socket (PLCC) if I ever get to putting linuxbios on that one. But anyone considering linuxbios that does not have a programmer should think of their backup plan if there is a bug or flashing failure. The main point of my question, though, was if anyone was aware of another way to program the flash short of unsoldering it. I wasn't aware of any, and maybe it seemed like a silly question, but if the mobo mfrs would start using the LPC interface flash, and put a header on the mobo to access it, you could program it from a PC-LPT interface with a specially wired cable (plus a few R's and D's). This has been done on the Xbox and the software is available on the net. The LPC flash would also allow much larger memory in the same footprint, which is really useful. The success of this can depend somewhat on how the other chips behave, though, while programming (mobo power is off). -Steve
On Wed, 30 Oct 2002 14:44:02 -0800 "Steve M. Gehlbach" <steve@nexpath.com> wrote:
The main point of my question, though, was if anyone was aware of another way to program the flash short of unsoldering it.
JTAG ;-)
On Wed, 30 Oct 2002, Steve M. Gehlbach wrote:
A number of the Giga-byte boards seem to have the bios soldered, in particular the the GA-6VEML (the Walmart $199 computer). The Via Eden appears to also but I am just looking at the photo. For the EPIA, if you bongo the PLCC (socketed), you'll need another PLCC bios mobo to fix it and hot swapping a PLCC has got to require a deft touch.
A very clumsy touch is fine. I do this many times a day. The chips are very hardy. I think I may have lost one out of literally many dozens over the last few years. ron
On Wednesday 30 October 2002 17:44, Steve M. Gehlbach wrote:
Aren't the bios chips soldered down on some of these boards? I
was wondering
what alternatives you have, short of unsoldering the chip and finding a programmer, if something goes wrong in the flashing process or
the linuxbios
code has a bug.
you really should not buy a board with a bios soldered down ... there are very few of them because failed bios flashes in essence destroy a board.
ron
A number of the Giga-byte boards seem to have the bios soldered, in particular the the GA-6VEML (the Walmart $199 computer). The Via Eden appears to also but I am just looking at the photo. For the EPIA, if you bongo the PLCC (socketed), you'll need another PLCC bios mobo to fix it and hot swapping a PLCC has got to require a deft touch. Personally I prefer to use my Needham's programmer and I have never flashed on the mobo. In the case of the GA-6VEML, I intend to install an SM socket (PLCC) if I ever get to putting linuxbios on that one. But anyone considering linuxbios that does not have a programmer should think of their backup plan if there is a bug or flashing failure.
The main point of my question, though, was if anyone was aware of another way to program the flash short of unsoldering it. I wasn't aware of any, and maybe it seemed like a silly question, but if the mobo mfrs would start using the LPC interface flash, and put a header on the mobo to access it, you could program it from a PC-LPT interface with a specially wired cable (plus a few R's and D's). This has been done on the Xbox and the software is available on the net.
LinuxBIOS and kernel on the xbox? Where do I get a copy. I may have to pick up a used xbox. I dont think we would get the kind of help with porting linuxbios to that than we have other platforms. :)
The LPC flash would also allow much larger memory in the same footprint, which is really useful. The success of this can depend somewhat on how the other chips behave, though, while programming (mobo power is off).
-Steve
_______________________________________________ Linuxbios mailing list Linuxbios@clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios
On Fri, Nov 01, 2002 at 02:12:28PM -0500, GNUOrder wrote:
The main point of my question, though, was if anyone was aware of another way to program the flash short of unsoldering it. I wasn't aware of any, and maybe it seemed like a silly question, but if the mobo mfrs would start using the LPC interface flash, and put a header on the mobo to access it, you could program it from a PC-LPT interface with a specially wired cable (plus a few R's and D's). This has been done on the Xbox and the software is available on the net.
LinuxBIOS and kernel on the xbox? Where do I get a copy. I may have to pick up a used xbox. I dont think we would get the kind of help with porting linuxbios to that than we have other platforms. :)
The Xbox BIOS is actually somewhat documented on http://xbox-linux.sf.net/ And there's the $55k (I believe) reward for making an open source Xbox BIOS. Might compensate for the lack of documentation? :) Anyway, it's fairly easy to get hold of an "alternative" Xbox BIOS that allows you to run any software you want on your Xbox, not just stuff signed by MS. This other BIOS image can be put either into the TSOP40 memory soldered to the Xbox mainboard, or in a LPC memory that is connected to the LPC bus in the Xbox. You also need to pull down a signal on the mainboard to ground to make it boot from the LPC bus instead of the legacy ROM bus. I do believe that most flash memory chips are reprogrammable using the JEDEC commands, documented in any compliant flash memory data sheet. That does however involve writing to the chip and that's usually where the problem is, write-enable signals aren't always wired to the flash memory chips on mainboards and when they are they're connected to some GPIO port on the chipset. In some cases the memory controller also needs to be set to allow ROM writes, by flipping the right bit in the chipset PCI config space, otherwise it'll just block any write requests to the relevant address region. For the LPC programmer and friends, check out http://www.warmcat.com/milksop/ //Peter
On Wed, Oct 30, 2002 at 02:44:02PM -0800, Steve M. Gehlbach wrote:
For the EPIA, if you bongo the PLCC (socketed), you'll need another PLCC bios mobo to fix it and hot swapping a PLCC has got to require a deft touch.
Hi Steve, It should be possible to use the Bios Savior product (http://www.ioss.com.tw/eg/) on motherboards that have a socketed BIOS. This product allows one to backup the firmware BIOS to an alternate flash part and then switch between the two using an external switch. -Kevin -- ------------------------------------------------------------------------ | Kevin O'Connor "BTW, IMHO we need a FAQ for | | kevin@koconnor.net 'IMHO', 'FAQ', 'BTW', etc. !" | ------------------------------------------------------------------------
participants (9)
-
Andrew Ip -
GNUOrder -
Ian Molton -
Kevin Hester -
Kevin O'Connor -
Peter Stuge -
Randall Craig -
Ronald G Minnich -
Steve M. Gehlbach