Re: [coreboot] Samsung 550 Chromebook own Coreboot

[Kyösti Mälkki]

Did someone change the SPD eeprom address notation in pei_data from
7-bit to 8-bit addresses?

samsung/lumpy/romstage.c :
    .spd_addresses = { 0x50, 0x00,0xf0,0x00 },

google/stout/romstage.c :
    spd_addresses: { 0xA0, 0x00,0xA4,0x00 },

Kyösti

Samsung 550 Chromebook own Coreboot

[Aaron Durbin]

On Mon, Jul 29, 2013 at 10:22 AM, Kyösti Mälkki  wrote:
> Did someone change the SPD eeprom address notation in pei_data from
> 7-bit to 8-bit addresses?
>
> samsung/lumpy/romstage.c :
>         .spd_addresses = { 0x50, 0x00,0xf0,0x00 },
>
> google/stout/romstage.c :
>         spd_addresses: { 0xA0, 0x00,0xA4,0x00 },

The 0xf0 handles the soldered down memory. I was looking at the 0x50
address as well, but I think that is correct (I'm looking at code that
I think is the wrapper that you guys are using). I could be wrong
though.

Samsung 550 Chromebook own Coreboot

[Stefan Reinauer]

* Kyösti Mälkki  [130729 17:22]:
> Did someone change the SPD eeprom address notation in pei_data from
> 7-bit to 8-bit addresses?
>
> samsung/lumpy/romstage.c :
>    .spd_addresses = { 0x50, 0x00,0xf0,0x00 },
>
> google/stout/romstage.c :
>    spd_addresses: { 0xA0, 0x00,0xA4,0x00 },

Yes, the format changed when switching to the new system agent.

Fixes are on the way.

Samsung 550 Chromebook own Coreboot

[Duncan Laurie]

Unfortunately the input can depend on the systemagent binary.  In this case
the sandybridge-only binary has a different SMBUS layer and the 7-bit
notation is correct.  Now the systemagent code comes with its own driver
that uses 8-bit notation.

-duncan

On Mon, Jul 29, 2013 at 8:22 AM, Kyösti Mälkki wrote:
> Did someone change the SPD eeprom address notation in pei_data from
> 7-bit to 8-bit addresses?
>
> samsung/lumpy/romstage.c :
>         .spd_addresses = { 0x50, 0x00,0xf0,0x00 },
>
> google/stout/romstage.c :
>         spd_addresses: { 0xA0, 0x00,0xA4,0x00 },
>
> Kyösti