Re: [coreboot] coreboot Digest, Vol 58, Issue 20

[Harrison, Jon (SELEX GALILEO, UK)]

Hi,

Not been around for a while, but noticed this come by.

Seems to me that this config is pretty much identicle to my epia-n
config.
i.e. VIA EDEN ESP (C3) + Via CN400 + VT8237R +	W83627HG

There's not much difference between the CN400 and CLE266 so something
based on that config may just work without too much tweaking.

I've not built from svn for a long time and I don't remember if my final
patches ever got committed to the upstream. But in the final incarnation
my build was working well and had CBFS and optional SeaBIOS support.

My recollection is that there's a hardwired smbus address buried in
there somewhere that you might have to tweak for your MoBo to
successfully get through the raminit.

jon
> -----Original Message-----

[snip]
> Today's Topics:
> Re: VIA EDEN ESP (C3) + Apollo CLE266(VT8623) + VT8237R +
> W83627HG (Andrej Skirn)
>
> Message: 1
> Date: Tue, 08 Dec 2009 11:10:34 +0200
> From: Andrej Skirn 
> To: [e-mail]
> Subject: Re: [coreboot] VIA EDEN ESP (C3) + Apollo CLE266(VT8623) +
>    VT8237R +	W83627HG
> Message-ID: 
> Content-Type: text/plain; charset=ISO-8859-1; format=flowed
>
> Stefan Reinauer wrote:
> > On 12/8/09 12:58 AM, Andrej Skirn wrote:
> > > Presently, my main problem seems to be that the
> > > northbridge/via/vt8623/raminit.h does not define a mem_controller
> > > struct required by the southbridge code, so the north- and
>
> southbridge
> > > code don't seem to be clearly delimited.
> >
> > try completely commenting out smbus_fixup...
>
> Thanks from the quick reply. The code does indeed compile if 
> I undef out 
> the smbus_fixup() function in 
> suthbridge/via/vt8237r_early_smbus.c, or 
> use the cn400 raminit.h with the mem_controller definition and don't 
> call the smbus_fixup() function. But from the comments it would seem 
> like that's something I might need. Also judging from the 
> code I should 
> be getting console output starting from console_init(), before any of 
> the smbus operations, but as of yet I'm not seeing anything. 
> I will try 
> to track activity on LPC bus, but if someone has 
> experience/working code 
> for similar platform it would save a lot of effort.
>
> coreboot mailing list
> [e-mail]
> http://www.coreboot.org/mailman/listinfo/coreboot
>
> End of coreboot Digest, Vol 58, Issue 20

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