the following patch was just integrated into master: commit 9bf656b94d245b89d388fc63ff5512f32ad7b4ee Author: Stefan Reinauer reinauer@chromium.org Date: Mon Apr 30 16:42:07 2012 -0700
Fix SATA port map to only enable port 0
The sata controller comes up in legacy/normal mode and is currently put into AHCI mode in romstage.
If that is removed and the controller is left alone until the ramstage driver (like we do on Stumpy/Lumpy) then the resource allocator will have configured the device for IDE mode with an IO address in BAR5. Then when the ramstage driver puts the controller into AHCI mode it will not have the correct resources to do the rest of the AHCI setup.
So the controller mode needs to be changed in the enable stage rather than in the init phase. This same register contains the port map and it is a R/WO (write once) field so the configured port map must be written at the same time. For non-AHCI mode the devicetree map was ignored before but it is used now.
Since the port map register is now written at enable step it does not need to be written again during init.
With this change the sata port map can be reduced to just port 0 and then U-boot does not have to probe all available ports.
Change-Id: I977952cd88797ab4cea79202e832ecbb5c37e0bd Signed-off-by: Duncan Laurie dlaurie@chromium.org
Build-Tested: build bot (Jenkins) at Tue May 1 05:58:41 2012, giving +1 See http://review.coreboot.org/977 for details.
-gerrit