New patch to review for coreboot: 964adad Lippert Fam14 DSDT: Add secondary bus range to PCI0

[Mike Loptien]

Mike Loptien ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2737

-gerrit

commit 964adad87afb7c7f5032511176a689f7f4490539
Author: Mike Loptien 
Date:   Fri Mar 15 13:05:59 2013 -0600

Lippert Fam14 DSDT: Add secondary bus range to PCI0

Adding the 'WordBusNumber' macro to the PCI0
    CRES ResourceTemplate in the Persimmon DSDT.
    This sets up the bus number for the PCI0 device
    and the secondary bus number in the CRS method.
    This change came in response to a 'dmesg' error
    which states:
    '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS'

By adding the 'WordBusNumber' macro, ACPI can set
    up a valid range for the PCIe downstream busses,
    thereby relieving the Linux kernel from "guessing"
    the valid range based off _BBN or assuming [0-0xFF].
    The Linux kernel code that checks this bus range is
    in `drivers/acpi/pci_root.c`.  PCI busses can have
    up to 256 secondary busses connected to them via
    a PCI-PCI bridge.  However, these busses do not
    have to be sequentially numbered, so leaving out a
    section of the range (eg. allowing [0-0x7F]) will
    unnecessarily restrict the downstream busses.

This is the same change as made to Persimmon with
    change-id I44f22:
    http://review.coreboot.org/#/c/2592/

Change-Id: Ie36b60973c6a5f9076bb55c8f451532711a2f8a8
    Signed-off-by: Mike Loptien 
---
 src/mainboard/lippert/frontrunner-af/dsdt.asl | 16 ++++++++++++++++
 src/mainboard/lippert/toucan-af/dsdt.asl      | 16 ++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl
index d3b88f7..54c50b1 100644
--- a/src/mainboard/lippert/frontrunner-af/dsdt.asl
+++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl
@@ -1478,6 +1478,22 @@ DefinitionBlock (
    		} /* end Ac97modem */

Name(CRES, ResourceTemplate() {
+				/* Set the Bus number and Secondary Bus number for the PCI0 device
+				 * The Secondary bus range for PCI0 lets the system
+				 * know what bus values are allowed on the downstream
+				 * side of this PCI bus if there is a PCI-PCI bridge.
+				 * PCI busses can have 256 secondary busses which
+				 * range from [0-0xFF] but they do not need to be
+				 * sequential.
+				 */
+				WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+					0x0000,		/* address granularity */
+					0x0000,		/* range minimum */
+					0x00FF,		/* range maximum */
+					0x0000,		/* translation */
+					0x0100,		/* length */
+					,, PSB0)	/* ResourceSourceIndex, ResourceSource, DescriptorName */
+
    			IO(Decode16, 0x004E, 0x004E, 1, 2)	/* SIO config regs */
    			IO(Decode16, 0x0E00, 0x0E00, 1, 0x80)	/* SIO runtime regs */
    			IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl
index cde41b4..b72fb14 100644
--- a/src/mainboard/lippert/toucan-af/dsdt.asl
+++ b/src/mainboard/lippert/toucan-af/dsdt.asl
@@ -1478,6 +1478,22 @@ DefinitionBlock (
    		} /* end Ac97modem */

Name(CRES, ResourceTemplate() {
+				/* Set the Bus number and Secondary Bus number for the PCI0 device
+				 * The Secondary bus range for PCI0 lets the system
+				 * know what bus values are allowed on the downstream
+				 * side of this PCI bus if there is a PCI-PCI bridge.
+				 * PCI busses can have 256 secondary busses which
+				 * range from [0-0xFF] but they do not need to be
+				 * sequential.
+				 */
+				WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+					0x0000,		/* address granularity */
+					0x0000,		/* range minimum */
+					0x00FF,		/* range maximum */
+					0x0000,		/* translation */
+					0x0100,		/* length */
+					,, PSB0)	/* ResourceSourceIndex, ResourceSource, DescriptorName */
+
    			IO(Decode16, 0x004E, 0x004E, 1, 2)	/* SIO config regs */
    			IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)