Something has been troubling me for some time which is how the code manages to run before the memory controllers are configured. The assembler I can see has no accesses to memory, but the C code does, is their some magic gcc switch that makes it be entirely register based?
It's troubled me for a while one the memories up then I'm more than happy but before that I'm a little bemused.
Many thanks
Chris
* maillists@petrolhead.com maillists@petrolhead.com [040312 12:04]:
Something has been troubling me for some time which is how the code manages to run before the memory controllers are configured. The assembler I can see has no accesses to memory, but the C code does, is their some magic gcc switch that makes it be entirely register based?
The early initialization code of LinuxBIOS v1.1.x (upcoming v2) is written in C, but it does not use GCC for compilation, but Eric Biederman's ROMCC. This fine piece of software compiles C code to Assembler that does not use any RAM at all. All values are kept in registers. This allows only a certain complexity of the algorithms used, but it is perfectly fine to get RAM working.
Stefan
On Fri, 12 Mar 2004 maillists@petrolhead.com wrote:
Something has been troubling me for some time which is how the code manages to run before the memory controllers are configured. The assembler I can see has no accesses to memory, but the C code does, is their some magic gcc switch that makes it be entirely register based?
check out romcc. uses no memory. very neat.
ron
maillists@petrolhead.com writes:
Something has been troubling me for some time which is how the code manages to run before the memory controllers are configured. The assembler I can see has no accesses to memory, but the C code does, is their some magic gcc switch that makes it be entirely register based?
Unfortunately gcc's architecture does not appear to have the necessary support so I wrote romcc to do this.
It's troubled me for a while one the memories up then I'm more than happy but before that I'm a little bemused.
It is also possible to store data in the dcache if you can reliably lock in cache blocks. Your code still needs to run out of NOR flash. The PowerPC supports this. On x86 I have not seen any publicly documented and supported way to do this yet... I have done it and liked the results so much I implemented romcc.
Eric
On 12 Mar 2004, Eric W. Biederman wrote:
It is also possible to store data in the dcache if you can reliably lock in cache blocks. Your code still needs to run out of NOR flash. The PowerPC supports this. On x86 I have not seen any publicly documented and supported way to do this yet... I have done it and liked the results so much I implemented romcc.
Note that Greg Watson's PPC port of LinuxBIOS uses this 'early cacne' support.
It would be nice to see this capability in the K8++
ron
-
ebiederman＠lnxi.com -
maillists＠petrolhead.com -
ron minnich -
Stefan Reinauer