Hi,
I am trying to add a mainboard using celeron J1900 to coreboot-4.14, the serial console output stops after entering the MRC. The mrc.bin I used is extracted from Mrchromebox's roms for baytrail based chromebooks.
Hi there Yes it does. Rename mrc.bin to mrc.elf
Regards
On Thu, 4 Nov 2021 at 08:45, Zhiwen Zheng zhiwen@40701.xyz wrote:
Hi,
I am trying to add a mainboard using celeron J1900 to coreboot-4.14, the serial console output stops after entering the MRC. The mrc.bin I used is extracted from Mrchromebox's roms for baytrail based chromebooks. _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Now the raminit passed, thank you very much.
On Thu, 4 Nov 2021 08:56:49 +0000 Simon Newton simon.newton@gmail.com wrote:
Hi there Yes it does. Rename mrc.bin to mrc.elf
Regards
On Thu, 4 Nov 2021 at 08:45, Zhiwen Zheng zhiwen@40701.xyz wrote:
Hi,
I am trying to add a mainboard using celeron J1900 to coreboot-4.14, the serial console output stops after entering the MRC. The mrc.bin I used is extracted from Mrchromebox's roms for baytrail based chromebooks. _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
-- Kind Regards,
Simon Newton
E: Simon.newton@gmail.com
Hello,
On Thu, Nov 4, 2021 at 8:58 AM Simon Newton simon.newton@gmail.com wrote:
Hi there Yes it does. Rename mrc.bin to mrc.elf
Yes, the latest Bay Trail MRC binaries are ELF files, so their entry point is not at the beginning of the file. MRC's position in flash needs to be adjusted accordingly using the data in the ELF header. However, the Makefile only does this if the filename contains `elf` somewhere. https://review.coreboot.org/57989 removed the filename check, but it's not in the coreboot 4.14 release. Things like this are the reason why using the master branch for development is best (in most cases; there are exceptions, but this isn't one of them).
Regards
On Thu, 4 Nov 2021 at 08:45, Zhiwen Zheng zhiwen@40701.xyz wrote:
Hi,
I am trying to add a mainboard using celeron J1900 to coreboot-4.14, the serial console output stops after entering the MRC. The mrc.bin I used is extracted from Mrchromebox's roms for baytrail based chromebooks.
Yes, Bay Trail MRC works with the Celeron J1900, I know for sure because I've tried it myself. I started porting the Asrock Q1900M mainboard many months ago, https://review.coreboot.org/39658 contains the code. It's been over a year since I last updated this change, so it's very likely that it doesn't build on current coreboot.
I had to work around several MRC limitations to successfully boot coreboot on my Asrock Q1900M. The first limitation is that MRC can't read SPDs over SMBus, but https://review.coreboot.org/44092 already addresses this. The relevant code is in romstage.c after the `/* Patch memory type and voltage settings to make MRC happy */` comment on line 25, which overwrites some SPD information. The code does two things:
1. Bay Trail MRC refuses to work with the regular size DIMMs the Asrock Q1900M uses. Override the module type to SO-DIMM by patching byte 3 (Key Byte/Module Type). 2. Bay Trail MRC refuses to train DDR3 DIMMs that do not support 1.35V operation. Patch byte 6 (Module Nominal Voltage, VDD) to bypass this. Vendor firmware works properly with the same DIMMs.
While I was typing this, I noticed your latest reply. If RAM init succeeded, then the above workarounds aren't needed. Still, someone else might find this information useful in the future.
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-- Kind Regards,
Simon Newton
E: Simon.newton@gmail.com _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Best regards, Angel
I add the following code to sc_init() in southcluster.c to enable SERIRQ, and it works as expected when doing cold boot. With SERIRQ enabled, the uart in superio can function correctly, and I can login into the linux serial console. But after a reboot initiated from linux cmdline, the linux boot hang in getty serial(same as without SERIRQ enabled), only a power cycle can resolve the issue. I take the following code from coreboot-4.11 fsp-baytrail. I also tried the check_for_warm_reset() in bootblock.c to hardreset the machine, but the check condition in that procedure doesn't catch this situation, linux reset by default use keyboard controller seemingly.
u32 *oic = (u32 *)(ILB_BASE_ADDRESS + 0x60); u8 *serirq_cntl = (u8 *)(ILB_BASE_ADDRESS + 0x10);
/* Enable SERIRQ */ write32(oic, (read32(oic) | (1 << 12))); /* Enable continuous mode */ write8(serirq_cntl, (1 << 7));
On Thu, 04 Nov 2021 10:21:19 +0000 (UTC) Zhiwen Zheng zhiwen@40701.xyz wrote:
Now the raminit passed, thank you very much.
On Thu, 4 Nov 2021 08:56:49 +0000 Simon Newton simon.newton@gmail.com wrote:
Hi there Yes it does. Rename mrc.bin to mrc.elf
Regards
On Thu, 4 Nov 2021 at 08:45, Zhiwen Zheng zhiwen@40701.xyz wrote:
Hi,
I am trying to add a mainboard using celeron J1900 to coreboot-4.14, the serial console output stops after entering the MRC. The mrc.bin I used is extracted from Mrchromebox's roms for baytrail based chromebooks. _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
-- Kind Regards,
Simon Newton
E: Simon.newton@gmail.com
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
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Zhiwen Zheng