New patch to review for coreboot: 20ebb05 vt8237: add support for setting the power state after loss of power

[Florian Zumbiehl]

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/437

-gerrit

commit 20ebb056d1fe0a5084dc9203a59a59a10aa184d2
Author: Florian Zumbiehl 
Date:   Tue Nov 1 20:19:04 2011 +0100

vt8237: add support for setting the power state after loss of power

Change-Id: Ia7e3e77235530e952b2e84fdec8373b90fa59b7a
    Signed-off-by: Florian Zumbiehl 
---
 src/southbridge/via/vt8237r/lpc.c |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index b1e1afe..e5f2355 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -421,6 +421,7 @@ static void vt8237s_init(struct device *dev)
 static void vt8237_common_init(struct device *dev)
 {
    u8 enables, byte;
+	unsigned char pwr_on;

/* Enable addr/data stepping. */
    byte = pci_read_config8(dev, PCI_COMMAND);
@@ -508,6 +509,15 @@ static void vt8237_common_init(struct device *dev)
     */
    pci_write_config8(dev, 0x5b, 0xb);

+	/* configure power state of the board after loss of power */
+	if (get_option(&pwr_on, "power_on_after_fail") < 0)
+		pwr_on = 1;
+	enables = pci_read_config8(dev, 0x58);
+	pci_write_config8(dev, 0x58, enables & ~0x02);
+	outb(0x0d, 0x70);
+	outb(pwr_on ? 0x00 : 0x80, 0x71);
+	pci_write_config8(dev, 0x58, enables);
+
    /* Set 0x58 to 0x43 APIC and RTC. */
    pci_write_config8(dev, 0x58, 0x43);