New patch to review for coreboot: 6a26fdd AMD f14: Add SPD read functions to wrapper code

[Martin Roth]

Martin Roth ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2497

-gerrit

commit 6a26fddaee993b51f2d30c406def7bfed0fd9d74
Author: Martin Roth 
Date:   Sun Feb 24 10:46:11 2013 -0700

AMD f14: Add SPD read functions to wrapper code

CHANGE:
    This is the initial step for moving the AMD F14 SB800/HUDSON
    SPD-read callout out of the mainboard directories and into
    the vendorcode.  The next step is to update the platforms to use
    this routine in BiosCallouts.c and to delete the code from the
    mainboard directories.  The DIMM addresses should be moved into
    devicetree.cb.
    If there are significant differences or reasons that the mainboard
    needs to override this code, it's perfectly reasonable to keep using
    the version in the mainboard, but this allows us to remove duplicated
    code and simplify the mainboard directories.

NOTES:
    This code duplicates what was in persimmon, with changes to use the
    devicetree.cb structures.  The ASF setup was also removed from the
    persimmon copy (PMIO writes to 0x28 & 0x29) as that's not needed for
    the SPD access and doesn't make sense to initialize here.

It is intended that this file will not be included in ramstage as
    the DIMM init is all done in romstage.

A commit for Persimmon to use this code will follow shortly.

This is similar to what was done for Parmer/Thatcher in commit
    7fb692bd - http://review.coreboot.org/#/c/2190/
    Fam15tn: Move SPD read from mainboards into wrapper

Yes, it would make sense to split this into two separate files
    and move the SMBUS initialization and access into the southbridge
    wrapper.  Maybe that can come next.

Change-Id: I1e106d3912c160b0015bf02158d9faba4f578ee3
    Signed-off-by: Martin Roth 
---
 src/northbridge/amd/agesa/family14/Makefile.inc |   2 +
 src/northbridge/amd/agesa/family14/chip.h       |  28 ++++
 src/northbridge/amd/agesa/family14/dimmSpd.c    | 165 ++++++++++++++++++++++++
 src/northbridge/amd/agesa/family14/dimmSpd.h    |  56 ++++++++
 4 files changed, 251 insertions(+)

diff --git a/src/northbridge/amd/agesa/family14/Makefile.inc b/src/northbridge/amd/agesa/family14/Makefile.inc
index 8cdd0a0..eacd1f1 100644
--- a/src/northbridge/amd/agesa/family14/Makefile.inc
+++ b/src/northbridge/amd/agesa/family14/Makefile.inc
@@ -17,4 +17,6 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #

+romstage-y += dimmSpd.c
+
 ramstage-y += northbridge.c
diff --git a/src/northbridge/amd/agesa/family14/chip.h b/src/northbridge/amd/agesa/family14/chip.h
new file mode 100644
index 0000000..21f8c94
--- /dev/null
+++ b/src/northbridge/amd/agesa/family14/chip.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _AGESA_FAM14_CHIP_H_
+#define _AGESA_FAM14_CHIP_H_
+
+struct northbridge_amd_agesa_family14_config
+{
+	u8 spdAddrLookup[2][2][4];
+};
+
+#endif
diff --git a/src/northbridge/amd/agesa/family14/dimmSpd.c b/src/northbridge/amd/agesa/family14/dimmSpd.c
new file mode 100644
index 0000000..f416df5
--- /dev/null
+++ b/src/northbridge/amd/agesa/family14/dimmSpd.c
@@ -0,0 +1,165 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/pci_def.h>
+#include <device/device.h>
+#include <stdlib.h>
+#include "OEM.h" /* SMBUS0_BASE_ADDRESS */
+
+/* warning: Porting.h includes an open #pragma pack(1) */
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+#include "dimmSpd.h"
+#include "chip.h"
+
+//#pragma optimize ("", off) // for source level debug
+
+/*-----------------------------------------------------------------------------
+ *
+ * readSmbusByteData - read a single SPD byte from any offset
+ */
+
+static int readSmbusByteData (UINT16 iobase, UINT8 address, char *buffer, int offset)
+{
+	unsigned int status;
+	UINT64 limit;
+
+	address |= 1; // set read bit
+
+	__outbyte (iobase + 0, 0xFF);				// clear error status
+	__outbyte (iobase + 1, 0x1F);				// clear error status
+	__outbyte (iobase + 3, offset);				// offset in eeprom
+	__outbyte (iobase + 4, address);			// slave address and read bit
+	__outbyte (iobase + 2, 0x48);				// read byte command
+
+	// time limit to avoid hanging for unexpected error status (should never happen)
+	limit = __rdtsc () + 2000000000 / 10;
+	for (;;) {
+		status = __inbyte (iobase);
+		if (__rdtsc () > limit) break;
+		if ((status & 2) == 0) continue;		// SMBusInterrupt not set, keep waiting
+		if ((status & 1) == 1) continue;		// HostBusy set, keep waiting
+		break;
+	}
+
+	buffer [0] = __inbyte (iobase + 5);
+	if (status == 2)				// check for done with no errors
+		status = 0;
+	return status;
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ * readSmbusByte - read a single SPD byte from the default offset
+ *				 this function is faster function readSmbusByteData
+ */
+
+static UINT8 readSmbusByte (UINT16 iobase, UINT8 address, char *buffer)
+{
+	unsigned int status;
+	UINT64 limit;
+
+	__outbyte (iobase + 0, 0xFF);				// clear error status
+	__outbyte (iobase + 2, 0x44);				// read command
+
+	// time limit to avoid hanging for unexpected error status
+	limit = __rdtsc () + 2000000000 / 10;
+	for (;;) {
+		status = __inbyte (iobase);
+		if (__rdtsc () > limit) break;
+		if ((status & 2) == 0) continue;		// SMBusInterrupt not set, keep waiting
+		if ((status & 1) == 1) continue;		// HostBusy set, keep waiting
+		break;
+	}
+
+	buffer [0] = __inbyte (iobase + 5);
+	if (status == 2)				// check for done with no errors
+		status = 0;
+	return status;
+}
+
+/*---------------------------------------------------------------------------
+ *
+ * readspd - Read one or more SPD bytes from a DIMM.
+ *			Start with offset zero and read sequentially.
+ *			Optimization relies on autoincrement to avoid
+ *			sending offset for every byte.
+ *			Reads 128 bytes in 7-8 ms at 400 KHz.
+ */
+
+static UINT8 readspd (UINT16 iobase, UINT8 SmbusSlaveAddress, char *buffer, UINT16 count)
+{
+	UINT16 index;
+	UINT8 error;
+
+	/* read the first byte using offset zero */
+	error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
+	if (error) return error;
+
+	/* read the remaining bytes using auto-increment for speed */
+	for (index = 1; index < count; index++) {
+		error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
+		if (error) return error;
+	}
+
+	return 0;
+}
+
+static void writePmReg (UINT8 reg, UINT8 data)
+{
+	__outbyte (0xCD6, reg);
+	__outbyte (0xCD7, data);
+}
+
+static void setupFch (UINT16 ioBase)
+{
+	/* set up SMBUS - Set to SMBUS 0 & set base address */
+	/* For SB800 to Hudson 3 */
+	writePmReg (0x2D, ioBase >> 8);
+	writePmReg (0x2C, (ioBase & 0xe0) | 1);
+	__outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
+}
+
+AGESA_STATUS fam14_ReadSPD (UINT32 unused1, UINT32 unused2, void *infoptr)
+{
+	UINT8 spdAddress;
+	UINT16 ioBase =  SMBUS0_BASE_ADDRESS;
+	AGESA_READ_SPD_PARAMS *info = infoptr;
+	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	ROMSTAGE_CONST struct northbridge_amd_agesa_family14_config *config = dev->chip_info;
+
+	if ((dev == 0) || (config == 0))
+		return AGESA_ERROR;
+
+	if (info->SocketId     >= ARRAY_SIZE(config->spdAddrLookup      ))
+		return AGESA_ERROR;
+	if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0]   ))
+		return AGESA_ERROR;
+	if (info->DimmId       >= ARRAY_SIZE(config->spdAddrLookup[0][0]))
+		return AGESA_ERROR;
+
+	spdAddress = config->spdAddrLookup
+		[info->SocketId] [info->MemChannelId] [info->DimmId];
+
+	if (spdAddress == 0)
+		return AGESA_ERROR;
+	setupFch (ioBase);
+	return readspd (ioBase, spdAddress, (void *) info->Buffer, 128);
+}
diff --git a/src/northbridge/amd/agesa/family14/dimmSpd.h b/src/northbridge/amd/agesa/family14/dimmSpd.h
new file mode 100644
index 0000000..cc9edf8
--- /dev/null
+++ b/src/northbridge/amd/agesa/family14/dimmSpd.h
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#ifndef _DIMMSPD_H_
+#define _DIMMSPD_H_
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+fam14_ReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT void *SpdData);
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+#endif