Testers wanted for all ICH versions!
Prepare for ICH7/ICH8 SPI support by adding some debugging for all ICH* chipsets. Functionality (except printing) should be unchanged.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Index: flashrom-ich7/chipset_enable.c =================================================================== --- flashrom-ich7/chipset_enable.c (Revision 3143) +++ flashrom-ich7/chipset_enable.c (Arbeitskopie) @@ -139,8 +139,8 @@ }
/* - * See ie. page 375 of "Intel ICH7 External Design Specification" - * http://download.intel.com/design/chipsets/datashts/30701302.pdf + * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet" + * http://download.intel.com/design/chipsets/datashts/30701303.pdf */ static int enable_flash_ich(struct pci_dev *dev, const char *name, int bios_cntl) @@ -153,6 +153,10 @@ */ old = pci_read_byte(dev, bios_cntl);
+ printf("BIOS Lock Enable: %sabled, ", (old & (1 << 1)) ? "en" : "dis"); + printf("BIOS Write Enable: %sabled, ", (old & (1 << 1)) ? "en" : "dis"); + printf("BIOS_CNTL is 0x%x\n", old); + new = old | 1;
if (new == old) @@ -178,6 +182,37 @@ return enable_flash_ich(dev, name, 0xdc); }
+static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name) +{ + uint8_t old, new; + uint32_t tmp; + + /* Root Complex Base Address Register (RCBA) */ + tmp = pci_read_long(dev, 0xf0); + tmp &= 0xffffc000; + printf("Root Complex Base Address Register = 0x%x\n", tmp); + printf("GCS address = 0x%x\n", tmp + 0x3410); + /* TODO: Read the GCS */ + printf("SPIBAR = 0x%x\n", tmp + 0x3020); + /* TODO: Dump the SPI config regs */ + + old = pci_read_byte(dev, 0xdc); + printf("SPI Read Configuration: "); + new = (old >> 2) & 0x3; + switch (new) { + case 0: + case 1: + case 2: + printf("prefetching %sabled, caching %sabled, ", + (new & 0x2) ? "en" : "dis", (new & 0x1) ? "dis" : "en"); + break; + default: + printf("invalid prefetching/caching settings, "); + break; + } + return enable_flash_ich_dc(dev, name); +} + static int enable_flash_vt823x(struct pci_dev *dev, const char *name) { uint8_t val; @@ -524,13 +559,13 @@ {0x8086, 0x24d0, "Intel ICH5/ICH5R", enable_flash_ich_4e}, {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc}, {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc}, - {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich_dc}, - {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich_dc}, - {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich_dc}, - {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich_dc}, - {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich_dc}, - {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich_dc}, - {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich_dc}, + {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich_dc_spi}, + {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich_dc_spi}, + {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich_dc_spi}, + {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich_dc_spi}, + {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich_dc_spi}, + {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich_dc_spi}, + {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich_dc_spi}, {0x1106, 0x8231, "VIA VT8231", enable_flash_vt823x}, {0x1106, 0x3177, "VIA VT8235", enable_flash_vt823x}, {0x1106, 0x3227, "VIA VT8237", enable_flash_vt823x},
On Fri, Mar 14, 2008 at 02:52:25PM +0100, Carl-Daniel Hailfinger wrote:
Testers wanted for all ICH versions!
Prepare for ICH7/ICH8 SPI support by adding some debugging for all ICH* chipsets. Functionality (except printing) should be unchanged.
My laptop (Dell 1420N) has ICH8:
# lspci -nn 00:00.0 Host bridge [0600]: Intel Corporation Mobile PM965/GM965/GL960 Memory Controller Hub [8086:2a00] (rev 0c) 00:02.0 VGA compatible controller [0300]: Intel Corporation Mobile GM965/GL960 Integrated Graphics Controller [8086:2a02] (rev 0c) 00:02.1 Display controller [0380]: Intel Corporation Mobile GM965/GL960 Integrated Graphics Controller [8086:2a03] (rev 0c) 00:1a.0 USB Controller [0c03]: Intel Corporation 82801H (ICH8 Family) USB UHCI Contoller #4 [8086:2834] (rev 02) 00:1a.1 USB Controller [0c03]: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #5 [8086:2835] (rev 02) 00:1a.7 USB Controller [0c03]: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #2 [8086:283a] (rev 02) 00:1b.0 Audio device [0403]: Intel Corporation 82801H (ICH8 Family) HD Audio Controller [8086:284b] (rev 02) 00:1c.0 PCI bridge [0604]: Intel Corporation 82801H (ICH8 Family) PCI Express Port 1 [8086:283f] (rev 02) 00:1c.1 PCI bridge [0604]: Intel Corporation 82801H (ICH8 Family) PCI Express Port 2 [8086:2841] (rev 02) 00:1c.3 PCI bridge [0604]: Intel Corporation 82801H (ICH8 Family) PCI Express Port 4 [8086:2845] (rev 02) 00:1c.5 PCI bridge [0604]: Intel Corporation 82801H (ICH8 Family) PCI Express Port 6 [8086:2849] (rev 02) 00:1d.0 USB Controller [0c03]: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #1 [8086:2830] (rev 02) 00:1d.1 USB Controller [0c03]: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #2 [8086:2831] (rev 02) 00:1d.2 USB Controller [0c03]: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #3 [8086:2832] (rev 02) 00:1d.7 USB Controller [0c03]: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 [8086:2836] (rev 02) 00:1e.0 PCI bridge [0604]: Intel Corporation 82801 Mobile PCI Bridge [8086:2448] (rev f2) 00:1f.0 ISA bridge [0601]: Intel Corporation 82801HEM (ICH8M) LPC Interface Controller [8086:2815] (rev 02) 00:1f.1 IDE interface [0101]: Intel Corporation 82801HBM/HEM (ICH8M/ICH8M-E) IDE Controller [8086:2850] (rev 02) 00:1f.2 SATA controller [0106]: Intel Corporation 82801HBM/HEM (ICH8M/ICH8M-E) SATA AHCI Controller [8086:2829] (rev 02) 00:1f.3 SMBus [0c05]: Intel Corporation 82801H (ICH8 Family) SMBus Controller [8086:283e] (rev 02) 03:01.0 FireWire (IEEE 1394) [0c00]: Ricoh Co Ltd R5C832 IEEE 1394 Controller [1180:0832] (rev 05) 03:01.1 Generic system peripheral [0805]: Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter [1180:0822] (rev 22) 03:01.2 System peripheral [0880]: Ricoh Co Ltd R5C843 MMC Host Controller [1180:0843] (rev 12) 03:01.3 System peripheral [0880]: Ricoh Co Ltd R5C592 Memory Stick Bus Host Adapter [1180:0592] (rev 12) 03:01.4 System peripheral [0880]: Ricoh Co Ltd xD-Picture Card Controller [1180:0852] (rev 12) 09:00.0 Ethernet controller [0200]: Broadcom Corporation NetLink BCM5906M Fast Ethernet PCI Express [14e4:1713] (rev 02) 0c:00.0 Network controller [0280]: Intel Corporation PRO/Wireless 3945ABG Network Connection [8086:4222] (rev 02)
Your patch does not seem to do much though:
# ./flashrom -V Calibrating delay loop... 338M loops per second. OK. No coreboot table found. WARNING: No chipset found. Flash detection will most likely fail. Probing for Am29F040B, 512 KB probe_29f040b: id1 0x60, id2 0x8a Probing for Am29LV040B, 512 KB probe_29f040b: id1 0x60, id2 0x8a Probing for Am29F016D, 2048 KB probe_29f040b: id1 0xff, id2 0xff Probing for AE49F2008, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for At29C040A, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for At29C020, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for At49F002(N), 256 KB probe_jedec: id1 0x30, id2 0xc Probing for At49F002(N)T, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for EN29F002(A)(N)T, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for EN29F002(A)(N)B, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for MBM29F400TC, 512 KB probe_m29f400bt: id1 0x60, id2 0xb Probing for MX29F002, 256 KB probe_29f002: id1 0x30, id2 0xc Probing for MX25L4005, 512 KB generic_spi_command called, but no SPI chipset detected Probing for MX25L8005, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for MX25L3205, 4096 KB generic_spi_command called, but no SPI chipset detected Probing for S25FL016A, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for SST25VF040B, 512 KB generic_spi_command called, but no SPI chipset detected Probing for SST25VF016B, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for SST29EE020A, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for SST28SF040A, 512 KB probe_28sf040: id1 0x60, id2 0x8a Probing for SST39SF010A, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for SST39SF020A, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for SST39SF040, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for SST39VF020, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for SST49LF040B, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for SST49LF040, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for SST49LF020A, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for SST49LF080A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF002A/B, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for SST49LF003A/B, 384 KB probe_jedec: id1 0x3, id2 0x5 Probing for SST49LF004A/B, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for SST49LF008A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF004C, 512 KB probe_49lfxxxc: id1 0x60, id2 0x8a Probing for SST49LF008C, 1024 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST49LF016C, 2048 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST49LF160C, 2048 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for Pm49FL002, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for Pm49FL004, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for Pm25LV512, 64 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV010, 128 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV020, 256 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV040, 512 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV080B, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV016B, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for W29C011, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for W29C040P, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for W29C020C, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for W29EE011, 128 KB probe_w29ee011: id1 0xff, id2 0xff Probing for W49F002U, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for W49V002A, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for W49V002FA, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for W39V040FA, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for W39V040A, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for W39V040B, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for W39V080A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for W25x10, 128 KB generic_spi_command called, but no SPI chipset detected Probing for W25x20, 256 KB generic_spi_command called, but no SPI chipset detected Probing for W25x40, 512 KB generic_spi_command called, but no SPI chipset detected Probing for W25x80, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for M29F002B, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for M50FW040, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for M29W040B, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for M29F002T/NT, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for M29F400BT, 512 KB probe_m29f400bt: id1 0x60, id2 0xb Probing for M50FLW040A, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for M50FLW040B, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for M50FLW080A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FLW080B, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FW080, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FW016, 2048 KB probe_jedec: id1 0xff, id2 0xff Probing for M50LPW116, 2048 KB probe_jedec: id1 0xff, id2 0xff Probing for M29W010B, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for M29F040B, 512 KB probe_29f040b: id1 0x60, id2 0x8a Probing for M25P05-A, 64 KB generic_spi_command called, but no SPI chipset detected Probing for M25P10-A, 128 KB generic_spi_command called, but no SPI chipset detected Probing for M25P20, 256 KB generic_spi_command called, but no SPI chipset detected Probing for M25P40, 512 KB generic_spi_command called, but no SPI chipset detected Probing for M25P80, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for M25P16, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for M25P32, 4096 KB generic_spi_command called, but no SPI chipset detected Probing for M25P64, 8192 KB generic_spi_command called, but no SPI chipset detected Probing for M25P128, 16384 KB generic_spi_command called, but no SPI chipset detected Probing for 82802ab, 512 KB probe_82802ab: id1 0x60, id2 0x8a Probing for 82802ac, 1024 KB probe_82802ab: id1 0xff, id2 0xff Probing for F49B002UA, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for LHF00L04, 1024 KB probe_lhf00l04: id1 0xff, id2 0xff Probing for S29C51001T, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for S29C51002T, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for S29C51004T, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for S29C31004T, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for EON unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected Probing for MX unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected Probing for PMC unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected Probing for SST unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected Probing for ST unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected No EEPROM/flash device found.
Thanks, Ward.
On 14.03.2008 15:23, Ward Vandewege wrote:
On Fri, Mar 14, 2008 at 02:52:25PM +0100, Carl-Daniel Hailfinger wrote:
Testers wanted for all ICH versions!
Prepare for ICH7/ICH8 SPI support by adding some debugging for all ICH* chipsets. Functionality (except printing) should be unchanged.
My laptop (Dell 1420N) has ICH8:
# lspci -nn 00:1f.0 ISA bridge [0601]: Intel Corporation 82801HEM (ICH8M) LPC Interface Controller [8086:2815] (rev 02)
Thanks. Please try this new patch:
Index: flashrom-ich7/chipset_enable.c =================================================================== --- flashrom-ich7/chipset_enable.c (Revision 3143) +++ flashrom-ich7/chipset_enable.c (Arbeitskopie) @@ -30,6 +30,7 @@ #include <stdlib.h> #include <sys/types.h> #include <sys/stat.h> +#include <sys/mman.h> #include <fcntl.h> #include <unistd.h> #include "flash.h" @@ -139,8 +140,8 @@ }
/* - * See ie. page 375 of "Intel ICH7 External Design Specification" - * http://download.intel.com/design/chipsets/datashts/30701302.pdf + * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet" + * http://download.intel.com/design/chipsets/datashts/30701303.pdf */ static int enable_flash_ich(struct pci_dev *dev, const char *name, int bios_cntl) @@ -153,6 +154,10 @@ */ old = pci_read_byte(dev, bios_cntl);
+ printf("BIOS Lock Enable: %sabled, ", (old & (1 << 1)) ? "en" : "dis"); + printf("BIOS Write Enable: %sabled, ", (old & (1 << 1)) ? "en" : "dis"); + printf("BIOS_CNTL is 0x%x\n", old); + new = old | 1;
if (new == old) @@ -178,6 +183,44 @@ return enable_flash_ich(dev, name, 0xdc); }
+static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name) +{ + uint8_t old, new; + uint32_t tmp; + void *rcba; + + /* Root Complex Base Address Register (RCBA) */ + tmp = pci_read_long(dev, 0xf0); + tmp &= 0xffffc000; + printf("Root Complex Base Address Register = 0x%x\n", tmp); + rcba = mmap(0, 0x3510, PROT_READ, MAP_SHARED, fd_mem, (off_t)tmp); + if (rcba == MAP_FAILED) { + perror("Can't mmap memory using " MEM_DEV); + exit(1); + } + printf("GCS address = 0x%x\n", tmp + 0x3410); + printf("GCS = 0x%x\n", *(volatile uint8_t *)(rcba + 0x3410)); + printf("SPIBAR = 0x%x\n", tmp + 0x3020); + /* TODO: Dump the SPI config regs */ + munmap(rcba, 0x3510); + + old = pci_read_byte(dev, 0xdc); + printf("SPI Read Configuration: "); + new = (old >> 2) & 0x3; + switch (new) { + case 0: + case 1: + case 2: + printf("prefetching %sabled, caching %sabled, ", + (new & 0x2) ? "en" : "dis", (new & 0x1) ? "dis" : "en"); + break; + default: + printf("invalid prefetching/caching settings, "); + break; + } + return enable_flash_ich_dc(dev, name); +} + static int enable_flash_vt823x(struct pci_dev *dev, const char *name) { uint8_t val; @@ -524,13 +567,15 @@ {0x8086, 0x24d0, "Intel ICH5/ICH5R", enable_flash_ich_4e}, {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc}, {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc}, - {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich_dc}, - {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich_dc}, - {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich_dc}, - {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich_dc}, - {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich_dc}, - {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich_dc}, - {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich_dc}, + {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich_dc_spi}, + {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich_dc_spi}, + {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich_dc_spi}, + {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich_dc_spi}, + {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich_dc_spi}, + {0x8086, 0x2811, "Intel ICH8M-E", enable_flash_ich_dc_spi}, + {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich_dc_spi}, + {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich_dc_spi}, + {0x8086, 0x2815, "Intel ICH8M", enable_flash_ich_dc_spi}, {0x1106, 0x8231, "VIA VT8231", enable_flash_vt823x}, {0x1106, 0x3177, "VIA VT8235", enable_flash_vt823x}, {0x1106, 0x3227, "VIA VT8237", enable_flash_vt823x},
On Fri, Mar 14, 2008 at 03:36:47PM +0100, Carl-Daniel Hailfinger wrote:
On 14.03.2008 15:23, Ward Vandewege wrote:
On Fri, Mar 14, 2008 at 02:52:25PM +0100, Carl-Daniel Hailfinger wrote:
Testers wanted for all ICH versions!
Prepare for ICH7/ICH8 SPI support by adding some debugging for all ICH* chipsets. Functionality (except printing) should be unchanged.
My laptop (Dell 1420N) has ICH8:
# lspci -nn 00:1f.0 ISA bridge [0601]: Intel Corporation 82801HEM (ICH8M) LPC Interface Controller [8086:2815] (rev 02)
Thanks. Please try this new patch:
That's better:
# ./flashrom Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH8M", enabling flash write... Root Complex Base Address Register = 0xfed18000 GCS address = 0xfed1b410 GCS = 0x60 SPIBAR = 0xfed1b020 SPI Read Configuration: prefetching enabled, caching enabled, BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x8 OK. WARNING: size: 0 -> 4096 (page size) WARNING: size: 0 -> 4096 (page size) WARNING: size: 0 -> 4096 (page size) WARNING: size: 0 -> 4096 (page size) WARNING: size: 0 -> 4096 (page size) No EEPROM/flash device found.
Thanks, Ward.
On 14.03.2008 15:41, Ward Vandewege wrote:
On Fri, Mar 14, 2008 at 03:36:47PM +0100, Carl-Daniel Hailfinger wrote:
On 14.03.2008 15:23, Ward Vandewege wrote:
On Fri, Mar 14, 2008 at 02:52:25PM +0100, Carl-Daniel Hailfinger wrote:
Testers wanted for all ICH versions!
Prepare for ICH7/ICH8 SPI support by adding some debugging for all ICH* chipsets. Functionality (except printing) should be unchanged.
My laptop (Dell 1420N) has ICH8:
# lspci -nn 00:1f.0 ISA bridge [0601]: Intel Corporation 82801HEM (ICH8M) LPC Interface Controller [8086:2815] (rev 02)
Thanks. Please try this new patch:
That's better:
# ./flashrom Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH8M", enabling flash write... Root Complex Base Address Register = 0xfed18000 GCS address = 0xfed1b410 GCS = 0x60 SPIBAR = 0xfed1b020 SPI Read Configuration: prefetching enabled, caching enabled, BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x8 OK. WARNING: size: 0 -> 4096 (page size) WARNING: size: 0 -> 4096 (page size) WARNING: size: 0 -> 4096 (page size) WARNING: size: 0 -> 4096 (page size) WARNING: size: 0 -> 4096 (page size) No EEPROM/flash device found.
Thanks! Next try (with flashrom -V please):
Index: flashrom-ich7/chipset_enable.c =================================================================== --- flashrom-ich7/chipset_enable.c (Revision 3143) +++ flashrom-ich7/chipset_enable.c (Arbeitskopie) @@ -30,6 +30,7 @@ #include <stdlib.h> #include <sys/types.h> #include <sys/stat.h> +#include <sys/mman.h> #include <fcntl.h> #include <unistd.h> #include "flash.h" @@ -139,8 +140,8 @@ }
/* - * See ie. page 375 of "Intel ICH7 External Design Specification" - * http://download.intel.com/design/chipsets/datashts/30701302.pdf + * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet" + * http://download.intel.com/design/chipsets/datashts/30701303.pdf */ static int enable_flash_ich(struct pci_dev *dev, const char *name, int bios_cntl) @@ -153,6 +154,10 @@ */ old = pci_read_byte(dev, bios_cntl);
+ printf("BIOS Lock Enable: %sabled, ", (old & (1 << 1)) ? "en" : "dis"); + printf("BIOS Write Enable: %sabled, ", (old & (1 << 1)) ? "en" : "dis"); + printf("BIOS_CNTL is 0x%x\n", old); + new = old | 1;
if (new == old) @@ -178,6 +183,50 @@ return enable_flash_ich(dev, name, 0xdc); }
+static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name) +{ + uint8_t old, new, bbs; + uint32_t tmp, gcs; + void *rcba; + + /* Root Complex Base Address Register (RCBA) */ + tmp = pci_read_long(dev, 0xf0); + tmp &= 0xffffc000; + printf("Root Complex Base Address Register = 0x%x\n", tmp); + rcba = mmap(0, 0x3510, PROT_READ, MAP_SHARED, fd_mem, (off_t)tmp); + if (rcba == MAP_FAILED) { + perror("Can't mmap memory using " MEM_DEV); + exit(1); + } + printf("GCS address = 0x%x\n", tmp + 0x3410); + gcs = *(volatile uint32_t *)(rcba + 0x3410); + printf("GCS = 0x%x: ", gcs); + printf("BIOS Interface Lock-Down: %sabled, ", + (gcs & 0x1) ? "en" : "dis"); + bbs = (gcs >> 10) & 0x3; + printf("BOOT BIOS Straps: 0x%x (%s)\n", bbs, + (bbs == 0x3) ? "LPC" : ((bbs == 0x2) ? "PCI" : "SPI")); + printf("SPIBAR = 0x%x\n", tmp + 0x3020); + /* TODO: Dump the SPI config regs */ + munmap(rcba, 0x3510); + + old = pci_read_byte(dev, 0xdc); + printf("SPI Read Configuration: "); + new = (old >> 2) & 0x3; + switch (new) { + case 0: + case 1: + case 2: + printf("prefetching %sabled, caching %sabled, ", + (new & 0x2) ? "en" : "dis", (new & 0x1) ? "dis" : "en"); + break; + default: + printf("invalid prefetching/caching settings, "); + break; + } + return enable_flash_ich_dc(dev, name); +} + static int enable_flash_vt823x(struct pci_dev *dev, const char *name) { uint8_t val; @@ -524,13 +573,15 @@ {0x8086, 0x24d0, "Intel ICH5/ICH5R", enable_flash_ich_4e}, {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc}, {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc}, - {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich_dc}, - {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich_dc}, - {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich_dc}, - {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich_dc}, - {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich_dc}, - {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich_dc}, - {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich_dc}, + {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich_dc_spi}, + {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich_dc_spi}, + {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich_dc_spi}, + {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich_dc_spi}, + {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich_dc_spi}, + {0x8086, 0x2811, "Intel ICH8M-E", enable_flash_ich_dc_spi}, + {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich_dc_spi}, + {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich_dc_spi}, + {0x8086, 0x2815, "Intel ICH8M", enable_flash_ich_dc_spi}, {0x1106, 0x8231, "VIA VT8231", enable_flash_vt823x}, {0x1106, 0x3177, "VIA VT8235", enable_flash_vt823x}, {0x1106, 0x3227, "VIA VT8237", enable_flash_vt823x},
On Fri, Mar 14, 2008 at 04:12:58PM +0100, Carl-Daniel Hailfinger wrote:
Thanks! Next try (with flashrom -V please):
# ./flashrom -V Calibrating delay loop... 336M loops per second. OK. No coreboot table found. Found chipset "Intel ICH8M", enabling flash write... Root Complex Base Address Register = 0xfed18000 GCS address = 0xfed1b410 GCS = 0x20460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) SPIBAR = 0xfed1b020 SPI Read Configuration: prefetching enabled, caching enabled, BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x9 OK. Probing for Am29F040B, 512 KB probe_29f040b: id1 0x60, id2 0x8a Probing for Am29LV040B, 512 KB probe_29f040b: id1 0x60, id2 0x8a Probing for Am29F016D, 2048 KB probe_29f040b: id1 0xff, id2 0xff Probing for AE49F2008, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for At29C040A, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for At29C020, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for At49F002(N), 256 KB probe_jedec: id1 0x30, id2 0xc Probing for At49F002(N)T, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for EN29F002(A)(N)T, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for EN29F002(A)(N)B, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for MBM29F400TC, 512 KB probe_m29f400bt: id1 0x60, id2 0xb Probing for MX29F002, 256 KB probe_29f002: id1 0x30, id2 0xc Probing for MX25L4005, 512 KB generic_spi_command called, but no SPI chipset detected Probing for MX25L8005, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for MX25L3205, 4096 KB generic_spi_command called, but no SPI chipset detected Probing for S25FL016A, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for SST25VF040B, 512 KB generic_spi_command called, but no SPI chipset detected Probing for SST25VF016B, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for SST29EE020A, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for SST28SF040A, 512 KB probe_28sf040: id1 0x60, id2 0x8a Probing for SST39SF010A, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for SST39SF020A, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for SST39SF040, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for SST39VF020, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for SST49LF040B, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for SST49LF040, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for SST49LF020A, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for SST49LF080A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF002A/B, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for SST49LF003A/B, 384 KB probe_jedec: id1 0x3, id2 0x5 Probing for SST49LF004A/B, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for SST49LF008A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF004C, 512 KB probe_49lfxxxc: id1 0x60, id2 0x8a Probing for SST49LF008C, 1024 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST49LF016C, 2048 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST49LF160C, 2048 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for Pm49FL002, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for Pm49FL004, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for Pm25LV512, 64 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV010, 128 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV020, 256 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV040, 512 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV080B, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV016B, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for W29C011, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for W29C040P, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for W29C020C, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for W29EE011, 128 KB probe_w29ee011: id1 0xff, id2 0xff Probing for W49F002U, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for W49V002A, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for W49V002FA, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for W39V040FA, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for W39V040A, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for W39V040B, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for W39V080A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for W25x10, 128 KB generic_spi_command called, but no SPI chipset detected Probing for W25x20, 256 KB generic_spi_command called, but no SPI chipset detected Probing for W25x40, 512 KB generic_spi_command called, but no SPI chipset detected Probing for W25x80, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for M29F002B, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for M50FW040, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for M29W040B, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for M29F002T/NT, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for M29F400BT, 512 KB probe_m29f400bt: id1 0x60, id2 0xb Probing for M50FLW040A, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for M50FLW040B, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for M50FLW080A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FLW080B, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FW080, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FW016, 2048 KB probe_jedec: id1 0xff, id2 0xff Probing for M50LPW116, 2048 KB probe_jedec: id1 0xff, id2 0xff Probing for M29W010B, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for M29F040B, 512 KB probe_29f040b: id1 0x60, id2 0x8a Probing for M25P05-A, 64 KB generic_spi_command called, but no SPI chipset detected Probing for M25P10-A, 128 KB generic_spi_command called, but no SPI chipset detected Probing for M25P20, 256 KB generic_spi_command called, but no SPI chipset detected Probing for M25P40, 512 KB generic_spi_command called, but no SPI chipset detected Probing for M25P80, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for M25P16, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for M25P32, 4096 KB generic_spi_command called, but no SPI chipset detected Probing for M25P64, 8192 KB generic_spi_command called, but no SPI chipset detected Probing for M25P128, 16384 KB generic_spi_command called, but no SPI chipset detected Probing for 82802ab, 512 KB probe_82802ab: id1 0x60, id2 0x8a Probing for 82802ac, 1024 KB probe_82802ab: id1 0xff, id2 0xff Probing for F49B002UA, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for LHF00L04, 1024 KB probe_lhf00l04: id1 0xff, id2 0xff Probing for S29C51001T, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for S29C51002T, 256 KB probe_jedec: id1 0x30, id2 0xc Probing for S29C51004T, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for S29C31004T, 512 KB probe_jedec: id1 0x60, id2 0x8a Probing for EON unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected Probing for MX unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected Probing for PMC unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected Probing for SST unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected Probing for ST unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected No EEPROM/flash device found.
Thanks, Ward.
On Fri, Mar 14, 2008 at 04:12:58PM +0100, Carl-Daniel Hailfinger wrote:
Next try (with flashrom -V please):
This code detects the ICH8 chipset on my laptop, and it appears to use SPI.
Acked-by: Ward Vandewege ward@gnu.org
On 14.03.2008 16:40, Ward Vandewege wrote:
On Fri, Mar 14, 2008 at 04:12:58PM +0100, Carl-Daniel Hailfinger wrote:
Next try (with flashrom -V please):
This code detects the ICH8 chipset on my laptop, and it appears to use SPI.
Acked-by: Ward Vandewege ward@gnu.org
Thanks, r3144 with the changes Uwe requested.
Regards, Carl-Daniel
On Fri, Mar 14, 2008 at 04:12:58PM +0100, Carl-Daniel Hailfinger wrote:
That's better:
# ./flashrom Calibrating delay loop... OK. No coreboot table found.
Found chipset "Intel ICH8M", enabling flash write... Root Complex Base Address Register = 0xfed18000 GCS address = 0xfed1b410 GCS = 0x60 SPIBAR = 0xfed1b020 SPI Read Configuration: prefetching enabled, caching enabled, BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x8
Please make this additional debug output only appear when -V is used, too much information casual users shouldn't have to see.
Uwe.
On Fri, Mar 14, 2008 at 04:12:58PM +0100, Carl-Daniel Hailfinger wrote:
/*
- See ie. page 375 of "Intel ICH7 External Design Specification"
- See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
- */
static int enable_flash_ich(struct pci_dev *dev, const char *name, int bios_cntl) @@ -153,6 +154,10 @@ */ old = pci_read_byte(dev, bios_cntl);
- printf("BIOS Lock Enable: %sabled, ", (old & (1 << 1)) ? "en" : "dis");
- printf("BIOS Write Enable: %sabled, ", (old & (1 << 1)) ? "en" : "dis");
Shouldn't this be 'old & (1 << 0)'? Write enable is bit 0, lock enable is bit 1.
Uwe.
On 14.03.2008 17:50, Uwe Hermann wrote:
On Fri, Mar 14, 2008 at 04:12:58PM +0100, Carl-Daniel Hailfinger wrote:
/*
- See ie. page 375 of "Intel ICH7 External Design Specification"
- See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
- */
static int enable_flash_ich(struct pci_dev *dev, const char *name, int bios_cntl) @@ -153,6 +154,10 @@ */ old = pci_read_byte(dev, bios_cntl);
- printf("BIOS Lock Enable: %sabled, ", (old & (1 << 1)) ? "en" : "dis");
- printf("BIOS Write Enable: %sabled, ", (old & (1 << 1)) ? "en" : "dis");
Shouldn't this be 'old & (1 << 0)'? Write enable is bit 0, lock enable is bit 1.
Thanks, fixed. The checkin will also have all new printk as printk_debug (that was in my version anyway, I just forgot to send it to the list).
Regards, Carl-Daniel
-
Carl-Daniel Hailfinger -
Uwe Hermann -
Ward Vandewege