Post code 0x80

[Konstantin Lazarev]

Hello,

I am working on booting up VIA VX800 board with coreboot.
I have coreboot (r4824) stuck on POST code 0x80 (sequence was "00" -> "10" -> "80") with this board.
Could somebody please let me know where (in which source file in coreboot) this code is outputted in port 0x80?

Thank you,
Konstantin Lazarev.

[Myles Watson]

On Thu, Oct 22, 2009 at 6:29 PM, Konstantin Lazarev
wrote:
> Hello,
>
> I am working on booting up VIA VX800 board with coreboot.
> I have coreboot (r4824) stuck on POST code 0x80 (sequence was "00" -> "10"
> -> "80") with this board.
> Could somebody please let me know where (in which source file in coreboot)
> this code is outputted in port 0x80?

src/boot/hardwaremain.c, right before console_init.

Hopefully you'll quickly get to the point where you can use serial output,
it's much more informative.

Thanks,
Myles

[Uwe Hermann]

On Thu, Oct 22, 2009 at 09:04:49PM -0600, Myles Watson wrote:
> On Thu, Oct 22, 2009 at 6:29 PM, Konstantin Lazarev
> wrote:
> > Hello,
> >
> > I am working on booting up VIA VX800 board with coreboot.
> > I have coreboot (r4824) stuck on POST code 0x80 (sequence was "00" -> "10"
> > -> "80") with this board.
> > Could somebody please let me know where (in which source file in coreboot)
> > this code is outputted in port 0x80?
>
> src/boot/hardwaremain.c, right before console_init.

There's also documentation/POSTCODES which documents some of them
(probably not all) and which is probably also outdated and needs fixing.
Yay, yet another item on our TODO list :)

Uwe.

[Konstantin Lazarev]

Hi Myles,

Thank you for hint. I found this place too. Apparently it is not correct for vx800 platform.

I tried to modify this output in src/boot/hardwaremain.c to have different POST code. And I still have the same sequence "00"->''10"->"80" after complete rebuild of the image.
Ok. It looks that I need more understanding about what is the sequence of execution of coreboot.
Here is the quote from documentation/POSTCODES
----------------------------------------
0x10 Entry into protected mode
0x01 Entry into 'crt0.s' reset code jumps to here
0x11 Start copying LinuxBIOS to RAM with decompression if compressed
0x12 Copy/decompression finished jumping to RAM
0x80 Entry into LinuxBIOS in RAM
0x13 Entry into c_start
0xfe Pre call to hardwaremain()
0x39 Console is initialized
0x40 Console boot message succeeded
0x66 Devices have been enumerated
0x88 Devices have been configured
0x89 Devices have been enabled
0xf8 Entry into elf boot
0xf3 Jumping to payload
----------------------------------------

From this quote I see that boot sequence for vx800 lacks decompression/copy stages and goes directly to entry in RAM. Supposedly code 0x80 is outputted in function hardwaremain which called from c_start.S. But I see in sources that some motherboards/northbridges have their own version of hardwaremain function.  vx800 has one too. But it is in examples and looks that it is not used.

So my question is:
What is the sequence of coreboot start-up for 32-bits x86 after entry32.inc (post code 0x10). What code is executed next before hardwaremain.

Thank you,
Konstantin Lazarev.

________________________________
From: Myles Watson 
To: Konstantin Lazarev 
Cc: [e-mail]
Sent: Thursday, October 22, 2009 8:04:49 PM
Subject: Re: [coreboot] Post code 0x80

On Thu, Oct 22, 2009 at 6:29 PM, Konstantin Lazarev  wrote:

Hello,
> I am working on booting up VIA VX800 board with coreboot.
> I have coreboot (r4824) stuck on POST code 0x80 (sequence was "00" -> "10" -> "80") with this board.
> Could somebody please let me know where (in which source file in coreboot) this code is outputted in port 0x80?

src/boot/hardwaremain.c, right before console_init.

Hopefully you'll quickly get to the point where you can use serial output, it's much more informative.

Thanks,
Myles

[Myles Watson]

On Fri, Oct 23, 2009 at 11:16 AM, Konstantin Lazarev <[e-mail]
> wrote:
> Hi Myles,
>
> Thank you for hint. I found this place too. Apparently it is not correct
> for vx800 platform.
> I tried to modify this output in src/boot/hardwaremain.c to have different
> POST code. And I still have the same sequence "00"->''10"->"80" after
> complete rebuild of the image.
> Ok. It looks that I need more understanding about what is the sequence of
> execution of coreboot.
> Here is the quote from documentation/POSTCODES
>
> 0x10 Entry into protected mode
> 0x01 Entry into 'crt0.s' reset code jumps to here
> 0x11 Start copying LinuxBIOS to RAM with decompression if compressed
> 0x12 Copy/decompression finished jumping to RAM
> 0x80 Entry into LinuxBIOS in RAM

Post codes are poorly maintained.  Because debugging with the serial port is
_so_ much easier, they aren't used much except to get the serial console
working.

Do you see anything on the serial console?  There should be a lot of output
before LinuxBIOS is in RAM.

----------------------------------------
> From this quote I see that boot sequence for vx800 lacks decompression/copy
> stages and goes directly to entry in RAM.

Yeah.  That sounds bogus.
> So my question is:
> What is the sequence of coreboot start-up for 32-bits x86 after entry32.inc
> (post code 0x10). What code is executed next before hardwaremain.

I would look at
src/cpu/via/car/cache_as_ram.inc
which calls amd64_main() in
src/mainboard/via/epia-m700/cache_as_ram_auto.c

I'm not exactly sure the path it takes, but cache_as_ram.inc is very early.
Hopefully you'll be able to insert some post codes there and see them.

Thanks,
Myles

[Peter Stuge]

Konstantin Lazarev wrote:
> I am working on booting up VIA VX800 board with coreboot.

Which board are you using?

//Peter