Author: myles Date: 2008-12-31 21:02:03 +0100 (Wed, 31 Dec 2008) New Revision: 1093
Modified: coreboot-v3/mainboard/kontron/986lcd-m/dts coreboot-v3/northbridge/intel/i945/northbridge.c coreboot-v3/northbridge/intel/i945/northbridge.dts Log: This patch fixes up kontron for the new resource allocator. More could be done. northbridge/intel/i945/northbridge.dts Remove bridge flag. Northbridges don't have children. The domains they implement do. northbridge/intel/i945/northbridge.c Add IORESOURCE_BRIDGE flags and change the limit for MMIO to avoid ROM. mainboard/kontron/986lcd-m/dts Make PCI devices children of the domain and add a few devices.
Signed-off-by: Myles Watson mylesgw@gmail.com Acked-by: Ronald G. Minnich rminnich@gmail.com
Modified: coreboot-v3/mainboard/kontron/986lcd-m/dts =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/dts 2008-12-31 20:00:30 UTC (rev 1092) +++ coreboot-v3/mainboard/kontron/986lcd-m/dts 2008-12-31 20:02:03 UTC (rev 1093) @@ -145,55 +145,90 @@ }; domain@0 { /config/("northbridge/intel/i945/northbridge.dts"); - /* guesses; we need a real lspci */ - pci@0,0 { - pci@1b,0 { - /config/("southbridge/intel/i82801gx/ac97audio.dts"); - }; - pci@1c,0 { - /config/("southbridge/intel/i82801gx/pcie1.dts"); - }; - pci@1c,1 { - /config/("southbridge/intel/i82801gx/pcie2.dts"); - }; - pci@1c,2{ - /config/("southbridge/intel/i82801gx/pcie3.dts"); - }; - pci@1d,0{ - /config/("southbridge/intel/i82801gx/usb1.dts"); - }; - pci@1d,1{ - /config/("southbridge/intel/i82801gx/usb2.dts"); - }; - pci@1d,2{ - /config/("southbridge/intel/i82801gx/usb3.dts"); - }; - pci@1d,3{ - /config/("southbridge/intel/i82801gx/usb4.dts"); - }; - pci@1d,7{ - /config/("southbridge/intel/i82801gx/usb_ehci.dts"); - }; - pci@1e,0{ - /config/("southbridge/intel/i82801gx/pci.dts"); - }; - pci@1f,0{/* which ich? */ - /config/("southbridge/intel/i82801gx/ich7m_dh_lpc.dts"); - }; - pci@1f,1{ - /config/("southbridge/intel/i82801gx/ide.dts"); - }; - pci@1f,2{ - /config/("southbridge/intel/i82801gx/sata.dts"); - }; - pci@1f,3{ - /config/("southbridge/intel/i82801gx/smbus.dts"); - }; - + pci@0,0 { + /config/("northbridge/intel/i945/mc.dts"); }; - ioport@2e { - /config/("superio/winbond/w83627thg/dts"); - com1enable = "1"; + pci@1,0 { /* PCIe */ + disabled; }; + pci@2,0 { /* Onboard VGA. */ + rom_address = "0xfff00000"; /* Shouldn't this be a lar path? */ + }; + pci@2,1 { /* Display controller. */ + }; + pci@1b,0 { + /config/("southbridge/intel/i82801gx/ac97audio.dts"); + }; + pci@1c,0 { + /config/("southbridge/intel/i82801gx/pcie1.dts"); + }; + pci@1c,1 { + /config/("southbridge/intel/i82801gx/pcie2.dts"); + }; + pci@1c,2{ + /config/("southbridge/intel/i82801gx/pcie3.dts"); + }; + pci@1c,3{ disabled; }; /* PCIe port 4 */ + pci@1c,4{ disabled; }; /* PCIe port 5 */ + pci@1c,5{ disabled; }; /* PCIe port 6 */ + pci@1d,0{ + /config/("southbridge/intel/i82801gx/usb1.dts"); + }; + pci@1d,1{ + /config/("southbridge/intel/i82801gx/usb2.dts"); + }; + pci@1d,2{ + /config/("southbridge/intel/i82801gx/usb3.dts"); + }; + pci@1d,3{ + /config/("southbridge/intel/i82801gx/usb4.dts"); + }; + pci@1d,7{ + /config/("southbridge/intel/i82801gx/usb_ehci.dts"); + }; + pci@1e,0{ + /config/("southbridge/intel/i82801gx/pci.dts"); + }; + pci@1e,2{ disabled; }; /* AC'97 Audio */ + pci@1e,3{ disabled; }; /* AC'97 Modem */ + pci@1f,0{/* which ich? */ + /config/("southbridge/intel/i82801gx/ich7m_dh_lpc.dts"); + ioport@2e { + /config/("superio/winbond/w83627thg/dts"); + com1enable = "1"; + com2enable = "1"; + kbenable = "1"; + /* irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq */ + gameenable = "1"; + gpio2enable = "1"; + gpio34enable = "1"; + hwmenable = "1"; + }; + ioport@4e { + /config/("superio/winbond/w83627thg/dts"); + com1enable = "1"; + com1io = "0x3e8"; + com1irq = "11"; + com2enable = "1"; + com2io = "0x2e8"; + com2irq = "10"; + }; + }; + pci@1f,1{ /* Disabled and commented out in v2. */ + /config/("southbridge/intel/i82801gx/ide.dts"); + disabled; + }; + pci@1f,2{ + /config/("southbridge/intel/i82801gx/sata.dts"); + }; + pci@1f,3{ + /config/("southbridge/intel/i82801gx/smbus.dts"); + }; + /* Disabled and commented out in v2. + * pci@1f,4{ + * /config/("southbridge/intel/i82801gx/codec.dts"); + * disabled; + * }; + */ }; };
Modified: coreboot-v3/northbridge/intel/i945/northbridge.c =================================================================== --- coreboot-v3/northbridge/intel/i945/northbridge.c 2008-12-31 20:00:30 UTC (rev 1092) +++ coreboot-v3/northbridge/intel/i945/northbridge.c 2008-12-31 20:02:03 UTC (rev 1093) @@ -51,8 +51,8 @@ resource->align = 0; resource->gran = 0; resource->limit = 0xffffUL; - resource->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_BRIDGE;
/* Initialize the system wide memory resources constraints */ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); @@ -60,9 +60,10 @@ resource->size = 0; resource->align = 0; resource->gran = 0; - resource->limit = 0xffffffffUL; - resource->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + /* This is a hack. I don't know all the right reserved regions. */ + resource->limit = 0xfeffffffUL; + resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_BRIDGE; }
static void tolm_test(void *gp, struct device *dev, struct resource *new)
Modified: coreboot-v3/northbridge/intel/i945/northbridge.dts =================================================================== --- coreboot-v3/northbridge/intel/i945/northbridge.dts 2008-12-31 20:00:30 UTC (rev 1092) +++ coreboot-v3/northbridge/intel/i945/northbridge.dts 2008-12-31 20:02:03 UTC (rev 1093) @@ -19,4 +19,5 @@ */ { device_operations = "i945_pci_domain_ops"; + bridge; };
-
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