[commit] r5201 - in trunk/src: cpu/amd/car cpu/amd/model_10xxx cpu/amd/model_fxx include/cpu/x86 mainboard/amd/serengeti_cheetah_fam10 mainboard/msi/ms9652_fam10 mainboard/supermicro/h8dmr_fam10 ma...

[repository service]

Author: myles
Date: Thu Mar 11 22:34:27 2010
New Revision: 5201
URL: http://tracker.coreboot.org/trac/coreboot/changeset/5201

Log:
Replace clear_memory with memset.
Replace set_init_ram_access with the call to set_var_mtrr.
Remove unused #include statments.

Signed-off-by: Myles Watson 
Acked-by: Patrick Georgi

Deleted:
   trunk/src/cpu/amd/car/clear_init_ram.c
   trunk/src/include/cpu/x86/mem.h
Modified:
   trunk/src/cpu/amd/car/post_cache_as_ram.c
   trunk/src/cpu/amd/model_10xxx/init_cpus.c
   trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c
   trunk/src/cpu/amd/model_fxx/init_cpus.c
   trunk/src/cpu/amd/model_fxx/model_fxx_init.c
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
   trunk/src/mainboard/msi/ms9652_fam10/romstage.c
   trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
   trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
   trunk/src/mainboard/tyan/s2912_fam10/romstage.c
   trunk/src/northbridge/amd/amdk8/raminit.c
   trunk/src/northbridge/amd/amdk8/raminit_f.c
   trunk/src/northbridge/intel/e7520/raminit.c
   trunk/src/northbridge/intel/e7525/raminit.c
   trunk/src/northbridge/intel/i3100/raminit.c
   trunk/src/northbridge/intel/i3100/raminit_ep80579.c
   trunk/src/northbridge/intel/i945/raminit.c

Modified: trunk/src/cpu/amd/car/post_cache_as_ram.c
==============================================================================
--- trunk/src/cpu/amd/car/post_cache_as_ram.c	Wed Mar 10 04:43:05 2010	(r5200)
+++ trunk/src/cpu/amd/car/post_cache_as_ram.c	Thu Mar 11 22:34:27 2010	(r5201)
@@ -3,8 +3,6 @@
  */
 #include "cpu/amd/car/disable_cache_as_ram.c"

-#include "cpu/amd/car/clear_init_ram.c"
-
 static inline void print_debug_pcar(const char *strval, uint32_t val)
 {
         printk_debug("%s%08x\r\n", strval, val);
@@ -64,7 +62,8 @@
         #error "You need to set CONFIG_RAMTOP greater than 1M"
 #endif
    
-	set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_RAMTOP) */
+	/* So we can access RAM from [1M, CONFIG_RAMTOP) */
+	set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);

//	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x8000, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x7c00);
    print_debug("Copying data from cache to RAM -- switching to use RAM as stack... ");
@@ -94,7 +93,12 @@
    disable_cache_as_ram_bsp();

print_debug("Clearing initial memory region: ");
-        clear_init_ram(); //except the range from [(CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_RAMTOP))
+#if CONFIG_HAVE_ACPI_RESUME == 1
+	/* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
+	memset((void*) CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE, 0);
+#else
+        memset((void*)0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE), 0);
+#endif
         print_debug("Done\r\n");

//	dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);

Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c
==============================================================================
--- trunk/src/cpu/amd/model_10xxx/init_cpus.c	Wed Mar 10 04:43:05 2010	(r5200)
+++ trunk/src/cpu/amd/model_10xxx/init_cpus.c	Thu Mar 11 22:34:27 2010	(r5201)
@@ -421,7 +421,7 @@
    	 */
    	//wait_till_sysinfo_in_ram();

-		set_init_ram_access();
+		set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);

STOP_CAR_AND_CPU();
    	printk_debug("\nAP %02x should be halted but you are reading this....\n", apicid);

Modified: trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c
==============================================================================
--- trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c	Wed Mar 10 04:43:05 2010	(r5200)
+++ trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c	Thu Mar 11 22:34:27 2010	(r5201)
@@ -34,7 +34,6 @@
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
-#include <cpu/x86/mem.h>
 #include <cpu/amd/quadcore.h>
 #include <cpu/amd/model_10xxx_msr.h>

Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c
==============================================================================
--- trunk/src/cpu/amd/model_fxx/init_cpus.c	Wed Mar 10 04:43:05 2010	(r5200)
+++ trunk/src/cpu/amd/model_fxx/init_cpus.c	Thu Mar 11 22:34:27 2010	(r5201)
@@ -317,7 +317,7 @@
    		        print_initcpu8("while waiting for BSP signal to STOP, timeout in ap ", apicid);
    		}
                         lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu
-                        set_init_ram_access();
+			set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
    #if CONFIG_MEM_TRAIN_SEQ == 1
    		train_ram_on_node(id.nodeid, id.coreid, sysinfo,
    				  (unsigned) STOP_CAR_AND_CPU);

Modified: trunk/src/cpu/amd/model_fxx/model_fxx_init.c
==============================================================================
--- trunk/src/cpu/amd/model_fxx/model_fxx_init.c	Wed Mar 10 04:43:05 2010	(r5200)
+++ trunk/src/cpu/amd/model_fxx/model_fxx_init.c	Thu Mar 11 22:34:27 2010	(r5201)
@@ -24,7 +24,6 @@
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
-#include <cpu/x86/mem.h>

#include <cpu/amd/dualcore.h>

@@ -238,7 +237,7 @@

/* clear memory 2M (limitk - basek) */
                 addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10));
-                clear_memory(addr, size);
+                memset(addr, size, 0);
 }

static void init_ecc_memory(unsigned node_id)

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	Wed Mar 10 04:43:05 2010	(r5200)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	Thu Mar 11 22:34:27 2010	(r5201)
@@ -130,7 +130,6 @@
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "northbridge/amd/amdht/ht_wrapper.c"

-#include "include/cpu/x86/mem.h"
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"

Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/romstage.c	Wed Mar 10 04:43:05 2010	(r5200)
+++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c	Thu Mar 11 22:34:27 2010	(r5201)
@@ -110,7 +110,6 @@
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "northbridge/amd/amdht/ht_wrapper.c"

-#include "include/cpu/x86/mem.h"
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c	Wed Mar 10 04:43:05 2010	(r5200)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c	Thu Mar 11 22:34:27 2010	(r5201)
@@ -108,7 +108,6 @@
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "northbridge/amd/amdht/ht_wrapper.c"

-#include "include/cpu/x86/mem.h"
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"

Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c	Wed Mar 10 04:43:05 2010	(r5200)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c	Thu Mar 11 22:34:27 2010	(r5201)
@@ -108,7 +108,6 @@
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "northbridge/amd/amdht/ht_wrapper.c"

-#include "include/cpu/x86/mem.h"
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"

Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/romstage.c	Wed Mar 10 04:43:05 2010	(r5200)
+++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c	Thu Mar 11 22:34:27 2010	(r5201)
@@ -110,7 +110,6 @@
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "northbridge/amd/amdht/ht_wrapper.c"

-#include "include/cpu/x86/mem.h"
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"

Modified: trunk/src/northbridge/amd/amdk8/raminit.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/raminit.c	Wed Mar 10 04:43:05 2010	(r5200)
+++ trunk/src/northbridge/amd/amdk8/raminit.c	Thu Mar 11 22:34:27 2010	(r5201)
@@ -4,7 +4,6 @@
    2005.02 yhlu add E0 memory hole support
 */

-#include <cpu/x86/mem.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
 #include <stdlib.h>

Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/raminit_f.c	Wed Mar 10 04:43:05 2010	(r5200)
+++ trunk/src/northbridge/amd/amdk8/raminit_f.c	Thu Mar 11 22:34:27 2010	(r5201)
@@ -20,7 +20,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */

-#include <cpu/x86/mem.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/tsc.h>

Modified: trunk/src/northbridge/intel/e7520/raminit.c
==============================================================================
--- trunk/src/northbridge/intel/e7520/raminit.c	Wed Mar 10 04:43:05 2010	(r5200)
+++ trunk/src/northbridge/intel/e7520/raminit.c	Thu Mar 11 22:34:27 2010	(r5201)
@@ -18,7 +18,6 @@
  *
  */

-#include <cpu/x86/mem.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <stdlib.h>

Modified: trunk/src/northbridge/intel/e7525/raminit.c
==============================================================================
--- trunk/src/northbridge/intel/e7525/raminit.c	Wed Mar 10 04:43:05 2010	(r5200)
+++ trunk/src/northbridge/intel/e7525/raminit.c	Thu Mar 11 22:34:27 2010	(r5201)
@@ -18,7 +18,6 @@
  *
  */

-#include <cpu/x86/mem.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <stdlib.h>

Modified: trunk/src/northbridge/intel/i3100/raminit.c
==============================================================================
--- trunk/src/northbridge/intel/i3100/raminit.c	Wed Mar 10 04:43:05 2010	(r5200)
+++ trunk/src/northbridge/intel/i3100/raminit.c	Thu Mar 11 22:34:27 2010	(r5201)
@@ -19,7 +19,6 @@
  *
  */

-#include <cpu/x86/mem.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <stdlib.h>

Modified: trunk/src/northbridge/intel/i3100/raminit_ep80579.c
==============================================================================
--- trunk/src/northbridge/intel/i3100/raminit_ep80579.c	Wed Mar 10 04:43:05 2010	(r5200)
+++ trunk/src/northbridge/intel/i3100/raminit_ep80579.c	Thu Mar 11 22:34:27 2010	(r5201)
@@ -19,7 +19,6 @@
  *
  */

-#include <cpu/x86/mem.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include "raminit_ep80579.h"

Modified: trunk/src/northbridge/intel/i945/raminit.c
==============================================================================
--- trunk/src/northbridge/intel/i945/raminit.c	Wed Mar 10 04:43:05 2010	(r5200)
+++ trunk/src/northbridge/intel/i945/raminit.c	Thu Mar 11 22:34:27 2010	(r5201)
@@ -17,7 +17,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

-#include <cpu/x86/mem.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <spd.h>