Kerry She (shekairui@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/159
-gerrit
commit 5c1e35472b33b04ff018f500fd719d4b2474be5d Author: Kerry She shekairui@gmail.com Date: Thu Aug 18 18:44:00 2011 +0800
AMD SB800 southbridge update
This patch enables access to the registers of the hardware monitor logical device in the superio via isa ports 0x295/0x296. Previously this was not enabled in the SB8xx LPC device. This is required for initialisation in init_hwm() in src/superio/winbond/w83627hf/superio.c and also by OS-level sensor monitoring such as lm-sensors to access temperature, fan monitoring and control and voltage registers. asrock/e350m1 and advansus/a785e-i mainboard changes are included herein.
Change-Id: I2176885549277b335c0c41b48457d09b9b76b703 Signed-off-by: Per Hansen perh52@runbox.com Signed-off-by: Kerry She shekairui@gmail.com --- src/mainboard/advansus/a785e-i/Kconfig | 1 + src/mainboard/advansus/a785e-i/platform_cfg.h | 5 +++++ src/mainboard/asrock/e350m1/Kconfig | 1 + src/mainboard/asrock/e350m1/platform_cfg.h | 5 +++++ src/southbridge/amd/cimx/sb800/Kconfig | 4 ++++ src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 1 + src/southbridge/amd/cimx/sb800/cfg.c | 5 +++++ src/vendorcode/amd/cimx/sb800/OEM.h | 8 ++++++++ src/vendorcode/amd/cimx/sb800/SBPOR.c | 11 ++++++++++- src/vendorcode/amd/cimx/sb800/SBTYPE.h | 5 +++++ 10 files changed, 45 insertions(+), 1 deletions(-)
diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index d3d8bec..29c1c6b 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_CIMX_SB800 select SUPERIO_WINBOND_W83627HF #COM1, COM2 #select SUPERIO_FINTEK_F81216AD #COM3, COM4 + select SB_SUPERIO_HWM select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/advansus/a785e-i/platform_cfg.h b/src/mainboard/advansus/a785e-i/platform_cfg.h index 11cc504..ee68386 100644 --- a/src/mainboard/advansus/a785e-i/platform_cfg.h +++ b/src/mainboard/advansus/a785e-i/platform_cfg.h @@ -219,4 +219,9 @@ */ #define GEC_CONFIG 0
+/** + * @def SIO_HWM_BASE_ADDRESS Super IO HWM base address + */ +#define SIO_HWM_BASE_ADDRESS 0x290 + #endif diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index c60f6df..802b58f 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 select SUPERIO_WINBOND_W83627HF + select SB_SUPERIO_HWM select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h index 6e0faea..3267651 100644 --- a/src/mainboard/asrock/e350m1/platform_cfg.h +++ b/src/mainboard/asrock/e350m1/platform_cfg.h @@ -219,4 +219,9 @@ */ #define GEC_CONFIG 0
+/** + * @def SIO_HWM_BASE_ADDRESS Super IO HWM base address + */ +#define SIO_HWM_BASE_ADDRESS 0x290 + #endif diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index b5f9325..681c881 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -27,5 +27,9 @@ if SOUTHBRIDGE_AMD_CIMX_SB800 config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/cimx/sb800/bootblock.c" + +config SB_SUPERIO_HWM + bool + default n endif #SOUTHBRIDGE_AMD_CIMX_SB800
diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 89b4dc3..164a651 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -120,6 +120,7 @@ typedef union _PCI_ADDR { #define cimIrConfigDefault 0x00 // Disable #define cimSpiFastReadEnableDefault 0x01 // Enable #define cimSpiFastReadSpeedDefault 0x01 // 33 MHz +#define cimSioHwmPortEnableDefault FALSE // GPP/AB Controller #define cimNbSbGen2Default TRUE #define cimAlinkPhyPllPowerDownDefault TRUE diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 57ff718..45a460b 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -50,6 +50,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; + sb_config->BuildParameters.SioHwmBaseAddress = SIO_HWM_BASE_ADDRESS; sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; sb_config->BuildParameters.GecShadowRomBase = GEC_BASE_ADDRESS; sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; @@ -94,6 +95,10 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_SDIN_PIN; sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL;
+ /* LPC */ + /* SuperIO hardware monitor register access */ + sb_config->SioHwmPortEnable = CONFIG_SB_SUPERIO_HWM; + /* * GPP. default configure only enable port0 with 4 lanes, * configure in devicetree.cb would overwrite the default configuration diff --git a/src/vendorcode/amd/cimx/sb800/OEM.h b/src/vendorcode/amd/cimx/sb800/OEM.h index 9abea30..b38acba 100644 --- a/src/vendorcode/amd/cimx/sb800/OEM.h +++ b/src/vendorcode/amd/cimx/sb800/OEM.h @@ -87,6 +87,14 @@ #endif
/** + * SIO_HWM_BASE_ADDRESS - Super IO HWM base address + * + */ +#ifndef SIO_HWM_BASE_ADDRESS + #define SIO_HWM_BASE_ADDRESS 0x290 +#endif + +/** * SPI_BASE_ADDRESS - SPI controller (ROM) base address * */ diff --git a/src/vendorcode/amd/cimx/sb800/SBPOR.c b/src/vendorcode/amd/cimx/sb800/SBPOR.c index 33d09d6..daf13c7 100644 --- a/src/vendorcode/amd/cimx/sb800/SBPOR.c +++ b/src/vendorcode/amd/cimx/sb800/SBPOR.c @@ -144,6 +144,7 @@ sbPowerOnInit ( UINT8 cimSataMode; UINT8 cimSpiFastReadEnable; UINT8 cimSpiFastReadSpeed; + UINT8 cimSioHwmPortEnable; UINT8 SataPortNum;
cimNbSbGen2 = pConfig->NbSbGen2; @@ -155,12 +156,14 @@ sbPowerOnInit ( cimSpiFastReadEnable = cimSpiFastReadEnableDefault; } cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed; + cimSioHwmPortEnable = pConfig->SioHwmPortEnable; #if SB_CIMx_PARAMETER == 0 cimNbSbGen2 = cimNbSbGen2Default; cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default); cimSataMode = (UINT8) ((cimSataMode & 0x0F) | (cimSATARefClkSelDefault + cimSATARefDivSelDefault)); cimSpiFastReadEnable = cimSpiFastReadEnableDefault; cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault; + cimSioHwmPortEnable = cimSioHwmPortEnableDefault; #endif
// SB800 Only Enabled (Mmio_mem_enablr) // Default value is correct @@ -200,6 +203,12 @@ sbPowerOnInit (
// Set Build option into SB WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress)); + if (cimSioHwmPortEnable) { + // Use Wide IO Port 1 to provide access to the superio HWM registers. + WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG66 , AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioHwmBaseAddress)); + RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG48 + 3, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); // Wide IO Port 1: enable + RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG74 , AccWidthUint8 | S3_SAVE, 0xFF, BIT2); // set width 0:512, 1:16 bytes + } RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress)); RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1)); // Enabled SMBUS0/SMBUS1 (ASF) Base Address @@ -354,4 +363,4 @@ sbPowerOnInit (
// Set PMx88[5]to enable LdtStp# output to do the C3 or FidVid transation RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8, 0xFF, BIT5); -} \ No newline at end of file +} diff --git a/src/vendorcode/amd/cimx/sb800/SBTYPE.h b/src/vendorcode/amd/cimx/sb800/SBTYPE.h index ea3e6f6..b8278cf 100644 --- a/src/vendorcode/amd/cimx/sb800/SBTYPE.h +++ b/src/vendorcode/amd/cimx/sb800/SBTYPE.h @@ -156,6 +156,10 @@ typedef struct _BUILDPARAM { * @par * SIO PME BASE Address */ + unsigned int SioHwmBaseAddress; /**< SioHwmBaseAddress + * @par + * SIO HWM BASE Address + */ unsigned int WatchDogTimerBase; /**< WatchDogTimerBase * @par * Watch Dog Timer Address @@ -911,6 +915,7 @@ typedef struct _AMDSBCFG { unsigned int MTC1e:1; //29 /** MiscDummy - Reserved */ unsigned int MiscDummy:2; //31:30 + unsigned int SioHwmPortEnable:1; // Enable SuperIO HWM access via LPC
//DebugOptions //offset 4 bytes (146-149) /** PcibAutoClkCtrlLow - Debug function Reserved */