ohava laptop coreboot

[Sahil Sinha]

I spoke with someone in the IRC to send this here, I offered free hardware
for a port of coreboot to this machine.

Sahil Sinha
Ohava Computers
[phone]
www.ohava.com

[Stefan Reinauer]

On 9/20/10 5:26 AM, Sahil Sinha wrote:
> I spoke with someone in the IRC to send this here, I offered free 
> hardware for a port of coreboot to this machine.

Can you also provide the necessary RS-NDAed Intel data sheets for the 
chipset? (I.e. not the stuff on the public web page)

Stefan

[Sahil Sinha]

Stefan,

How would I go about doing that? Do I need to request it from
the manufacturer?

Sahil Sinha
Ohava Computers
[phone]
www.ohava.com

On Mon, Sep 20, 2010 at 6:41 AM, Stefan Reinauer <
[e-mail]> wrote:
> On 9/20/10 5:26 AM, Sahil Sinha wrote:
> > I spoke with someone in the IRC to send this here, I offered free hardware
> > for a port of coreboot to this machine.
>
> Can you also provide the necessary RS-NDAed Intel data sheets for the
> chipset? (I.e. not the stuff on the public web page)
>
> Stefan

[Peter Stuge]

Hi Sahil,

Sahil Sinha wrote:
> I spoke with someone in the IRC to send this here, I offered free
> hardware for a port of coreboot to this machine.

I'm afraid that's not really reasonable compensation when considering
the scope of the project.

Thanks for sending detailed hardware information! Let's have a look:
> [    0.134272] CPU0: Intel(R) Core(TM) i7 CPU       M 620  @ 2.67GHz stepping 02
> Found chipset "Intel HM55", enabling flash write... chipset PCI ID is 8086:3b09,

Unfortunately, neither the Nehalem architecture nor this chipset is
supported by coreboot at this point.

Implementing support for these components is possible, but it is a
major project. My guess would be 12-18 man-months, but an accurate
estimate is impossible without a pre-study involving the already
mentioned RS-NDA documentation from Intel as well as an excellent
relationship with hardware design engineers. The project itself will
also require various advanced technical debugging equipment. These
pre-requisities can all be arranged, but they are fairly significant.
> Found chip "Winbond W25x16" (2048 KB, SPI) at physical address 0xffe00000.
> Reading flash... Transaction error!
> run OPCODE 0x03 failed
> FAILED.

The above is a moderately positive indication with regard to
upgrading the flash chip from Linux using flashrom, but communication
with the chip is being blocked by the chipset. The solution during
development to apply more advanced technology; either the flash chip
is replaced completely with an emulator, or an external flash
programmer is connected onto the flash chip in the system.
> Found ITE IT8502E/TE/G (id=0x8502, rev=0x3) at 0x4e
> Found SMSC SCH5317 (id=0x85, rev=0x02) at 0x4e

These two components use the same id and the project would need to
investigate what is actually used in the hardware design, but the
superio is a very simple component compared with the CPU and chipset.
> On Mon, Sep 20, 2010 at 6:41 AM, Stefan Reinauer <
> [e-mail]> wrote:
> > Can you also provide the necessary RS-NDAed Intel data sheets for
> > the chipset? (I.e. not the stuff on the public web page)
>
> How would I go about doing that? Do I need to request it from the
> manufacturer?

RS-NDA is second level, AKA orange cover, restricted information
released by Intel only to approved individuals upon review of each
document request.

When establishing the required NDAs it is critical to clearly state
the intent of using the information to develop open source software
which will be published and distributed freely, because special terms
may need to be negotiated to permit an open workflow and/or actual
compliance of the finished work with the license used by coreboot.
(GPLv2)

I'm glad to see your interest in coreboot! :)

//Peter