New patch to review for coreboot: 06051e2 link/graphics: add functions to support aux channel communications

[Stefan Reinauer]

Stefan Reinauer ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2834

-gerrit

commit 06051e2e8f1a47379c6b186512536611f922c452
Author: Ronald G. Minnich 
Date:   Wed Feb 27 09:54:47 2013 -0800

link/graphics: add functions to support aux channel communications

For full integration of FUI into coreboot, we need aux channel
    communcations.  The intel_dp.c is a file taken from Linux and is
    used for aux channel comms.  This file has been cut down to work
    with coreboot.  For now it is associated with the link mainboard
    until we get a better handle on how this all fits together.  This
    code is almost certainly usable on other platforms in the long term.
    But one step at a time.

Change-Id: I7be4c56e0a7903f3901ac86e12b28f3bdc0f7947
    Signed-off-by: Ronald G. Minnich 
---
 src/mainboard/google/link/Makefile.inc |   1 +
 src/mainboard/google/link/i915.c       |   4 +-
 src/mainboard/google/link/i915io.c     |   2 +-
 src/mainboard/google/link/i915io.h     |  11 +++
 src/mainboard/google/link/intel_dp.c   | 165 +++++++++++++++++++++++++++++++++
 5 files changed, 180 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc
index a769d95..8fb69c6 100644
--- a/src/mainboard/google/link/Makefile.inc
+++ b/src/mainboard/google/link/Makefile.inc
@@ -23,6 +23,7 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c
 ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915io.c
+ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c

smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
 SPD_BIN = $(obj)/spd.bin
diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c
index de7c306..d6438cb 100644
--- a/src/mainboard/google/link/i915.c
+++ b/src/mainboard/google/link/i915.c
@@ -62,7 +62,7 @@ extern int oprom_is_loaded;
 #define READ32(addr) io_i915_READ32(addr)
 #define WRITE32(val, addr) io_i915_WRITE32(val, addr)

-static unsigned long io_i915_READ32(unsigned long addr)
+unsigned long io_i915_READ32(unsigned long addr)
 {
        unsigned long val;
        outl(addr, addrport);
@@ -70,7 +70,7 @@ static unsigned long io_i915_READ32(unsigned long addr)
        return val;
 }

-static void io_i915_WRITE32(unsigned long val, unsigned long addr)
+void io_i915_WRITE32(unsigned long val, unsigned long addr)
 {
        outl(addr, addrport);
        outl(val, dataport);
diff --git a/src/mainboard/google/link/i915io.c b/src/mainboard/google/link/i915io.c
index 98c73b7..5fd3d4c 100644
--- a/src/mainboard/google/link/i915io.c
+++ b/src/mainboard/google/link/i915io.c
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
-
+#include <stdint.h>
 #include "i915io.h"

struct iodef iodefs[] = {
diff --git a/src/mainboard/google/link/i915io.h b/src/mainboard/google/link/i915io.h
index 768bc7e..638d59e 100644
--- a/src/mainboard/google/link/i915io.h
+++ b/src/mainboard/google/link/i915io.h
@@ -58,3 +58,14 @@ struct iodef {
    unsigned long data;
    unsigned long udelay;
 };
+
+/* i915.c */
+unsigned long io_i915_READ32(unsigned long addr);
+void io_i915_WRITE32(unsigned long val, unsigned long addr);
+
+/* intel_dp.c */
+u32 pack_aux(u8 *src, int src_bytes);
+void unpack_aux(u32 src, u8 *dst, int dst_bytes);
+int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u8 *send, int send_bytes,
+	u8 *recv, int recv_size);
+
diff --git a/src/mainboard/google/link/intel_dp.c b/src/mainboard/google/link/intel_dp.c
new file mode 100644
index 0000000..b2160a1
--- /dev/null
+++ b/src/mainboard/google/link/intel_dp.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright 2013 Google Inc.
+ * Copyright © 2008 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Keith Packard 
+ *
+ */
+
+#include <console/console.h>
+#include <stdint.h>
+#include <delay.h>
+#include "i915io.h"
+
+u32
+pack_aux(u8 *src, int src_bytes)
+{
+	int	i;
+	u32 v = 0;
+
+	if (src_bytes > 4)
+		src_bytes = 4;
+	for (i = 0; i < src_bytes; i++)
+		v |= ((u32) src[i]) << ((3-i) * 8);
+	return v;
+}
+
+void
+unpack_aux(u32 src, u8 *dst, int dst_bytes)
+{
+	int i;
+	if (dst_bytes > 4)
+		dst_bytes = 4;
+	for (i = 0; i < dst_bytes; i++)
+		dst[i] = src >> ((3-i) * 8);
+}
+
+int
+intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u8 *send, int send_bytes,
+		u8 *recv, int recv_size)
+{
+	int i;
+	int recv_bytes;
+	u32 status;
+	u32 aux_clock_divider;
+	int try, precharge = 5;
+
+	/* The clock divider is based off the hrawclk,
+	 * and would like to run at 2MHz. So, take the
+	 * hrawclk value and divide by 2 and use that
+	 *
+	 * Note that PCH attached eDP panels should use a 125MHz input
+	 * clock divider.
+	 */
+	/* 200 on link */
+	aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
+
+	/* Try to wait for any previous AUX channel activity */
+	for (try = 0; try < 3; try++) {
+		status = io_i915_READ32(ch_ctl);
+		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
+			break;
+		udelay(1000);
+	}
+
+	if (try == 3) {
+	  printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
+	  printk(BIOS_SPEW, "dp_aux_ch not started status 0x%08lx\n",
+		  io_i915_READ32(ch_ctl));
+	  return -1;
+	}
+
+	/* Must try at least 3 times according to DP spec */
+	for (try = 0; try < 5; try++) {
+		/* Load the send data into the aux channel data registers */
+		for (i = 0; i < send_bytes; i += 4)
+			io_i915_WRITE32(ch_data + i,
+				   pack_aux(send + i, send_bytes - i));
+
+		/* Send the command and wait for it to complete */
+		io_i915_WRITE32(ch_ctl,
+			   DP_AUX_CH_CTL_SEND_BUSY |
+			   DP_AUX_CH_CTL_TIME_OUT_400us |
+			   (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
+			   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
+			   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
+			   DP_AUX_CH_CTL_DONE |
+			   DP_AUX_CH_CTL_TIME_OUT_ERROR |
+			   DP_AUX_CH_CTL_RECEIVE_ERROR);
+		for (;;) {
+			status = io_i915_READ32(ch_ctl);
+			if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
+				break;
+			udelay(100);
+		}
+
+		/* Clear done status and any errors */
+		io_i915_WRITE32(ch_ctl,
+			   status |
+			   DP_AUX_CH_CTL_DONE |
+			   DP_AUX_CH_CTL_TIME_OUT_ERROR |
+			   DP_AUX_CH_CTL_RECEIVE_ERROR);
+
+		if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
+			      DP_AUX_CH_CTL_RECEIVE_ERROR))
+			continue;
+		if (status & DP_AUX_CH_CTL_DONE)
+			break;
+	}
+
+	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
+		printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
+		printk(BIOS_SPEW, "dp_aux_ch not done status 0x%08x\n", status);
+		return -1;
+	}
+
+	/* Check for timeout or receive error.
+	 * Timeouts occur when the sink is not connected
+	 */
+	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
+		printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
+		printk(BIOS_SPEW, "dp_aux_ch receive error status 0x%08x\n", status);
+		return -1;
+	}
+
+	/* Timeouts occur when the device isn't connected, so they're
+	 * "normal" -- don't fill the kernel log with these */
+	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
+		printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
+		printk(BIOS_SPEW, "dp_aux_ch timeout status 0x%08x\n", status);
+		return -1;
+	}
+
+	/* Unload any bytes sent back from the other side */
+	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
+		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
+	if (recv_bytes > recv_size)
+		recv_bytes = recv_size;
+
+	for (i = 0; i < recv_bytes; i += 4)
+		unpack_aux(io_i915_READ32(ch_data + i),
+			   recv + i, recv_bytes - i);
+
+	return recv_bytes;
+}
+