[v2] r4856 - in trunk/coreboot-v2/src: . config console cpu/amd/car cpu/amd/model_10xxx cpu/amd/model_fxx cpu/amd/socket_AM2r2 cpu/amd/socket_F_1207 mainboard/amd/serengeti_cheetah mainboard/amd/serengeti_cheetah_fam10 mainboard/asus/a8n_e mainboard/digitallogic/adl855pc mainboard/digitallogic/msm586seg mainboard/gigabyte/ga_2761gxdk mainboard/gigabyte/m57sli mainboard/msi/ms7135 mainboard/msi/ms7260 mainboard/msi/ms9282 mainboard/nvidia/l1_2pvv mainboard/supermicro/h8dme mainboard/supermicro/h8d
Author: myles Date: 2009-10-26 16:14:07 +0100 (Mon, 26 Oct 2009) New Revision: 4856
Modified: trunk/coreboot-v2/src/Kconfig trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/console/Kconfig trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c trunk/coreboot-v2/src/cpu/amd/model_10xxx/Kconfig trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig trunk/coreboot-v2/src/cpu/amd/model_fxx/init_cpus.c trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Config.lb trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Kconfig trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Config.lb trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Kconfig trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c trunk/coreboot-v2/src/mainboard/asus/a8n_e/Kconfig trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Kconfig trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Kconfig trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Kconfig trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig trunk/coreboot-v2/src/mainboard/msi/ms7135/Kconfig trunk/coreboot-v2/src/mainboard/msi/ms7260/Kconfig trunk/coreboot-v2/src/mainboard/msi/ms9282/Kconfig trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c trunk/coreboot-v2/src/mainboard/technexion/tim8690/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s1846/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2880/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2881/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2882/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2885/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2912/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb trunk/coreboot-v2/src/northbridge/amd/amdfam10/Kconfig trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig Log: Define some variables that were not defined. There are a couple left. Do kbuildall then grep not.defined kbuildall.results/* The interesting ones were GENERATE_* I had to put them in twice to make it work correctly: once outside the menu setting the defaults, and once inside the menu. Now they show up when they should, and are always defined
Define HAVE_INIT_TIMER to only exclude the three boards that define it to be 0 in newconfig. Define MEM_TRAIN_SEQ to be an integer and set it correctly. Remove CAR_FAM10 and just depend on NORTHBRIDGE_AMD_AMDFAM10 MOVNTI is a performance enhancement, and should default to 0 so it doesn't break boards that forget to define it.
Signed-off-by: Myles Watson mylesgw@gmail.com Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: trunk/coreboot-v2/src/Kconfig =================================================================== --- trunk/coreboot-v2/src/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -74,10 +74,6 @@ int default 36
-config AGP_APERTURE_SIZE - hex - default 0x0 - config XIP_ROM_BASE hex default 0xfffe0000 @@ -181,7 +177,7 @@
config HAVE_INIT_TIMER bool - default n + default y
config HAVE_MAINBOARD_RESOURCES bool @@ -189,7 +185,7 @@
config HAVE_MOVNTI bool - default y + default n
config HAVE_OPTION_TABLE bool @@ -216,6 +212,7 @@ default n
config VIDEO_MB + default 0 int
config USE_WATCHDOG_ON_BOOT @@ -230,6 +227,7 @@
config GFXUMA bool + default n help Enable Unified Memory Architecture for graphics.
@@ -238,6 +236,27 @@ # # endmenu
+#TODO Remove this option or make it useful. +config HAVE_LOW_TABLES + bool + default y + help + This Option is unused in the code. Since two boards try to set it to + 'n', they may be broken. We either need to make the option useful or + get rid of it. The broken boards are: + asus/m2v-mx_se + supermicro/h8dme + +config HAVE_HIGH_TABLES + bool + default n + help + This variable specifies whether a given northbridge has high table + support. + It is set in northbridge/*/Kconfig. + Whether or not the high tables are actually written by coreboot is + configurable by the user via WRITE_HIGH_TABLES. + config HAVE_ACPI_TABLES bool help @@ -262,16 +281,28 @@ Whether or not the PIRQ table is actually generated by coreboot is configurable by the user via GENERATE_PIRQ_TABLE.
-config HAVE_HIGH_TABLES +#These Options are here to avoid "undefined" warnings. +#The actual selection and help texts are in the following menu. + +config GENERATE_ACPI_TABLES bool + default HAVE_ACPI_TABLES
-menu "System tables" +config GENERATE_MP_TABLE + bool + default HAVE_MP_TABLE
-config HAVE_LOW_TABLES +config GENERATE_PIRQ_TABLE bool - default y + default HAVE_PIRQ_TABLE
config WRITE_HIGH_TABLES + bool + default HAVE_HIGH_TABLES + +menu "System tables" + +config WRITE_HIGH_TABLES bool "Write 'high' tables to avoid being overwritten in F segment" depends on HAVE_HIGH_TABLES default y @@ -409,3 +440,16 @@ config LIFT_BSP_APIC_ID bool default n + +# These probably belong somewhere else, but they are needed somewhere. +config AP_CODE_IN_CAR + bool + default n + +config USE_INIT + bool + default n + +config ENABLE_APIC_EXT_ID + bool + default n
Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/config/Options.lb 2009-10-26 15:14:07 UTC (rev 4856) @@ -299,11 +299,6 @@ export always comment "Use data cache as temporary RAM if possible" end -define CONFIG_CAR_FAM10 - default 0 - export always - comment "AMD family 10 CAR requires additional setup" -end define CONFIG_DCACHE_RAM_BASE default 0xc0000 format "0x%x"
Modified: trunk/coreboot-v2/src/console/Kconfig =================================================================== --- trunk/coreboot-v2/src/console/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/console/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -275,3 +275,14 @@
endmenu
+config CONSOLE_BTEXT + bool + default n + +config CONSOLE_SROM + bool + default n + +config CONSOLE_LOGBUF + bool + default n
Modified: trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc 2009-10-26 15:14:07 UTC (rev 4856) @@ -24,7 +24,7 @@ /* leave some space for global variable to pass to RAM stage */ #define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-/* for CONFIG_CAR_FAM10 */ +/* for CAR with FAM10 */ #define CacheSizeAPStack 0x400 /* 1K */
#define MSR_FAM10 0xC001102A
Modified: trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c 2009-10-26 15:14:07 UTC (rev 4856) @@ -103,9 +103,6 @@
// dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
-#ifndef CONFIG_MEM_TRAIN_SEQ -#define CONFIG_MEM_TRAIN_SEQ 0 -#endif set_sysinfo_in_ram(1); // So other core0 could start to train mem
#if CONFIG_MEM_TRAIN_SEQ == 1
Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -1,6 +1,5 @@ config CPU_AMD_MODEL_10XXX bool - select HAVE_INIT_TIMER select HAVE_MOVNTI select USE_PRINTK_IN_CAR select USE_DCACHE_RAM
Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c 2009-10-26 15:14:07 UTC (rev 4856) @@ -306,11 +306,6 @@ stop_this_cpu(); }
- -#ifndef CONFIG_MEM_TRAIN_SEQ -#define CONFIG_MEM_TRAIN_SEQ 0 -#endif - #if RAMINIT_SYSINFO == 1 static u32 init_cpus(u32 cpu_init_detectedx ,struct sys_info *sysinfo) #else @@ -478,8 +473,8 @@ /* Enable routing table */ printk_debug("Start node %02x", node);
-#if CONFIG_CAR_FAM10 == 1 - /* For CONFIG_CAR_FAM10 support, we need to set Dram base/limit for the new node */ +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 + /* For FAM10 support, we need to set Dram base/limit for the new node */ pci_write_config32(NODE_MP(node), 0x44, 0); pci_write_config32(NODE_MP(node), 0x40, 3); #endif
Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -1,6 +1,5 @@ config CPU_AMD_MODEL_FXX bool - select HAVE_INIT_TIMER select HAVE_MOVNTI select USE_PRINTK_IN_CAR select USE_DCACHE_RAM
Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/init_cpus.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/init_cpus.c 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/init_cpus.c 2009-10-26 15:14:07 UTC (rev 4856) @@ -215,11 +215,6 @@ stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp .... }
-#ifndef CONFIG_MEM_TRAIN_SEQ -#define CONFIG_MEM_TRAIN_SEQ 0 -#endif - - #if CONFIG_MEM_TRAIN_SEQ == 1 static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall); #endif
Modified: trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Config.lb 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Config.lb 2009-10-26 15:14:07 UTC (rev 4856) @@ -27,7 +27,6 @@ uses CONFIG_CBB uses CONFIG_CDB uses CONFIG_PCI_BUS_SEGN_BITS -uses CONFIG_CAR_FAM10
config chip.h
@@ -39,8 +38,6 @@ default CONFIG_DIMM_SUPPORT=0x0104 #DDR2 and REG default CONFIG_CPU_SOCKET_TYPE=0x11
-default CONFIG_CAR_FAM10=1 - if CONFIG_EXT_RT_TBL_SUPPORT default CONFIG_CBB=0xff default CONFIG_CDB=0
Modified: trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -2,7 +2,6 @@ bool select CPU_AMD_MODEL_10XXX select HT3_SUPPORT - select CAR_FAM10
config CPU_SOCKET_TYPE hex
Modified: trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Config.lb 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Config.lb 2009-10-26 15:14:07 UTC (rev 4856) @@ -27,7 +27,6 @@ uses CONFIG_CBB uses CONFIG_CDB uses CONFIG_PCI_BUS_SEGN_BITS -uses CONFIG_CAR_FAM10
config chip.h
@@ -39,8 +38,6 @@ default CONFIG_DIMM_SUPPORT=0x0104 #DDR2 and REG default CONFIG_CPU_SOCKET_TYPE=0x10
-default CONFIG_CAR_FAM10=1 - if CONFIG_EXT_RT_TBL_SUPPORT default CONFIG_CBB=0xff default CONFIG_CDB=0
Modified: trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -2,7 +2,6 @@ bool select CPU_AMD_MODEL_10XXX select PCI_IO_CFG_EXT - select CAR_FAM10
config CPU_SOCKET_TYPE hex
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -14,7 +14,6 @@ select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select AP_CODE_IN_CAR select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT @@ -81,6 +80,11 @@ default n depends on BOARD_AMD_SERENGETI_CHEETAH
+config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_AMD_SERENGETI_CHEETAH + config SB_HT_CHAIN_ON_BUS0 int default 2
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -67,6 +67,11 @@ default n depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
+config MEM_TRAIN_SEQ + int + default 2 + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + config SB_HT_CHAIN_ON_BUS0 int default 2
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-10-26 15:14:07 UTC (rev 4856) @@ -111,7 +111,6 @@ uses CONFIG_AMDMCT
uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_CAR_FAM10 uses CONFIG_AMD_UCODE_PATCH_FILE
###
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c 2009-10-26 15:14:07 UTC (rev 4856) @@ -49,7 +49,7 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -87,7 +87,7 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CAR with FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -34,6 +34,11 @@ default 0x10 depends on BOARD_ASUS_A8N_E
+config MEM_TRAIN_SEQ + int + default 2 + depends on BOARD_ASUS_A8N_E + config SB_HT_CHAIN_ON_BUS0 int default 2
Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -24,3 +24,8 @@ int default 5 depends on BOARD_DIGITALLOGIC_ADL855PC + +config HAVE_INIT_TIMER + bool + default n + depends on BOARD_DIGITALLOGIC_ADL855PC
Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -20,3 +20,7 @@ default 2 depends on BOARD_DIGITALLOGIC_MSM586SEG
+config HAVE_INIT_TIMER + bool + default n + depends on BOARD_DIGITALLOGIC_MSM586SEG
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -12,7 +12,6 @@ select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 @@ -42,6 +41,11 @@ default 16 depends on BOARD_GIGABYTE_GA_2761GXDK
+config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_GIGABYTE_GA_2761GXDK + config SB_HT_CHAIN_ON_BUS0 int default 2
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -14,7 +14,6 @@ select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select HAVE_ACPI_TABLES select K8_REV_F_SUPPORT @@ -45,6 +44,11 @@ default 16 depends on BOARD_GIGABYTE_M57SLI
+config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_GIGABYTE_M57SLI + config SB_HT_CHAIN_ON_BUS0 int default 2
Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -22,6 +22,11 @@ default 0x10 depends on BOARD_MSI_MS7135
+config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_MSI_MS7135 + config SB_HT_CHAIN_ON_BUS0 int default 2 @@ -52,11 +57,6 @@ default 0x100000 depends on BOARD_MSI_MS7135
-config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_MSI_MS7135 - config MAX_CPUS int default 2 @@ -67,11 +67,6 @@ default 1 depends on BOARD_MSI_MS7135
-config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_MSI_MS7135 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n
Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -13,7 +13,6 @@ select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 @@ -43,6 +42,11 @@ default 16 depends on BOARD_MSI_MS7260
+config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_MSI_MS7260 + config SB_HT_CHAIN_ON_BUS0 int default 2
Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -12,7 +12,6 @@ select USE_DCACHE_RAM select HAVE_HARD_RESET select IOAPIC - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512
Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -13,7 +13,6 @@ select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 @@ -43,6 +42,11 @@ default 16 depends on BOARD_NVIDIA_L1_2PVV
+config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_NVIDIA_L1_2PVV + config SB_HT_CHAIN_ON_BUS0 int default 2
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -41,6 +41,11 @@ default 0x10 depends on BOARD_SUPERMICRO_H8DME
+config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_SUPERMICRO_H8DME + config SB_HT_CHAIN_ON_BUS0 int default 2
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -40,6 +40,11 @@ default 0x10 depends on BOARD_SUPERMICRO_H8DMR
+config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_SUPERMICRO_H8DMR + config SB_HT_CHAIN_ON_BUS0 int default 2
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -41,6 +41,11 @@ default 0x10 depends on BOARD_SUPERMICRO_H8DMR_FAM10
+config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + config SB_HT_CHAIN_ON_BUS0 int default 2
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb 2009-10-26 15:14:07 UTC (rev 4856) @@ -114,7 +114,6 @@ uses CONFIG_AMDMCT
uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_CAR_FAM10 uses CONFIG_AMD_UCODE_PATCH_FILE
###
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c 2009-10-26 15:14:07 UTC (rev 4856) @@ -49,7 +49,7 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR_FAM10 + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -88,7 +88,7 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR_FAM10 + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -13,7 +13,6 @@ select USE_DCACHE_RAM select HAVE_HARD_RESET select IOAPIC - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES
Modified: trunk/coreboot-v2/src/mainboard/tyan/s1846/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s1846/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s1846/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -43,9 +43,3 @@ bool default n depends on BOARD_TYAN_S1846 - -#Override manually, as in Config.lb (FIXME) -config IRQ_SLOT_COUNT - int - default 0 - depends on BOARD_TYAN_S1846
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2880/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s2880/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -51,11 +51,6 @@ default 0x100000 depends on BOARD_TYAN_S2880
-config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2880 - config MAX_CPUS int default 4 @@ -66,11 +61,6 @@ default 2 depends on BOARD_TYAN_S2880
-config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2880 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -51,11 +51,6 @@ default 0x100000 depends on BOARD_TYAN_S2881
-config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2881 - config MAX_CPUS int default 4 @@ -66,11 +61,6 @@ default 2 depends on BOARD_TYAN_S2881
-config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2881 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2882/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s2882/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -51,11 +51,6 @@ default 0x100000 depends on BOARD_TYAN_S2882
-config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2882 - config MAX_CPUS int default 4 @@ -66,11 +61,6 @@ default 2 depends on BOARD_TYAN_S2882
-config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2882 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -51,11 +51,6 @@ default 0x100000 depends on BOARD_TYAN_S2885
-config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2885 - config MAX_CPUS int default 4 @@ -66,11 +61,6 @@ default 2 depends on BOARD_TYAN_S2885
-config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2885 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -53,11 +53,6 @@ default 0x100000 depends on BOARD_TYAN_S2891
-config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2891 - config MAX_CPUS int default 4 @@ -68,11 +63,6 @@ default 2 depends on BOARD_TYAN_S2891
-config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2891 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -53,11 +53,6 @@ default 0x100000 depends on BOARD_TYAN_S2892
-config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2892 - config MAX_CPUS int default 4 @@ -68,11 +63,6 @@ default 2 depends on BOARD_TYAN_S2892
-config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2892 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -53,11 +53,6 @@ default 0x100000 depends on BOARD_TYAN_S2895
-config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2895 - config MAX_CPUS int default 4 @@ -68,11 +63,6 @@ default 2 depends on BOARD_TYAN_S2895
-config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2895 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -13,7 +13,6 @@ select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 @@ -43,6 +42,11 @@ default 16 depends on BOARD_TYAN_S2912
+config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_TYAN_S2912 + config SB_HT_CHAIN_ON_BUS0 int default 2
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -13,7 +13,6 @@ select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID @@ -44,6 +43,11 @@ default 16 depends on BOARD_TYAN_S2912_FAM10
+config MEM_TRAIN_SEQ + int + default 2 + depends on BOARD_TYAN_S2912_FAM10 + config SB_HT_CHAIN_ON_BUS0 int default 2
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb 2009-10-26 15:14:07 UTC (rev 4856) @@ -114,7 +114,6 @@ uses CONFIG_AMDMCT
uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_CAR_FAM10 uses CONFIG_AMD_UCODE_PATCH_FILE
###
Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -21,11 +21,35 @@ bool select HAVE_HIGH_TABLES select HYPERTRANSPORT_PLUGIN_SUPPORT - select HT3_SUPPORT
config AGP_APERTURE_SIZE hex default 0x4000000 depends on NORTHBRIDGE_AMD_AMDFAM10
+config HT3_SUPPORT + bool + default y + depends on NORTHBRIDGE_AMD_AMDFAM10 + +config AMDMCT + bool + default y + depends on NORTHBRIDGE_AMD_AMDFAM10 + +config MEM_TRAIN_SEQ + int + default 0 + depends on NORTHBRIDGE_AMD_AMDFAM10 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on NORTHBRIDGE_AMD_AMDFAM10 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on NORTHBRIDGE_AMD_AMDFAM10 + source src/northbridge/amd/amdfam10/root_complex/Kconfig
Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -32,4 +32,19 @@ default n depends on NORTHBRIDGE_AMD_AMDK8
+config MEM_TRAIN_SEQ + int + default 0 + depends on NORTHBRIDGE_AMD_AMDK8 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on NORTHBRIDGE_AMD_AMDK8 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on NORTHBRIDGE_AMD_AMDK8 + source src/northbridge/amd/amdk8/root_complex/Kconfig
-
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