5 Feb
2008
5 Feb
'08
12:27 a.m.
ron minnich wrote:
Why can't we shadow?
We could.
If we never write to the ROM space, at all, why not put the changed cache settings in right BEFORE we jump to the payload? i.e. don't change it to "slow" mode until we no longer need it cached?
I think that this would be ok. Maybe a generic call pre_payload() before the payload is run. I think that this would be a good genreic call for mainboard customization, like hardware_stage1(). It does mean that there will be duplicate code for each Geode platform.
I was working on a patch but it grows the size of the bootblock. It was only a few bytes too large but I grew it from 16KB to 20KB. I know we don't expect the bootblock to change much but should is be mainboard specific?
I'm still hitting the PCI device problem so I have only tested that it builds and the ROM is being cached. I can't get to the cache disable portion.
Marc
--
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones@amd.com
http://www.amd.com/embeddedprocessors
Cache the ROM to speed up stage2 and payload decompression.
Due to some cache coherency snoop problems across PCI GeodeLc needs the ROM cache properties to be write-serialize + cache disabled by runtime.
Add pre_payload() call to each mainboard as the final coreboot function before the payload is called.
Signed-off by: Marc Jones marc.jones@amd.com
Index: coreboot-v3/northbridge/amd/geodelx/geodelxinit.c
===================================================================
--- coreboot-v3.orig/northbridge/amd/geodelx/geodelxinit.c 2008-02-04 13:35:52.000000000 -0700
+++ coreboot-v3/northbridge/amd/geodelx/geodelxinit.c 2008-02-04 13:36:12.000000000 -0700
@@ -658,7 +658,7 @@
#define SYSMEM_RCONF_WRITETHROUGH 8
#define DEVRC_RCONF_DEFAULT 0x21
#define ROMBASE_RCONF_DEFAULT 0xFFFC0000
-#define ROMRC_RCONF_DEFAULT 0x25
+#define ROMRC_RCONF_DEFAULT 0x04
/**
* TODO.
Index: coreboot-v3/mainboard/adl/msm800sev/stage1.c
===================================================================
--- coreboot-v3.orig/mainboard/adl/msm800sev/stage1.c 2008-02-04 15:41:14.000000000 -0700
+++ coreboot-v3/mainboard/adl/msm800sev/stage1.c 2008-02-04 15:50:04.000000000 -0700
@@ -53,3 +53,15 @@
cs5536_disable_internal_uart();
w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE);
}
+
+void pre_payload(void)
+{
+ struct msr msr;
+
+ /* Set ROM cache properties for runtime. */
+ msr = rdmsr(CPU_RCONF_DEFAULT);
+ msr.hi &= ~(0xFF << 24); // clear ROMRC
+ msr.hi |= 0x25 << 24; // set WS, CD, WP
+ wrmsr(CPU_RCONF_DEFAULT, msr);
+ banner(BIOS_DEBUG, "pre_payload: done");
+}
Index: coreboot-v3/mainboard/amd/norwich/stage1.c
===================================================================
--- coreboot-v3.orig/mainboard/amd/norwich/stage1.c 2008-02-04 15:40:11.000000000 -0700
+++ coreboot-v3/mainboard/amd/norwich/stage1.c 2008-02-04 15:50:04.000000000 -0700
@@ -46,3 +46,15 @@
*/
cs5536_setup_onchipuart();
}
+
+void pre_payload(void)
+{
+ struct msr msr;
+
+ /* Set ROM cache properties for runtime. */
+ msr = rdmsr(CPU_RCONF_DEFAULT);
+ msr.hi &= ~(0xFF << 24); // clear ROMRC
+ msr.hi |= 0x25 << 24; // set WS, CD, WP
+ wrmsr(CPU_RCONF_DEFAULT, msr);
+ banner(BIOS_DEBUG, "pre_payload: done");
+}
Index: coreboot-v3/mainboard/artecgroup/dbe61/stage1.c
===================================================================
--- coreboot-v3.orig/mainboard/artecgroup/dbe61/stage1.c 2008-02-04 15:40:28.000000000 -0700
+++ coreboot-v3/mainboard/artecgroup/dbe61/stage1.c 2008-02-04 15:50:04.000000000 -0700
@@ -61,3 +61,15 @@
*/
cs5536_setup_onchipuart();
}
+
+void pre_payload(void)
+{
+ struct msr msr;
+
+ /* Set ROM cache properties for runtime. */
+ msr = rdmsr(CPU_RCONF_DEFAULT);
+ msr.hi &= ~(0xFF << 24); // clear ROMRC
+ msr.hi |= 0x25 << 24; // set WS, CD, WP
+ wrmsr(CPU_RCONF_DEFAULT, msr);
+ banner(BIOS_DEBUG, "pre_payload: done");
+}
Index: coreboot-v3/mainboard/emulation/qemu-x86/stage1.c
===================================================================
--- coreboot-v3.orig/mainboard/emulation/qemu-x86/stage1.c 2008-02-04 15:41:00.000000000 -0700
+++ coreboot-v3/mainboard/emulation/qemu-x86/stage1.c 2008-02-04 15:41:49.000000000 -0700
@@ -30,3 +30,8 @@
void disable_car(void)
{
}
+
+
+void pre_payload(void)
+{
+}
Index: coreboot-v3/mainboard/pcengines/alix1c/stage1.c
===================================================================
--- coreboot-v3.orig/mainboard/pcengines/alix1c/stage1.c 2008-02-04 15:40:40.000000000 -0700
+++ coreboot-v3/mainboard/pcengines/alix1c/stage1.c 2008-02-04 15:57:31.000000000 -0700
@@ -49,3 +49,14 @@
w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE);
}
+
+void pre_payload(void)
+{
+ struct msr msr;
+
+ /* Set ROM cache properties for runtime. */
+ msr = rdmsr(CPU_RCONF_DEFAULT);
+ msr.hi &= ~(0xFF << 24); // clear ROMRC
+ msr.hi |= 0x25 << 24; // set WS, CD, WP
+ wrmsr(CPU_RCONF_DEFAULT, msr);
+}
Index: coreboot-v3/arch/x86/stage1.c
===================================================================
--- coreboot-v3.orig/arch/x86/stage1.c 2008-02-04 15:31:57.000000000 -0700
+++ coreboot-v3/arch/x86/stage1.c 2008-02-04 15:33:16.000000000 -0700
@@ -37,6 +37,7 @@
void die(const char *msg);
void hardware_stage1(void);
void disable_car(void);
+void pre_payload(void);
static void stop_ap(void)
{
@@ -177,11 +178,13 @@
legacy(&archive, "normal/payload", (void *)UNCOMPRESS_AREA, mem);
entry = load_file_segments(&archive, "normal/payload");
- if (entry != (void*)-1)
+ if (entry != (void*)-1) {
+ /* Final coreboot call before handing off to the payload. */
+ pre_payload();
run_address(entry);
- else
+ } else {
die("FATAL: No usable payload found.\n");
-
+ }
die ("FATAL: Last stage returned to coreboot.\n");
}
Index: coreboot-v3/arch/x86/Makefile
===================================================================
--- coreboot-v3.orig/arch/x86/Makefile 2008-02-04 16:13:28.000000000 -0700
+++ coreboot-v3/arch/x86/Makefile 2008-02-04 16:20:11.000000000 -0700
@@ -157,7 +157,7 @@
$(Q)$(OBJCOPY) --prefix-symbols=stage0_ $(obj)/stage0.o $(obj)/stage0-prefixed.o
$(Q)printf " TEST $(subst $(shell pwd)/,,$(@))\n"
- $(Q)test `wc -c < $(obj)/stage0.init` -gt 16128 && \
+ $(Q)test `wc -c < $(obj)/stage0.init` -gt 20224 && \
printf "Error. Bootblock got too big.\n" || true
$(Q)printf " NM $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(NM) $(obj)/stage0.o | sort -u > $(obj)/stage0.init.map
Index: coreboot-v3/arch/x86/ldscript.ld
===================================================================
--- coreboot-v3.orig/arch/x86/ldscript.ld 2008-02-04 16:00:01.000000000 -0700
+++ coreboot-v3/arch/x86/ldscript.ld 2008-02-04 16:02:20.000000000 -0700
@@ -28,7 +28,7 @@
TARGET(binary)
SECTIONS
{
- . = 0xffffc000 + 256; /* leave space for vpd */
+ . = 0xffffb000 + 256; /* leave space for vpd */
.stage0_1 . : {
_stage0_1 = .;
Index: coreboot-v3/util/lar/lar.h
===================================================================
--- coreboot-v3.orig/util/lar/lar.h 2008-02-04 16:05:50.000000000 -0700
+++ coreboot-v3/util/lar/lar.h 2008-02-04 16:07:29.000000000 -0700
@@ -52,7 +52,7 @@
#define MAGIC "LARCHIVE"
#define MAX_PATHLEN 1024
-#define BOOTBLOCK_SIZE 16384
+#define BOOTBLOCK_SIZE 20480
#define BOOTBLOCK_NAME "bootblock"
#define BOOTBLOCK_NAME_LEN 16