Hi,
attached patch disables failover for K8 based boards and makes them use the more usual fallback/normal style. Fam10h requires some reduction in size, or other tricks as the ROM part exceeds 64k (the original ROM mapping) by just a bit. I'll work on that soon.
The {HAVE,USE}_FAILOVER stuff still stays in the code itself as it might be useful as a reference (ie. what is strictly necessary to configure ROM mapping) for later work.
Signed-off-by: Patrick Georgi patrick.georgi@coresystems.de
Patrick
Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah/Config.lb +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb @@ -1,6 +1,6 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah/Options.lb +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb @@ -107,7 +107,7 @@ default CONFIG_ROM_SIZE=524288 ##
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT
#more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -116,7 +116,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0
## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/asus/a8n_e/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/asus/a8n_e/Config.lb +++ coreboot-v2/src/mainboard/asus/a8n_e/Config.lb @@ -23,7 +23,7 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end driver mainboard.o Index: coreboot-v2/src/mainboard/asus/a8n_e/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/asus/a8n_e/Options.lb +++ coreboot-v2/src/mainboard/asus/a8n_e/Options.lb @@ -102,9 +102,9 @@ uses CONFIG_USE_PRINTK_IN_CAR default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 - CONFIG_FAILOVER_SIZE default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_FAILOVER_SIZE = 4 * 1024 +default CONFIG_FAILOVER_SIZE = 4 * 1024 * CONFIG_HAVE_FAILOVER_BOOT default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_HAVE_FAILOVER_BOOT = 1 +default CONFIG_HAVE_FAILOVER_BOOT = 0 default CONFIG_HAVE_HARD_RESET = 1 default CONFIG_HAVE_PIRQ_TABLE = 1 default CONFIG_IRQ_SLOT_COUNT = 13 Index: coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c @@ -70,7 +70,6 @@ #include <cpu/amd/model_fxx_rev.h>
#include "southbridge/sis/sis966/sis966_early_smbus.c" -#include "southbridge/sis/sis966/sis966_enable_rom.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" Index: coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/gigabyte/ga_2761gxdk/Config.lb +++ coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb @@ -23,7 +23,7 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/gigabyte/ga_2761gxdk/Options.lb +++ coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb @@ -135,7 +135,7 @@ default CONFIG_ROM_SIZE=524288 #FALLBACK: 256K-4K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT
#more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -144,7 +144,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0
## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/gigabyte/m57sli/Config.lb +++ coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb @@ -21,7 +21,7 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/gigabyte/m57sli/Options.lb +++ coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb @@ -136,7 +136,7 @@ default CONFIG_ROM_SIZE=524288 #FALLBACK: 256K-4K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT
#more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -150,7 +150,7 @@ default CONFIG_HAVE_FANCTL=1 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0
## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/iwill/dk8_htx/Config.lb +++ coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb @@ -1,6 +1,6 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/iwill/dk8_htx/Options.lb +++ coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb @@ -109,7 +109,7 @@ default CONFIG_ROM_SIZE=524288 #FALLBACK: 256K-8K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 8K -default CONFIG_FAILOVER_SIZE=0x02000 +default CONFIG_FAILOVER_SIZE=0x02000 * CONFIG_HAVE_FAILOVER_BOOT
#more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -118,7 +118,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0
## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/msi/ms7135/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms7135/Config.lb +++ coreboot-v2/src/mainboard/msi/ms7135/Config.lb @@ -24,7 +24,7 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/msi/ms7135/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms7135/Options.lb +++ coreboot-v2/src/mainboard/msi/ms7135/Options.lb @@ -115,7 +115,7 @@ default CONFIG_ROM_SIZE=(512*1024) default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
#FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=(4*1024) +default CONFIG_FAILOVER_SIZE=(4*1024) * CONFIG_HAVE_FAILOVER_BOOT
### ### Build options @@ -125,7 +125,7 @@ default CONFIG_FAILOVER_SIZE=(4*1024) ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0
## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/msi/ms7260/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms7260/Config.lb +++ coreboot-v2/src/mainboard/msi/ms7260/Config.lb @@ -20,7 +20,7 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/msi/ms7260/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms7260/Options.lb +++ coreboot-v2/src/mainboard/msi/ms7260/Options.lb @@ -102,10 +102,10 @@ uses CONFIG_USE_PRINTK_IN_CAR
default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_FAILOVER_SIZE = 4 * 1024 +default CONFIG_FAILOVER_SIZE = 4 * 1024 * CONFIG_HAVE_FAILOVER_BOOT default CONFIG_LB_MEM_TOPK = 2048 # 1MB more for pgtbl. default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_HAVE_FAILOVER_BOOT = 1 +default CONFIG_HAVE_FAILOVER_BOOT = 0 default CONFIG_HAVE_HARD_RESET = 1 default CONFIG_HAVE_PIRQ_TABLE = 1 default CONFIG_IRQ_SLOT_COUNT = 11 # TODO: Check if correct. Index: coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/nvidia/l1_2pvv/Config.lb +++ coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb @@ -21,7 +21,7 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/nvidia/l1_2pvv/Options.lb +++ coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb @@ -133,7 +133,7 @@ default CONFIG_ROM_SIZE=524288 #FALLBACK: 256K-4K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT
#more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -142,7 +142,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0
## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/h8dme/Config.lb +++ coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb @@ -18,7 +18,7 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/h8dme/Options.lb +++ coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb @@ -137,7 +137,7 @@ default CONFIG_MULTIBOOT=0 #FALLBACK: 256K-4K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT
#more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -146,7 +146,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0
## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/h8dmr/Config.lb +++ coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb @@ -21,7 +21,7 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/h8dmr/Options.lb +++ coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb @@ -130,7 +130,7 @@ default CONFIG_ROM_SIZE=0x100000 ## default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT
#more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -139,7 +139,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0
## ## Build code to reset the motherboard from coreboot @@ -252,7 +252,7 @@ default CONFIG_MAINBOARD_PCI_SUBSYSTEM_D ###
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 0xf000 +default CONFIG_ROM_IMAGE_SIZE = 0x10000 - CONFIG_FAILOVER_SIZE
## Index: coreboot-v2/src/mainboard/tyan/s2895/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2895/Config.lb +++ coreboot-v2/src/mainboard/tyan/s2895/Config.lb @@ -1,6 +1,6 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/tyan/s2895/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2895/Options.lb +++ coreboot-v2/src/mainboard/tyan/s2895/Options.lb @@ -95,7 +95,7 @@ default CONFIG_ROM_SIZE=1024*1024 #FALLBACK: 256K-4K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT
#more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -104,7 +104,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0
## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/tyan/s2912/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2912/Config.lb +++ coreboot-v2/src/mainboard/tyan/s2912/Config.lb @@ -21,7 +21,7 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/tyan/s2912/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2912/Options.lb +++ coreboot-v2/src/mainboard/tyan/s2912/Options.lb @@ -133,7 +133,7 @@ default CONFIG_ROM_SIZE=524288 #FALLBACK: 256K-4K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT
#more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -142,7 +142,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0
## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/amd/serengeti_cheetah/Config-abuild.lb +++ coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/asus/a8n_e/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/asus/a8n_e/Config-abuild.lb +++ coreboot-v2/targets/asus/a8n_e/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/gigabyte/ga_2761gxdk/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/gigabyte/ga_2761gxdk/Config-abuild.lb +++ coreboot-v2/targets/gigabyte/ga_2761gxdk/Config-abuild.lb @@ -45,13 +45,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE - option COREBOOT_EXTRA_VERSION=".0-Failover" -end - - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/gigabyte/m57sli/Config-abuild.lb +++ coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/iwill/dk8_htx/Config-abuild.lb +++ coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/msi/ms7135/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/msi/ms7135/Config-abuild.lb +++ coreboot-v2/targets/msi/ms7135/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/msi/ms7260/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/msi/ms7260/Config-abuild.lb +++ coreboot-v2/targets/msi/ms7260/Config-abuild.lb @@ -42,13 +42,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE = 1 - option CONFIG_USE_FALLBACK_IMAGE = 0 - option CONFIG_ROM_IMAGE_SIZE = CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE = CONFIG_FAILOVER_SIZE - option COREBOOT_EXTRA_VERSION = ".0Failover" -end - -# buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/nvidia/l1_2pvv/Config-abuild.lb +++ coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/supermicro/h8dme/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/supermicro/h8dme/Config-abuild.lb +++ coreboot-v2/targets/supermicro/h8dme/Config-abuild.lb @@ -24,12 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE - option COREBOOT_EXTRA_VERSION=".0-failover" -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/supermicro/h8dmr/Config-abuild.lb +++ coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb @@ -21,10 +21,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option COREBOOT_EXTRA_VERSION=".0-failover" -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/tyan/s2895/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/tyan/s2895/Config-abuild.lb +++ coreboot-v2/targets/tyan/s2895/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/tyan/s2912/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/tyan/s2912/Config-abuild.lb +++ coreboot-v2/targets/tyan/s2912/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"