Re: [coreboot] Run PCI rom before PCI bus scan??

I think I figured out what is going on here. According to this doc:

http://www.intel.com/design/network/applnots/ap417.pdf

ICHx Integrated LAN Controller Function Disable and Power Control for  
Fast Ethernet

I think what this is saying is the Lan Enable is controlled by a  
signal from either a Super I/O GPIO, ICHx Resume-well GPIO, or  
micro-controller output. The signal is sent to the LAN_RST# pin on the  
ICH4.

To test this theory, I disabled the Lan in the original bios and  
rebooted. It does the exact same thing that coreboot is currently  
doing???

So I guess now I need to figure out where the signal is coming from??  
Can anyone shed some light on this?

Thanks - Joe