Author: oxygene Date: Sun Nov 21 15:38:24 2010 New Revision: 6104 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6104
Log: Move MCP55_PCI_E_X_* to Kconfig. Any useless values in romstage.cs were not brought over to Kconfig (this applies to all #defines to 4, as that's the default anyway)
Signed-off-by: Patrick Georgi patrick@georgi-clan.de Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: trunk/src/mainboard/gigabyte/m57sli/Kconfig trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/msi/ms7260/Kconfig trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9652_fam10/Kconfig trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/Kconfig trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/tyan/s2912/Kconfig trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/Kconfig trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/southbridge/nvidia/mcp55/Kconfig trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
Modified: trunk/src/mainboard/gigabyte/m57sli/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/Kconfig Sun Nov 21 12:36:03 2010 (r6103) +++ trunk/src/mainboard/gigabyte/m57sli/Kconfig Sun Nov 21 15:38:24 2010 (r6104) @@ -95,4 +95,8 @@ int default 11
+config MCP55_PCI_E_X_0 + int + default 0 + endif # BOARD_GIGABYTE_M57SLI
Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Sun Nov 21 12:36:03 2010 (r6103) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Sun Nov 21 15:38:24 2010 (r6104) @@ -76,8 +76,6 @@ return smbus_read_byte(device, address); }
-#define MCP55_PCI_E_X_0 0 - #define MCP55_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \
Modified: trunk/src/mainboard/msi/ms7260/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms7260/Kconfig Sun Nov 21 12:36:03 2010 (r6103) +++ trunk/src/mainboard/msi/ms7260/Kconfig Sun Nov 21 15:38:24 2010 (r6104) @@ -93,4 +93,8 @@ int default 11
+config MCP55_PCI_E_X_0 + int + default 0 + endif # BOARD_MSI_MS7260
Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Sun Nov 21 12:36:03 2010 (r6103) +++ trunk/src/mainboard/msi/ms7260/romstage.c Sun Nov 21 15:38:24 2010 (r6104) @@ -76,8 +76,6 @@ #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c"
-#define MCP55_PCI_E_X_0 0 - #define MCP55_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/Kconfig Sun Nov 21 12:36:03 2010 (r6103) +++ trunk/src/mainboard/msi/ms9652_fam10/Kconfig Sun Nov 21 15:38:24 2010 (r6104) @@ -192,4 +192,8 @@ bool default y
+config MCP55_PCI_E_X_0 + int + default 1 + endif # BOARD_MSI_MS9652_FAM10
Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Sun Nov 21 12:36:03 2010 (r6103) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Sun Nov 21 15:38:24 2010 (r6104) @@ -78,8 +78,6 @@
#include "cpu/amd/quadcore/quadcore.c"
-#define MCP55_PCI_E_X_0 1 - #define MCP55_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
Modified: trunk/src/mainboard/nvidia/l1_2pvv/Kconfig ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/Kconfig Sun Nov 21 12:36:03 2010 (r6103) +++ trunk/src/mainboard/nvidia/l1_2pvv/Kconfig Sun Nov 21 15:38:24 2010 (r6104) @@ -97,4 +97,8 @@ int default 11
+config MCP55_PCI_E_X_0 + int + default 2 + endif # BOARD_NVIDIA_L1_2PVV
Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Sun Nov 21 12:36:03 2010 (r6103) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Sun Nov 21 15:38:24 2010 (r6104) @@ -86,9 +86,6 @@
#include "cpu/amd/dualcore/dualcore.c"
-#define MCP55_PCI_E_X_0 2 -#define MCP55_PCI_E_X_1 4 - #define MCP55_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Sun Nov 21 12:36:03 2010 (r6103) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Sun Nov 21 15:38:24 2010 (r6104) @@ -141,8 +141,6 @@
#include "cpu/amd/dualcore/dualcore.c"
-#define MCP55_PCI_E_X_0 4 - #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Sun Nov 21 12:36:03 2010 (r6103) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Sun Nov 21 15:38:24 2010 (r6104) @@ -86,8 +86,6 @@
#include "cpu/amd/dualcore/dualcore.c"
-#define MCP55_PCI_E_X_0 4 - #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Sun Nov 21 12:36:03 2010 (r6103) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Sun Nov 21 15:38:24 2010 (r6104) @@ -79,8 +79,6 @@
#include "cpu/amd/quadcore/quadcore.c"
-#define MCP55_PCI_E_X_0 4 - #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Sun Nov 21 12:36:03 2010 (r6103) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Sun Nov 21 15:38:24 2010 (r6104) @@ -82,8 +82,6 @@
#include "cpu/amd/quadcore/quadcore.c"
-#define MCP55_PCI_E_X_0 4 - #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
Modified: trunk/src/mainboard/tyan/s2912/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2912/Kconfig Sun Nov 21 12:36:03 2010 (r6103) +++ trunk/src/mainboard/tyan/s2912/Kconfig Sun Nov 21 15:38:24 2010 (r6104) @@ -88,4 +88,8 @@ int default 11
+config MCP55_PCI_E_X_0 + int + default 1 + endif # BOARD_TYAN_S2912
Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Sun Nov 21 12:36:03 2010 (r6103) +++ trunk/src/mainboard/tyan/s2912/romstage.c Sun Nov 21 15:38:24 2010 (r6104) @@ -86,8 +86,6 @@
#include "cpu/amd/dualcore/dualcore.c"
-#define MCP55_PCI_E_X_0 1 - #define MCP55_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
Modified: trunk/src/mainboard/tyan/s2912_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/Kconfig Sun Nov 21 12:36:03 2010 (r6103) +++ trunk/src/mainboard/tyan/s2912_fam10/Kconfig Sun Nov 21 15:38:24 2010 (r6104) @@ -105,4 +105,8 @@ hex default 0xc0000
+config MCP55_PCI_E_X_0 + int + default 1 + endif # BOARD_TYAN_S2912_FAM10
Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Sun Nov 21 12:36:03 2010 (r6103) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Sun Nov 21 15:38:24 2010 (r6104) @@ -79,8 +79,6 @@
#include "cpu/amd/quadcore/quadcore.c"
-#define MCP55_PCI_E_X_0 1 - #define MCP55_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
Modified: trunk/src/southbridge/nvidia/mcp55/Kconfig ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/Kconfig Sun Nov 21 12:36:03 2010 (r6103) +++ trunk/src/southbridge/nvidia/mcp55/Kconfig Sun Nov 21 15:38:24 2010 (r6104) @@ -3,26 +3,46 @@ select HAVE_USBDEBUG select IOAPIC
+if SOUTHBRIDGE_NVIDIA_MCP55 + config ID_SECTION_OFFSET hex - default 0x80 if SOUTHBRIDGE_NVIDIA_MCP55 + default 0x80
config EHCI_BAR hex - default 0xfef00000 if SOUTHBRIDGE_NVIDIA_MCP55 + default 0xfef00000
config EHCI_DEBUG_OFFSET hex - default 0x98 if SOUTHBRIDGE_NVIDIA_MCP55 + default 0x98
config MCP55_USE_NIC bool - default n if SOUTHBRIDGE_NVIDIA_MCP55 + default n
config MCP55_USE_AZA bool - default n if SOUTHBRIDGE_NVIDIA_MCP55 + default n
config MCP55_NUM int - default 1 if SOUTHBRIDGE_NVIDIA_MCP55 + default 1 + +config MCP55_PCI_E_X_0 + int + default 4 + +config MCP55_PCI_E_X_1 + int + default 4 + +config MCP55_PCI_E_X_2 + int + default 4 + +config MCP55_PCI_E_X_3 + int + default 4 + +endif
Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Sun Nov 21 12:36:03 2010 (r6103) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Sun Nov 21 15:38:24 2010 (r6104) @@ -76,19 +76,6 @@ 8 0 4 4 4 8 :5 */
-#ifndef MCP55_PCI_E_X_0 - #define MCP55_PCI_E_X_0 4 -#endif -#ifndef MCP55_PCI_E_X_1 - #define MCP55_PCI_E_X_1 4 -#endif -#ifndef MCP55_PCI_E_X_2 - #define MCP55_PCI_E_X_2 4 -#endif -#ifndef MCP55_PCI_E_X_3 - #define MCP55_PCI_E_X_3 4 -#endif - #define MCP55_CHIP_REV 3
static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base) @@ -370,7 +357,7 @@ FIXME: May have problem if there is different MCP55 HTX card with different PCI_E lane allocation Need to use same trick about pci1234 to verify node/link connection */ - unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {MCP55_PCI_E_X_0, MCP55_PCI_E_X_1, MCP55_PCI_E_X_2, MCP55_PCI_E_X_3 }; + unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {CONFIG_MCP55_PCI_E_X_0, CONFIG_MCP55_PCI_E_X_1, CONFIG_MCP55_PCI_E_X_2, CONFIG_MCP55_PCI_E_X_3 }; int mcp55_num = 0; unsigned busnx; unsigned devnx;