Author: rminnich Date: 2008-02-27 06:27:51 +0100 (Wed, 27 Feb 2008) New Revision: 622
Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c coreboot-v3/mainboard/artecgroup/dbe62/initram.c coreboot-v3/mainboard/pcengines/alix1c/initram.c Log: Convert all boards using fake SPD entries to struct spd_entry, thereby making sure we return 0xff for nonexisiting entries and shrinking the data structure by 85%. As a bonus, the various initram.c for boards with fake SPD are now almost identical.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Tested on Alix1c, with minor mods to get it to compile. Full boot to Linux, with graphics.
Acked-by: Ronald G. Minnich rminnich@gmail.com
Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-02-25 22:56:08 UTC (rev 621) +++ coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-02-27 05:27:51 UTC (rev 622) @@ -55,41 +55,59 @@ * Lead Free (P) * DDR400 3-3-3 (D43) */ -/* SPD array */ -static const u8 spdbytes[] = { - [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10, - [SPD_BANK_DENSITY] = 0x40, - [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff, - [SPD_MEMORY_TYPE] = 7, - [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */ - [SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */ - [SPD_NUM_BANKS_PER_SDRAM] = 4, - [SPD_PRIMARY_SDRAM_WIDTH] = 8, - [SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */ - [SPD_NUM_COLUMNS] = 0xa, - [SPD_NUM_ROWS] = 3, - [SPD_REFRESH] = 0x3a, - [SPD_SDRAM_CYCLE_TIME_2ND] = 60, - [SPD_SDRAM_CYCLE_TIME_3RD] = 75, - [SPD_tRAS] = 40, - [SPD_tRCD] = 15, - [SPD_tRFC] = 70, - [SPD_tRP] = 15, - [SPD_tRRD] = 10, + +struct spd_entry { + u8 address; + u8 data; };
+/* Save space by using a short list of SPD values used by Geode LX Memory init */ +static const struct spd_entry spd_table[] = { + {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, + {SPD_BANK_DENSITY, 0x40}, + {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff}, + {SPD_MEMORY_TYPE, 7}, + {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */ + {SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */ + {SPD_NUM_BANKS_PER_SDRAM, 4}, + {SPD_PRIMARY_SDRAM_WIDTH, 8}, + {SPD_NUM_DIMM_BANKS, 1}, /* ALIX1.C is 1 bank. */ + {SPD_NUM_COLUMNS, 0xa}, + {SPD_NUM_ROWS, 3}, + {SPD_REFRESH, 0x3a}, + {SPD_SDRAM_CYCLE_TIME_2ND, 60}, + {SPD_SDRAM_CYCLE_TIME_3RD, 75}, + {SPD_tRAS, 40}, + {SPD_tRCD, 15}, + {SPD_tRFC, 70}, + {SPD_tRP, 15}, + {SPD_tRRD, 10}, +}; + +/** + * Given an SMBUS device, and an address in that device, return the value of SPD + * for that device. In this mainboard, the only one that can return is DIMM0. + * @param device The device number + * @param address The address in SPD rom to return the value of + * @returns The value + */ u8 spd_read_byte(u16 device, u8 address) { + int i; + /* returns 0xFF on any failures */ + u8 ret = 0xff; + printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device); - - if (device != (0x50 << 1)) { - printk(BIOS_DEBUG, " returns 0xff\n"); - return 0xff; + if (device == DIMM0) { + for (i = 0; i < ARRAY_SIZE(spd_table); i++) { + if (spd_table[i].address == address) { + ret = spd_table[i].data; + } + } }
- printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbytes[address]); - - return spdbytes[address]; + printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, ret); + return ret; }
/**
Modified: coreboot-v3/mainboard/artecgroup/dbe62/initram.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/initram.c 2008-02-25 22:56:08 UTC (rev 621) +++ coreboot-v3/mainboard/artecgroup/dbe62/initram.c 2008-02-27 05:27:51 UTC (rev 622) @@ -45,36 +45,35 @@ * @ 200 ns, data-out window, 1.6; access, +- 70 ns; dqs-dq skew: .4ns * http://www.micron.com/products/partdetail?part=MT46V16M16P-5B */ + struct spd_entry { u8 address; u8 data; };
/* Save space by using a short list of SPD values used by Geode LX Memory init */ - -static const struct spd_entry spdbytes[] = { - {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, - {SPD_BANK_DENSITY, 0x40}, - {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff}, - {SPD_MEMORY_TYPE, 7}, - {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10, /* A guess for the tRAC value */ - {SPD_MODULE_ATTRIBUTES, 0xff, /* FIXME later when we figure out. */ - {SPD_NUM_BANKS_PER_SDRAM, 4}, - {SPD_PRIMARY_SDRAM_WIDTH, 8}, - {SPD_NUM_DIMM_BANKS, 1}, - {SPD_NUM_COLUMNS, 0xa}, - {SPD_NUM_ROWS, 3}, - {SPD_REFRESH, 0x3a}, - {SPD_SDRAM_CYCLE_TIME_2ND, 60}, - {SPD_SDRAM_CYCLE_TIME_3RD, 75}, - {SPD_tRAS, 40}, - {SPD_tRCD, 15}, - {SPD_tRFC, 70}, - {SPD_tRP, 15}, - {SPD_tRRD, 10, +static const struct spd_entry spd_table[] = { + {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, + {SPD_BANK_DENSITY, 0x40}, + {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff}, + {SPD_MEMORY_TYPE, 7}, + {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */ + {SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */ + {SPD_NUM_BANKS_PER_SDRAM, 4}, + {SPD_PRIMARY_SDRAM_WIDTH, 8}, + {SPD_NUM_DIMM_BANKS, 1}, + {SPD_NUM_COLUMNS, 0xa}, + {SPD_NUM_ROWS, 3}, + {SPD_REFRESH, 0x3a}, + {SPD_SDRAM_CYCLE_TIME_2ND, 60}, + {SPD_SDRAM_CYCLE_TIME_3RD, 75}, + {SPD_tRAS, 40}, + {SPD_tRCD, 15}, + {SPD_tRFC, 70}, + {SPD_tRP, 15}, + {SPD_tRRD, 10}, };
- /** * Given an SMBUS device, and an address in that device, return the value of SPD * for that device. In this mainboard, the only one that can return is DIMM0. @@ -82,16 +81,16 @@ * @param address The address in SPD rom to return the value of * @returns The value */ -static u8 spd_read_byte(u16 device, u8 address) +u8 spd_read_byte(u16 device, u8 address) { int i; /* returns 0xFF on any failures */ u8 ret = 0xff;
printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device); - if (device == DIMM0){ - for (i=0; i < (sizeof spd_table/sizeof spd_table[0]); i++){ - if (spd_table[i].address == address){ + if (device == DIMM0) { + for (i = 0; i < ARRAY_SIZE(spd_table); i++) { + if (spd_table[i].address == address) { ret = spd_table[i].data; } }
Modified: coreboot-v3/mainboard/pcengines/alix1c/initram.c =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/initram.c 2008-02-25 22:56:08 UTC (rev 621) +++ coreboot-v3/mainboard/pcengines/alix1c/initram.c 2008-02-27 05:27:51 UTC (rev 622) @@ -55,41 +55,59 @@ * Lead Free (P) * DDR400 3-3-3 (D43) */ -/* SPD array */ -static const u8 spdbytes[] = { - [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10, - [SPD_BANK_DENSITY] = 0x40, - [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff, - [SPD_MEMORY_TYPE] = 7, - [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */ - [SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */ - [SPD_NUM_BANKS_PER_SDRAM] = 4, - [SPD_PRIMARY_SDRAM_WIDTH] = 8, - [SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */ - [SPD_NUM_COLUMNS] = 0xa, - [SPD_NUM_ROWS] = 3, - [SPD_REFRESH] = 0x3a, - [SPD_SDRAM_CYCLE_TIME_2ND] = 60, - [SPD_SDRAM_CYCLE_TIME_3RD] = 75, - [SPD_tRAS] = 40, - [SPD_tRCD] = 15, - [SPD_tRFC] = 70, - [SPD_tRP] = 15, - [SPD_tRRD] = 10, + +struct spd_entry { + u8 address; + u8 data; };
+/* Save space by using a short list of SPD values used by Geode LX Memory init */ +static const struct spd_entry spd_table[] = { + {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, + {SPD_BANK_DENSITY, 0x40}, + {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff}, + {SPD_MEMORY_TYPE, 7}, + {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */ + {SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */ + {SPD_NUM_BANKS_PER_SDRAM, 4}, + {SPD_PRIMARY_SDRAM_WIDTH, 8}, + {SPD_NUM_DIMM_BANKS, 1}, /* ALIX1.C is 1 bank. */ + {SPD_NUM_COLUMNS, 0xa}, + {SPD_NUM_ROWS, 3}, + {SPD_REFRESH, 0x3a}, + {SPD_SDRAM_CYCLE_TIME_2ND, 60}, + {SPD_SDRAM_CYCLE_TIME_3RD, 75}, + {SPD_tRAS, 40}, + {SPD_tRCD, 15}, + {SPD_tRFC, 70}, + {SPD_tRP, 15}, + {SPD_tRRD, 10}, +}; + +/** + * Given an SMBUS device, and an address in that device, return the value of SPD + * for that device. In this mainboard, the only one that can return is DIMM0. + * @param device The device number + * @param address The address in SPD rom to return the value of + * @returns The value + */ u8 spd_read_byte(u16 device, u8 address) { + int i; + /* returns 0xFF on any failures */ + u8 ret = 0xff; + printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device); - - if (device != (0x50 << 1)) { - printk(BIOS_DEBUG, " returns 0xff\n"); - return 0xff; + if (device == DIMM0) { + for (i = 0; i < ARRAY_SIZE(spd_table); i++) { + if (spd_table[i].address == address) { + ret = spd_table[i].data; + } + } }
- printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbytes[address]); - - return spdbytes[address]; + printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, ret); + return ret; }
/**