Author: stepan Date: Wed May 26 01:06:42 2010 New Revision: 5589 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5589
Log: Move CS5535 specific setup from GX2 driver to CS5535.
To apply this patch you need to cp src/northbridge/amd/gx2/chipsetinit.c src/southbridge/amd/cs5535/
Signed-off-by: Stefan Reinauer stepan@coresystems.de Acked-by: Nils Jacobs njacobs8@hetnet.nl
Added: trunk/src/southbridge/amd/cs5535/chipsetinit.c - copied, changed from r5546, trunk/src/northbridge/amd/gx2/chipsetinit.c Deleted: trunk/src/northbridge/amd/gx2/chipsetinit.c Modified: trunk/src/mainboard/amd/rumba/devicetree.cb trunk/src/mainboard/lippert/frontrunner/devicetree.cb trunk/src/mainboard/olpc/btest/devicetree.cb trunk/src/mainboard/olpc/rev_a/devicetree.cb trunk/src/mainboard/wyse/s50/devicetree.cb trunk/src/northbridge/amd/gx2/Makefile.inc trunk/src/northbridge/amd/gx2/chip.h trunk/src/northbridge/amd/gx2/northbridge.c trunk/src/northbridge/amd/gx2/northbridge.h trunk/src/southbridge/amd/cs5535/Makefile.inc trunk/src/southbridge/amd/cs5535/chip.h trunk/src/southbridge/amd/cs5536/cs5536.c
Modified: trunk/src/mainboard/amd/rumba/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/rumba/devicetree.cb Tue May 25 19:09:05 2010 (r5588) +++ trunk/src/mainboard/amd/rumba/devicetree.cb Wed May 26 01:06:42 2010 (r5589) @@ -1,5 +1,4 @@ chip northbridge/amd/gx2 - register "setupflash" = "0" #register "irqmap" = "0xaa5b" device lapic_cluster 0 on chip cpu/amd/model_gx2
Modified: trunk/src/mainboard/lippert/frontrunner/devicetree.cb ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/devicetree.cb Tue May 25 19:09:05 2010 (r5588) +++ trunk/src/mainboard/lippert/frontrunner/devicetree.cb Wed May 26 01:06:42 2010 (r5589) @@ -1,9 +1,15 @@ chip northbridge/amd/gx2 - register "setupflash" = "0" + device lapic_cluster 0 on + chip cpu/amd/model_gx2 + device lapic 0 on end + end + end + #register "irqmap" = "0xaa5b" device pci_domain 0 on device pci 0.0 on end chip southbridge/amd/cs5535 + register "setupflash" = "0" device pci 12.0 on device pci 12.1 off end # SMI device pci 12.2 on end # IDE @@ -12,9 +18,5 @@ end end end - - chip cpu/amd/model_gx2 - end - end
Modified: trunk/src/mainboard/olpc/btest/devicetree.cb ============================================================================== --- trunk/src/mainboard/olpc/btest/devicetree.cb Tue May 25 19:09:05 2010 (r5588) +++ trunk/src/mainboard/olpc/btest/devicetree.cb Wed May 26 01:06:42 2010 (r5589) @@ -1,6 +1,5 @@ chip northbridge/amd/gx2 register "irqmap" = "0xaa5b" - register "setupflash" = "0" device lapic_cluster 0 on chip cpu/amd/model_gx2 device lapic 0 on end
Modified: trunk/src/mainboard/olpc/rev_a/devicetree.cb ============================================================================== --- trunk/src/mainboard/olpc/rev_a/devicetree.cb Tue May 25 19:09:05 2010 (r5588) +++ trunk/src/mainboard/olpc/rev_a/devicetree.cb Wed May 26 01:06:42 2010 (r5589) @@ -1,6 +1,5 @@ chip northbridge/amd/gx2 register "irqmap" = "0xaa5b" - register "setupflash" = "0" device lapic_cluster 0 on chip cpu/amd/model_gx2 device lapic 0 on end
Modified: trunk/src/mainboard/wyse/s50/devicetree.cb ============================================================================== --- trunk/src/mainboard/wyse/s50/devicetree.cb Tue May 25 19:09:05 2010 (r5588) +++ trunk/src/mainboard/wyse/s50/devicetree.cb Wed May 26 01:06:42 2010 (r5589) @@ -21,7 +21,7 @@
chip northbridge/amd/gx2 register "irqmap" = "0xaa5b" - register "setupflash" = "0" + device lapic_cluster 0 on chip cpu/amd/model_gx2 device lapic 0 on end
Modified: trunk/src/northbridge/amd/gx2/Makefile.inc ============================================================================== --- trunk/src/northbridge/amd/gx2/Makefile.inc Tue May 25 19:09:05 2010 (r5588) +++ trunk/src/northbridge/amd/gx2/Makefile.inc Wed May 26 01:06:42 2010 (r5589) @@ -1,4 +1,3 @@ driver-y += northbridge.o obj-y += northbridgeinit.o -obj-y += chipsetinit.o obj-y += grphinit.o
Modified: trunk/src/northbridge/amd/gx2/chip.h ============================================================================== --- trunk/src/northbridge/amd/gx2/chip.h Tue May 25 19:09:05 2010 (r5588) +++ trunk/src/northbridge/amd/gx2/chip.h Wed May 26 01:06:42 2010 (r5589) @@ -1,7 +1,6 @@ struct northbridge_amd_gx2_config { uint16_t irqmap; - int setupflash; };
extern struct chip_operations northbridge_amd_gx2_ops;
Modified: trunk/src/northbridge/amd/gx2/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridge.c Tue May 25 19:09:05 2010 (r5588) +++ trunk/src/northbridge/amd/gx2/northbridge.c Wed May 26 01:06:42 2010 (r5589) @@ -486,13 +486,12 @@
/* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { - struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info; u32 tomk; printk(BIOS_DEBUG, "DEVICE_PATH_PCI_DOMAIN\n"); /* cpubug MUST be called before setup_gx2(), so we force the issue here */ northbridgeinit(); cpubug(); - gx2_chipsetinit(nb); + chipsetinit(); setup_gx2(); do_vsmbios(); graphics_init();
Modified: trunk/src/northbridge/amd/gx2/northbridge.h ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridge.h Tue May 25 19:09:05 2010 (r5588) +++ trunk/src/northbridge/amd/gx2/northbridge.h Wed May 26 01:06:42 2010 (r5589) @@ -6,7 +6,6 @@ #else unsigned int gx2_scan_root_bus(device_t root, unsigned int max); int sizeram(void); -void gx2_chipsetinit (struct northbridge_amd_gx2_config *nb); void graphics_init(void); void northbridgeinit(void); #endif
Modified: trunk/src/southbridge/amd/cs5535/Makefile.inc ============================================================================== --- trunk/src/southbridge/amd/cs5535/Makefile.inc Tue May 25 19:09:05 2010 (r5588) +++ trunk/src/southbridge/amd/cs5535/Makefile.inc Wed May 26 01:06:42 2010 (r5589) @@ -1,3 +1,4 @@ driver-y += cs5535.o #driver-y += cs5535_pci.o #driver-y += cs5535_ide.o +obj-y += chipsetinit.o
Modified: trunk/src/southbridge/amd/cs5535/chip.h ============================================================================== --- trunk/src/southbridge/amd/cs5535/chip.h Tue May 25 19:09:05 2010 (r5588) +++ trunk/src/southbridge/amd/cs5535/chip.h Wed May 26 01:06:42 2010 (r5589) @@ -4,7 +4,7 @@ extern struct chip_operations southbridge_amd_cs5535_ops;
struct southbridge_amd_cs5535_config { - int none; + int setupflash; };
#endif /* _SOUTHBRIDGE_AMD_CS5536 */
Copied and modified: trunk/src/southbridge/amd/cs5535/chipsetinit.c (from r5546, trunk/src/northbridge/amd/gx2/chipsetinit.c) ============================================================================== --- trunk/src/northbridge/amd/gx2/chipsetinit.c Fri May 14 11:56:46 2010 (r5546, copy source) +++ trunk/src/southbridge/amd/cs5535/chipsetinit.c Wed May 26 01:06:42 2010 (r5589) @@ -8,10 +8,12 @@ #include <string.h> #include <bitops.h> #include "chip.h" -#include "northbridge.h" +#include "northbridge/amd/gx2/northbridge.h" #include <cpu/amd/gx2def.h> #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> +#include "southbridge/amd/cs5535/cs5535.h" +// This code uses some cs5536 includes because cs5535 includes are empty: #include "southbridge/amd/cs5536/cs5536.h"
/* the structs in this file only set msr.lo. But ... that may not always be true */ @@ -47,18 +49,6 @@ { 0, {.hi=0, .lo=0x000000000} } };
-/* 5536 Clock Gating*/ -static struct msrinit CS5536_CLOCK_GATING_TABLE[] = { -/* MSR Setting*/ - { GLIU_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000004} }, - { GLPCI_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, - { GLCP_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000004} }, - { MDD_SB_GLD_MSR_PM, {.hi=0, .lo=0x050554111} }, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977) */ - { ATA_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, - { AC97_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, - { 0, {.hi=0, .lo=0x000000000} } -}; - #ifdef UNUSED_CODE struct acpiinit { unsigned short ioreg; @@ -81,19 +71,7 @@ {PM_WKXD, 0x0000000A0, 4}, {0,0,0} }; -#endif
-/* return 1 if we are a 5536-based system */ -static int is_5536(void) -{ - msr_t msr; - msr = rdmsr(GLIU_SB_GLD_MSR_CAP); - msr.lo >>= 20; - printk(BIOS_DEBUG, "is_5536: msr.lo is 0x%x(==5 means 5536)\n", msr.lo&0xf); - return ((msr.lo&0xf) == 5); -} - -#ifdef UNUSED_CODE /***************************************************************************** * * pmChipsetInit @@ -256,9 +234,6 @@ unsigned long msrnum; unsigned long totalmem;
- if (is_5536()) - return; - /* SWASIF for A1 DMA */ /* Set all memory to "just above systop" PCI so DMA will work */
@@ -279,18 +254,33 @@ }
void -gx2_chipsetinit (struct northbridge_amd_gx2_config *nb) +chipsetinit(void) { + device_t dev; + struct southbridge_amd_cs5535_config *sb; msr_t msr; struct msrinit *csi; int i; unsigned long msrnum;
+ dev = dev_find_device(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_NS_CS5535_ISA, 0); + + if (!dev) { + printk(BIOS_ERR, "CS5535 not found.\n"); + return; + } + + sb = (struct southbridge_amd_cs5535_config *)dev->chip_info; + + if (!sb) { + printk(BIOS_ERR, "CS5535 configuration not found.\n"); + return; + } + outb( P80_CHIPSET_INIT, 0x80); ChipsetGeodeLinkInit();
- printk(BIOS_DEBUG, "Companion is a %s\n", is_5536()?"CS5536":"CS5535"); - #ifdef UNUSED_CODE /* we hope NEVER to be in coreboot when S3 resumes if (! IsS3Resume()) */ @@ -310,15 +300,13 @@ } #endif
- if (!is_5536()) { - /* Setup USB. Need more details. #118.18 */ - msrnum = MSR_SB_USB1 + 8; - msr.lo = 0x00012090; - msr.hi = 0; - wrmsr(msrnum, msr); - msrnum = MSR_SB_USB2 + 8; - wrmsr(msrnum, msr); - } + /* Setup USB. Need more details. #118.18 */ + msrnum = MSR_SB_USB1 + 8; + msr.lo = 0x00012090; + msr.hi = 0; + wrmsr(msrnum, msr); + msrnum = MSR_SB_USB2 + 8; + wrmsr(msrnum, msr);
/* set hd IRQ */ outl (GPIOL_2_SET, GPIOL_INPUT_ENABLE); @@ -340,10 +328,7 @@
/* Set up Master Configuration Register */ /* If 5536, use same master config settings as 5535, except for OHCI MSRs */ - if (is_5536()) - i = 2; - else - i = 0; + i = 0;
csi = &SB_MASTER_CONF_TABLE[i]; for(; csi->msrnum; csi++){ @@ -354,19 +339,16 @@
/* Flash Setup */ printk(BIOS_INFO, "%sDOING ChipsetFlashSetup()!\n", - nb->setupflash ? "" : "NOT "); + sb->setupflash ? "" : "NOT ");
- if (nb->setupflash) + if (sb->setupflash) ChipsetFlashSetup();
/* Set up Hardware Clock Gating */
/* if (getnvram(TOKEN_SB_CLK_GATE) != TVALUE_DISABLE) */ { - if (is_5536()) - csi = CS5536_CLOCK_GATING_TABLE; - else - csi = CS5535_CLOCK_GATING_TABLE; + csi = CS5535_CLOCK_GATING_TABLE;
for(; csi->msrnum; csi++){ msr.lo = csi->msr.lo;
Modified: trunk/src/southbridge/amd/cs5536/cs5536.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536.c Tue May 25 19:09:05 2010 (r5588) +++ trunk/src/southbridge/amd/cs5536/cs5536.c Wed May 26 01:06:42 2010 (r5589) @@ -518,9 +518,6 @@ * * Called from northbridge init (Pre-VSA). * - * NOTE! This function is NOT called if the CS5536 is combined with - * an AMD Geode GX2. It's ONLY used on Geode LX based systems. - * ****************************************************************************/ void chipsetinit(void) {