Re: [coreboot] [PATCH] Fix RS690 MMCONFIG access

[Myles Watson]

2009/3/17 Carl-Daniel Hailfinger :
> The Pistachio and DBM690T ACPI code uses MMCONFIG to access southbridge
> PCI config registers. This fails because we explicitly disable MMCONFIG
> accesses with disable_pcie_bar3(). The comments in the code state that
> coreboot is expected to reenable MMCONFIG, but that never happens.

I think either of these options would be less ugly:
1. Don't disable MMCONFIG.
2. Enable it in dev.init for the southbridge. (the equivalent of Phase 6 in v3.)
> Index: LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c
>
> --- LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c     (Revision 4010)
> +++ LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c     (Arbeitskopie)
> @@ -36,7 +36,9 @@
>  #include <part/hard_reset.h>
>  #include <part/init_timer.h>
>  #include <boot/elf.h>
> +#include "../southbridge/amd/rs690/rs690.h"
>
> /**
>  * @brief Main function of the DRAM part of coreboot.
>  *
> @@ -49,6 +51,7 @@
>  void hardwaremain(int boot_complete)
>  {
>        struct lb_memory *lb_mem;
> device_t nb_dev;

why call it nb_dev when it's a southbridge?

Thanks,
Myles