Re: [LinuxBIOS] [PATCH] Add initial serial output for Via vt82c686

[Corey Osgood]

Forgot to attach the files. here they are.

-Corey

##################################################################
## BEGIN BOILERPLATE - DO NOT EDIT
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus payload) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
# The fallback image uses FALLBACK_SIZE bytes at the end of the ROM

default ROM_SECTION_SIZE   = FALLBACK_SIZE
    default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )

else
# The normal image goes at the beginning of the LinuxBIOS ROM region
# and uses all the remaining space

default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
    default ROM_SECTION_OFFSET = 0
end

##
## Compute where this copy of linuxBIOS will start in the boot rom
##
default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )

##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
default XIP_ROM_SIZE = 65536
default XIP_ROM_BASE = ((( _ROMBASE + ROM_IMAGE_SIZE ) / XIP_ROM_SIZE ) * XIP_ROM_SIZE - XIP_ROM_SIZE )

## END BOILERPLATE
##################################################################

arch i386 end

##
## Build the objects we have code for in this directory.
##

driver mainboard.o
#if HAVE_MP_TABLE 		object mptable.o 	 end
#if HAVE_PIRQ_TABLE 		object irq_tables.o	 end
#if HAVE_ACPI_TABLES 	object acpi_tables.o end
#object reset.o

# Include the VGA option ROM, but only if we're compiled to use it
#if CONFIG_PCI_ROM_RUN
#	if CONFIG_CONSOLE_VGA	
#		object vgarom.S
#	else
#		object no_vgarom.S
#	end
#else
#	object no_vgarom.S
#end

##
## Romcc output
##
makerule ./failover.E
        depends "$(MAINBOARD)/failover.c ./romcc"
        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end

makerule ./failover.inc
        depends "$(MAINBOARD)/failover.c ./romcc"
        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end

makerule ./auto.E
        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
        action  "./romcc -E -mcpu=p3 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
        action  "./romcc    -mcpu=p3 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end

##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds

##
## Build our reset vector (This is where linuxBIOS is entered)
##
if HAVE_FALLBACK_BOOT
    if USE_FALLBACK_IMAGE 
        mainboardinit cpu/x86/16bit/reset16.inc 
        ldscript /cpu/x86/16bit/reset16.lds
    else
        mainboardinit cpu/x86/32bit/reset32.inc 
        ldscript /cpu/x86/32bit/reset32.lds 
    end
else
    mainboardinit cpu/x86/16bit/reset16.inc 
    ldscript /cpu/x86/16bit/reset16.lds
end

### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc

##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds

###
### This is the early phase of linuxBIOS startup 
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
    ldscript /arch/i386/lib/failover.lds 
    mainboardinit ./failover.inc
end

###
### O.k. We aren't just an intermediary anymore!
###

##
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc

##
## Include the secondary Configuration files 
##
dir /pc80

if CONFIG_CHIP_NAME
    config chip.h
end

# based on sample config for tyan/s2735
chip northbridge/via/vt694
    device pci_domain 0 on end

chip cpu/intel/socket_PGA370 end
end

uses HAVE_MP_TABLE
uses HAVE_ACPI_TABLES
uses HAVE_PIRQ_TABLE
uses HAVE_FALLBACK_BOOT
uses HAVE_OPTION_TABLE
uses IRQ_SLOT_COUNT
#uses CONFIG_MAX_CPUS
#uses CONFIG_LOGICAL_CPUS
#uses CONFIG_MAX_PHYSICAL_CPUS
#uses CONFIG_IOAPIC
#uses CONFIG_SMP
uses CONFIG_ROM_PAYLOAD
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses STACK_SIZE
uses HEAP_SIZE
uses USE_OPTION_TABLE
#uses LB_CKS_RANGE_START
#uses LB_CKS_RANGE_END
#uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
#uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
#uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
#uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
#uses CONFIG_CONSOLE_VGA
#uses CONFIG_PCI_ROM_RUN
uses DEBUG
#uses CPU_OPT
#uses CONFIG_IDE

## The default definitions are used for these
uses CONFIG_ROM_PAYLOAD_START
uses PAYLOAD_SIZE

## These are defined in target Config.lb, don't add here
uses USE_FALLBACK_IMAGE
uses ROM_SIZE
uses ROM_IMAGE_SIZE
uses FALLBACK_SIZE
uses LINUXBIOS_EXTRA_VERSION

## These are defined in mainboard Config.lb, don't add here
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE

###
### Build options
###

##
## ROM_SIZE is the size of boot ROM that this board will use.
##
default ROM_SIZE=256*1024
default ROM_IMAGE_SIZE = 65536

##
## Build code for the fallback boot?
##
default HAVE_FALLBACK_BOOT=1
##default FALLBACK_SIZE=131072
default FALLBACK_SIZE=262144

## Delay timer options
##
default CONFIG_UDELAY_TSC=1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1

##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=0
default IRQ_SLOT_COUNT=5

##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default HAVE_MP_TABLE=0

## Build code to export ACPI tables?
default HAVE_ACPI_TABLES=0

##
## Build code to export a CMOS option table?
##
default HAVE_OPTION_TABLE=0

## CMOS checksum definitions (units == bytes)
## These must match the checksum record in cmos.layout
#default LB_CKS_RANGE_START=128
#default LB_CKS_RANGE_END=130
#default LB_CKS_LOC=131

##
## Build code for SMP support
## Only worry about 2 micro processors
## NOTE: CONFIG_MAX_CPUS is the number of LOGICAL CPUs,
##		 so if CONFIG_LOGICAL_CPUS is 1, CONFIG_MAX_CPUS should be 4.
##
#default CONFIG_SMP=0
#default CONFIG_MAX_CPUS=1
#default CONFIG_LOGICAL_CPUS=1
#default CONFIG_MAX_PHYSICAL_CPUS=2

# VGA Console
# NOTE: to initialize VGA, need to copy the VGA option ROM from the factory BIOS
#	    to VGA.rom
#default CONFIG_CONSOLE_VGA=0
#default CONFIG_PCI_ROM_RUN=0

##
## Build code to setup a generic IOAPIC
##
#default CONFIG_IOAPIC=0

##
## Motherboard identification
##
default MAINBOARD_PART_NUMBER="TIGER230"
default MAINBOARD_VENDOR="Tyan"
#default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480

###
### LinuxBIOS layout values
###

##
## Use a small 8K stack
##
default STACK_SIZE=0x2000

##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000

##
## CMOS settings not currently supported due to conflicts with factory BIOS
##
default USE_OPTION_TABLE = 0

##
## LinuxBIOS C code runs at this location in RAM
##
default _RAMBASE=0x00004000

##
## Load the payload from the ROM
##
default CONFIG_ROM_PAYLOAD = 1

###
### Defaults of options that you may want to override in the target config file
###

##
## The default compiler
##
default CC="$(CROSS_COMPILE)gcc -m32 -fno-stack-protector"
default HOSTCC="gcc -fno-stack-protector"

##
## Disable the gdb stub by default
## 
default CONFIG_GDB_STUB=0

##
## The Serial Console
##

# To Enable the Serial Console
default CONFIG_CONSOLE_SERIAL8250=1

## Select the serial console baud rate
default TTYS0_BAUD=115200
#default TTYS0_BAUD=57600
#default TTYS0_BAUD=38400
#default TTYS0_BAUD=19200
#default TTYS0_BAUD=9600
#default TTYS0_BAUD=4800
#default TTYS0_BAUD=2400
#default TTYS0_BAUD=1200

# Select the serial console base port
default TTYS0_BASE=0x3f8

# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3

##
### Select the linuxBIOS loglevel
##
## EMERG      1   system is unusable               
## ALERT      2   action must be taken immediately 
## CRIT       3   critical conditions              
## ERR        4   error conditions                 
## WARNING    5   warning conditions               
## NOTICE     6   normal but significant condition 
## INFO       7   informational                    
## DEBUG      8   debug-level messages             
## SPEW       9   Way too many details

## Request this level of debugging output
default  DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default  MAXIMUM_CONSOLE_LOGLEVEL=8

##
## Select power on after power fail setting
#default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"

## Things we may not have
#default CONFIG_IDE=1

#default DEBUG=1
# default CPU_OPT="-g"
default CONFIG_CHIP_NAME=1

### End Options.lb
end