[coreboot] [commit] r6584 - trunk/src/mainboard/amd/persimmon

[repository service]

Author: mjones
Date: Sun May 15 23:54:04 2011
New Revision: 6584
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6584

Log:
Enable SPI cacheline prefetch early to reduce boot time.

Signed-off-by: Scott Duplichan 
Acked-by: Marc Jones

Modified:
   trunk/src/mainboard/amd/persimmon/romstage.c

Modified: trunk/src/mainboard/amd/persimmon/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/persimmon/romstage.c	Sun May 15 23:51:31 2011	(r6583)
+++ trunk/src/mainboard/amd/persimmon/romstage.c	Sun May 15 23:54:04 2011	(r6584)
@@ -50,6 +50,13 @@
   // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
   __writemsr (0xc0010062, 0);

+  // early enable of PrefetchEnSPIFromHost
+  if (boot_cpu())
+    {
+    __outdword (0xcf8, 0x8000a3b8);
+    __outdword (0xcfc, __indword (0xcfc) | 0 << 24);
+    }
+
   // early enable of SPI 33 MHz fast mode read
   if (boot_cpu())
     {