Issue #478 has been updated by Bill XIE.
Robert Gruber wrote:
dmesg: TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'. After a period of time the boot finished by auto-switching to hpet. Setting kernel parameter directly to clocksource=hpet the system is booting fast.
Why is the faster clocksource tsc not working and tells coreboot is broken ?
As stated in https://www.chromium.org/chromium-os/how-tos-and-troubleshooting/tsc-resynch... , there are 4 types of TSC, while a core 2 cpu only has Constant TSC, which may change on C state transitions.
Newer cpu like Ivy Bridge have nonstop_tsc and tsc_deadline. They can keep using tsc as clock source.
Does this issue remain on an x200 running vendor firmware?
---------------------------------------- Bug #478: X200 booting Linux takes a long time with TSC (`clocksource=hpet` works) https://ticket.coreboot.org/issues/478#change-1467
* Author: Robert Gruber * Status: New * Priority: Normal * Target version: master * Start date: 2023-04-04 * Affected versions: 4.15, 4.16, 4.17, 4.18, 4.19, master * Needs backport to: master * Related links: Thank you for reporting this issue. Does booting with `'tsc=unstable` also work?
Please the coreboot log messages for example by running `cbmem -1`. ---------------------------------------- dmesg: TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'. After a period of time the boot finished by auto-switching to hpet. Setting kernel parameter directly to clocksource=hpet the system is booting fast.
Why is the faster clocksource tsc not working and tells coreboot is broken ?
---Files-------------------------------- cbmem.log (38.6 KB)