On Thu, Nov 6, 2008 at 1:28 AM, Roman Yeryomin leroi.lists@gmail.com wrote:
On Wed, Nov 5, 2008 at 11:35 PM, Roman Yeryomin leroi.lists@gmail.com wrote:
On Wed, Nov 5, 2008 at 8:09 PM, Marc Jones Marc.Jones@amd.com wrote:
I see the problem. It is interesting that in some situations that it works.
LPC serial IRQs were being left enabled when there is no LPC serial device.
WOW! Cool! :) It works!
Many thanks to everybody who tried to help! One more question right away... can there be any potential issues with eth1 and eth2 sitting on one interrupt?
cat /proc/interrupts CPU0 0: 541075 XT-PIC-XT timer 2: 0 XT-PIC-XT cascade 4: 403 XT-PIC-XT serial 8: 0 XT-PIC-XT rtc 10: 4828 XT-PIC-XT eth0 11: 319 XT-PIC-XT eth1, eth2 14: 20579 XT-PIC-XT ide0 NMI: 0 Non-maskable interrupts LOC: 0 Local timer interrupts RES: 0 Rescheduling interrupts CAL: 0 function call interrupts TLB: 0 TLB shootdowns TRM: 0 Thermal event interrupts SPU: 0 Spurious interrupts ERR: 0 MIS: 0
Roman