Re: Problem with AMD HDT setup for Tyan S2885 - LinuxBIOS debuggi ng

[Ken Fuchs]

YhLu wrote:
> HW engineer said 
> "on S2885, put jumper caps on J94 pin2 and pin3; J95 pin1 and pin2 to make
> HDT and MP HDT work.
> J94 and J95 are in middle of the area between bootable CPU memory modules
> and secondary CPU socket. the pin1 is the pin more close to the board edge
> and power connectors."

Thank you very much, YhLu!  This is exactly the information I need to
get the MP HDT working on my S2885.

Sincerely,

Ken Fuchs
> -----Original Message-----
> From: Ken Fuchs [mailto:[e-mail]] 
> Sent: Tuesday, November 09, 2004 12:35 PM
> To: [e-mail]
> Subject: Problem with AMD HDT setup for Tyan S2885 - LinuxBIOS debugging
>
> Purpose:
>
> To use AMD's HDT hardware/software to debug LinuxBIOS on various
>    mainboards and chipsets.
>
> Two HDT headers were added to a commercial Tyan S2885 board.
>
> Here's my hardware setup:
>
> S2885 with HDT CPU0 header <-> HDT ribbon cable
>           and HDT CPU1 header <-> HDT ribbon cable
>
> HDT ribbon cable <-> HDT Multiprocessor Adapter
>    HDT ribbon cable <-> |
>
> HDT Multiprocessor Adapter <-> Macraigor Systems' OCDemon (Raven)
>
> OCDemon (Raven) <-> parallel cable <-> host EPP mode port
>
> Power up sequence:
> Host
> Target
> OCDemon (Raven)
> HDT MP Adapter
>
> Symptoms of the problem:
>
> OCDemon host and target lights never go on.
>
> When using the host HDT software to open a new workspace, only 1
> processor is shown as available.
>
> While completing the opening of this single processor workspace, a
> warning window with the text below pops open:
>
> +--------------------------------------------+
> |Communication between HDT and               |
> |Processor No. 0 has problem!                |
> |                                            |
> |Please check your HDT host                  |
> |and target TAP connections.                 |
> |                                            |
> |Do you want to continue with incorrect info?|
> +--------------------------------------------+
>
> Possible clue to the solution:
>
> Missing TDI/TDO jumpers or jumper headers?  There is a 2x3 header
>    pad (no header) directly between the P1 socket and the P0 DIMM
>    sockets that could be the correct place for these jumper headers.
>    Maybe all I need to do is add a 2x3 header there and trace the
>    routes of the six pins, hopefully back to the P0's HDT connector?
>    (I don't have access to the S2885's schematics.)
>
> It seems that MP HDT must be enabled in this way.  I know that
>    reference boards have toggle switches for this purpose.
>
> Please respond with your suggestions.
>
> Thank you very much!
>
> Sincerely,
>
> Ken Fuchs 
> _______________________________________________
> Linuxbios mailing list
> [e-mail]
> http://www.clustermatic.org/mailman/listinfo/linuxbios