-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Mart Raudsepp Sent: Monday, February 09, 2009 9:22 AM To: coreboot@coreboot.org Subject: Re: [coreboot] [PATCH] cs5536/nand: Allow setting of NAND timing values in the dts.
Ühel kenal päeval, E, 2009-02-09 kell 08:04, kirjutas ron minnich:
nice to see people using the dts now!
It's a bit hard to use it for the LBAR setup as well (the code in chipset_flash_setup() in cs5536.c), as it needs to happen before VSA init, and VSA init is done in northbridge domain phase2_fixup - so we don't have a phase for NAND device to run before VSA is inited. Otherwise I'd use the NAND initialization from chipsetinit() to some nand_phase1 as well.
Acked-by: Ronald G. Minnich rminnich@gmail.com
I'm going to have to NAK this myself, as it doesn't compile with my gcc if there is no NAND device in the mainboard dts, as there is no southbridge_amd_cs5536_nand_config in statictree.h then, and gcc complains about /home/leio/dev/coreboot-v3/southbridge/amd/cs5536/cs5536.c:119: error: dereferencing pointer to incomplete type
We have this problem with IDE flags on the AMD 8111 chipset too. I'm not sure what the best way to do it is. So far we've just been forced to include the (possibly disabled) device in the dts.
Thanks, Myles