[coreboot] KBuild Report [r5061]

[coresystems autobuild service]

[1/117] a-trend/atc-6220 ok.
Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_SLOT_2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[2/117] a-trend/atc-6240 ok.
Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_SLOT_2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[3/117] abit/be6-ii_v2_0 ok.
Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_SLOT_2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[4/117] advantech/pcm-5820 ok.
Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_AMD_GX1  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x0
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WRITE_HIGH_TABLES  = 0x1
+CONFIG_WRITE_HIGH_TABLES  = 0x0
[5/117] amd/db800 ok.
Processing mainboard/amd/db800 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_AMD_LX  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[6/117] amd/dbm690t ok.
Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/amd/dbm690t/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_GFXUMA  = 0x1
+CONFIG_GFXUMA  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
[7/117] amd/norwich ok.
Processing mainboard/amd/norwich (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_AMD_LX  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[8/117] amd/pistachio ok.
Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/amd/pistachio/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_GFXUMA  = 0x1
+CONFIG_GFXUMA  = 0x0
+CONFIG_HAVE_ACPI_TABLES  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES  = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES  = 0x0
+CONFIG_HAVE_MP_TABLE  = 0x1
-CONFIG_HAVE_OPTION_TABLE  = 0x0
+CONFIG_HAVE_OPTION_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x1
[9/117] amd/rumba ok.
Processing mainboard/amd/rumba (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_AMD_GX2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_HAVE_HIGH_TABLES  = 0x0
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WRITE_HIGH_TABLES  = 0x1
+CONFIG_WRITE_HIGH_TABLES  = 0x0
[10/117] amd/serengeti_cheetah ok.
Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/amd/serengeti_cheetah/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_HAVE_ACPI_TABLES  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[11/117] amd/serengeti_cheetah_fam10 ok.
Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_HAVE_ACPI_TABLES  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[12/117] arima/hdama ok.
Processing mainboard/arima/hdama (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/arima/hdama/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
-CONFIG_DCACHE_RAM_BASE  = 0xcf000
+CONFIG_DCACHE_RAM_BASE  = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x1000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_DCACHE_RAM_SIZE  = 0x8000
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[13/117] artecgroup/dbe61 ok.
Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_AMD_LX  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[14/117] asi/mb_5blgp ok.
Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_AMD_GX1  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x0
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WRITE_HIGH_TABLES  = 0x1
+CONFIG_WRITE_HIGH_TABLES  = 0x0
[15/117] asi/mb_5blmp ok.
Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_AMD_GX1  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_GX1_VIDEO  = 0x1
+CONFIG_GX1_VIDEOMODE  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x0
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
+CONFIG_SPLASH_GRAPHIC  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WRITE_HIGH_TABLES  = 0x1
+CONFIG_WRITE_HIGH_TABLES  = 0x0
[16/117] asus/a8n_e ok.
Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/asus/a8n_e/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
-CONFIG_DCACHE_RAM_BASE  = 0xc8000
+CONFIG_DCACHE_RAM_BASE  = 0xcf000
-CONFIG_DCACHE_RAM_SIZE  = 0x8000
+CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[17/117] asus/a8v-e_se ok.
Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
+CONFIG_EPIA_VT8237R_INIT  = 0x0
+CONFIG_HAVE_ACPI_TABLES  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[18/117] asus/m2v-mx_se ok.
Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/asus/m2v-mx_se/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_EPIA_VT8237R_INIT  = 0x0
+CONFIG_HAVE_ACPI_TABLES  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x1
-CONFIG_HAVE_LOW_TABLES  = 0x0
+CONFIG_HAVE_LOW_TABLES  = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK  = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK  = 0x100000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x1f00000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_RAMTOP  = 0x2000000
+CONFIG_RAMTOP  = 0x200000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[19/117] asus/mew-am ok.
Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
+CONFIG_I810_VIDEO_MB_1MB  = 0x1
+CONFIG_I810_VIDEO_MB_512KB  = 0x0
+CONFIG_I810_VIDEO_MB_OFF  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[20/117] asus/mew-vm ok.
Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
-CONFIG_HAVE_OPTION_TABLE  = 0x0
+CONFIG_HAVE_OPTION_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
+CONFIG_I810_VIDEO_MB_1MB  = 0x1
+CONFIG_I810_VIDEO_MB_512KB  = 0x0
+CONFIG_I810_VIDEO_MB_OFF  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[21/117] asus/p2b-d ok.
Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_SLOT_2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[22/117] asus/p2b-ds ok.
Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_SLOT_2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[23/117] asus/p2b-f ok.
Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_SLOT_2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[24/117] asus/p2b ok.
Processing mainboard/asus/p2b (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_SLOT_2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[25/117] asus/p3b-f ok.
Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_SLOT_2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[26/117] axus/tc320 ok.
Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_AMD_GX1  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x0
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WRITE_HIGH_TABLES  = 0x1
+CONFIG_WRITE_HIGH_TABLES  = 0x0
[27/117] azza/pt-6ibd ok.
Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_SLOT_2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[28/117] bcom/winnet100 ok.
Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_AMD_GX1  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x0
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WRITE_HIGH_TABLES  = 0x1
+CONFIG_WRITE_HIGH_TABLES  = 0x0
[29/117] bcom/winnetp680 ok.
Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/bcom/winnetp680/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_CN700_VIDEO_MB_128MB  = 0x0
+CONFIG_CN700_VIDEO_MB_16MB  = 0x0
+CONFIG_CN700_VIDEO_MB_32MB  = 0x1
+CONFIG_CN700_VIDEO_MB_64MB  = 0x0
+CONFIG_CN700_VIDEO_MB_8MB  = 0x0
+CONFIG_CN700_VIDEO_MB_OFF  = 0x0
+CONFIG_CPU_VIA_C7  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_EPIA_VT8237R_INIT  = 0x0
+CONFIG_FALLBACK_SIZE  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_SMP  = 0x1
+CONFIG_SMP  = 0x0
[30/117] biostar/m6tba ok.
Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_SLOT_2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[31/117] broadcom/blast ok.
Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[32/117] compaq/deskpro_en_sff_p600 ok.
Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_SLOT_2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[33/117] dell/s1850 ok.
Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_TTYS0_BAUD  = 0x4b00
+CONFIG_TTYS0_BAUD  = 0x1c200
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[34/117] digitallogic/adl855pc ok.
Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_SMP  = 0x0
+CONFIG_SMP  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[35/117] digitallogic/msm586seg ok.
Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/digitallogic/msm586seg/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_CPU_AMD_SC520  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x0
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x0
+CONFIG_UDELAY_LAPIC  = 0x0
+CONFIG_UDELAY_TSC  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[36/117] digitallogic/msm800sev ok.
Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_AMD_LX  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[37/117] eaglelion/5bcm ok.
Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_AMD_GX1  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_GX1_VIDEO  = 0x1
+CONFIG_GX1_VIDEOMODE  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x0
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
+CONFIG_SPLASH_GRAPHIC  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WRITE_HIGH_TABLES  = 0x1
+CONFIG_WRITE_HIGH_TABLES  = 0x0
[38/117] emulation/qemu-x86 ok.
Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/emulation/qemu-x86/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_CPU_EMULATION_QEMU_X86  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0x8f000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_HAVE_HIGH_TABLES  = 0x0
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x0
+CONFIG_UDELAY_LAPIC  = 0x0
+CONFIG_UDELAY_TSC  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WRITE_HIGH_TABLES  = 0x1
+CONFIG_WRITE_HIGH_TABLES  = 0x0
[39/117] gigabyte/ga-6bxc ok.
Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_SLOT_2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[40/117] gigabyte/ga_2761gxdk ok.
Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_HAVE_FALLBACK_BOOT  = 0x1
+CONFIG_HAVE_FALLBACK_BOOT  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY  = 0x0
-CONFIG_SERIAL_CPU_INIT  = 0x1
+CONFIG_SERIAL_CPU_INIT  = 0x0
-CONFIG_USE_FALLBACK_IMAGE  = 0x1
+CONFIG_USE_FALLBACK_IMAGE  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[41/117] gigabyte/m57sli ok.
Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/gigabyte/m57sli/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_HAVE_ACPI_TABLES  = 0x1
-CONFIG_HAVE_FALLBACK_BOOT  = 0x1
+CONFIG_HAVE_FALLBACK_BOOT  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY  = 0x0
-CONFIG_SERIAL_CPU_INIT  = 0x1
+CONFIG_SERIAL_CPU_INIT  = 0x0
-CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL  = 0x1
-CONFIG_USE_FALLBACK_IMAGE  = 0x1
+CONFIG_USE_FALLBACK_IMAGE  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[42/117] hp/dl145_g3 ok.
Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_SERIAL_CPU_INIT  = 0x0
+CONFIG_SERIAL_CPU_INIT  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[43/117] hp/e_vectra_p2706t ok.
Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
+CONFIG_I810_VIDEO_MB_1MB  = 0x1
+CONFIG_I810_VIDEO_MB_512KB  = 0x0
+CONFIG_I810_VIDEO_MB_OFF  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
[44/117] ibm/e325 ok.
Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK  = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK  = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x1
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_SERIAL_CPU_INIT  = 0x1
+CONFIG_SERIAL_CPU_INIT  = 0x0
-CONFIG_SMP  = 0x1
+CONFIG_SMP  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x1
[45/117] ibm/e326 ok.
Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/ibm/e326/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK  = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK  = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x1
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_SERIAL_CPU_INIT  = 0x1
+CONFIG_SERIAL_CPU_INIT  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x1
[46/117] iei/juki-511p ok.
Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/iei/juki-511p/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_CPU_AMD_GX1  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_GX1_VIDEO  = 0x1
+CONFIG_GX1_VIDEOMODE  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x0
-CONFIG_HAVE_OPTION_TABLE  = 0x0
+CONFIG_HAVE_OPTION_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
+CONFIG_SPLASH_GRAPHIC  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WRITE_HIGH_TABLES  = 0x1
+CONFIG_WRITE_HIGH_TABLES  = 0x0
[47/117] iei/nova4899r ok.
Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_AMD_GX1  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_GX1_VIDEO  = 0x1
+CONFIG_GX1_VIDEOMODE  = 0x0
-CONFIG_HAVE_FALLBACK_BOOT  = 0x0
+CONFIG_HAVE_FALLBACK_BOOT  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x0
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
+CONFIG_SPLASH_GRAPHIC  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WRITE_HIGH_TABLES  = 0x1
+CONFIG_WRITE_HIGH_TABLES  = 0x0
[48/117] iei/pcisa-lx-800-r10 ok.
Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_AMD_LX  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[49/117] intel/d945gclf ok.
Processing mainboard/intel/d945gclf (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/intel/d945gclf/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_CORE  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xffed8000
+CONFIG_DCACHE_RAM_BASE  = 0xffdf8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_GFXUMA  = 0x1
+CONFIG_GFXUMA  = 0x0
+CONFIG_HAVE_ACPI_TABLES  = 0x1
-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES  = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES  = 0x0
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_USE_DCACHE_RAM  = 0x1
+CONFIG_USE_DCACHE_RAM  = 0x0
[50/117] intel/eagleheights ok.
Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_CORE2  = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_ACPI_TABLES  = 0x1
-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES  = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES  = 0x0
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID  = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID  = 0x8086
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_USE_DCACHE_RAM  = 0x1
+CONFIG_USE_DCACHE_RAM  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[51/117] intel/jarrell ok.
Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_ATI_RAGE_XL  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAX_REBOOT_CNT  = 0x8
+CONFIG_MAX_REBOOT_CNT  = 0x3
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[52/117] intel/mtarvon ok.
Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LB_CKS_LOC  = 0x7e
+CONFIG_LB_CKS_LOC  = 0x7b
-CONFIG_LB_CKS_RANGE_END  = 0x7d
+CONFIG_LB_CKS_RANGE_END  = 0x7a
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[53/117] intel/truxton ok.
Processing mainboard/intel/truxton (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_EP80579  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LB_CKS_LOC  = 0x7e
+CONFIG_LB_CKS_LOC  = 0x7b
-CONFIG_LB_CKS_RANGE_END  = 0x7d
+CONFIG_LB_CKS_RANGE_END  = 0x7a
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[54/117] intel/xe7501devkit ok.
Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEBUG  = 0x1
+CONFIG_DEBUG  = 0x0
+CONFIG_HAVE_ACPI_TABLES  = 0x1
-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
-CONFIG_HAVE_OPTION_TABLE  = 0x0
+CONFIG_HAVE_OPTION_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[55/117] iwill/dk8_htx ok.
Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/iwill/dk8_htx/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
-CONFIG_DCACHE_RAM_BASE  = 0xc4000
+CONFIG_DCACHE_RAM_BASE  = 0xc8000
-CONFIG_DCACHE_RAM_SIZE  = 0xc000
+CONFIG_DCACHE_RAM_SIZE  = 0x8000
+CONFIG_HAVE_ACPI_TABLES  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK  = 0x80000
+CONFIG_HW_MEM_HOLE_SIZEK  = 0x100000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x1
[56/117] iwill/dk8s2 ok.
Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_ATI_RAGE_XL  = 0x1
-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
-CONFIG_DCACHE_RAM_BASE  = 0xcf000
+CONFIG_DCACHE_RAM_BASE  = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x1000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_DCACHE_RAM_SIZE  = 0x8000
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK  = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK  = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x1
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_SERIAL_CPU_INIT  = 0x1
+CONFIG_SERIAL_CPU_INIT  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x1
[57/117] iwill/dk8x ok.
Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
-CONFIG_DCACHE_RAM_BASE  = 0xcf000
+CONFIG_DCACHE_RAM_BASE  = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x1000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_DCACHE_RAM_SIZE  = 0x8000
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK  = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK  = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x1
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_SERIAL_CPU_INIT  = 0x1
+CONFIG_SERIAL_CPU_INIT  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x1
[58/117] jetway/j7f24 ok.
Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/jetway/j7f24/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_CN700_VIDEO_MB_128MB  = 0x0
+CONFIG_CN700_VIDEO_MB_16MB  = 0x0
+CONFIG_CN700_VIDEO_MB_32MB  = 0x1
+CONFIG_CN700_VIDEO_MB_64MB  = 0x0
+CONFIG_CN700_VIDEO_MB_8MB  = 0x0
+CONFIG_CN700_VIDEO_MB_OFF  = 0x0
+CONFIG_CPU_VIA_C7  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_EPIA_VT8237R_INIT  = 0x0
+CONFIG_FALLBACK_SIZE  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
-CONFIG_HAVE_OPTION_TABLE  = 0x0
+CONFIG_HAVE_OPTION_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
[59/117] kontron/986lcd-m ok.
Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/kontron/986lcd-m/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_CORE  = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
[60/117] kontron/kt690 ok.
Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/kontron/kt690/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_HAVE_ACPI_TABLES  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[61/117] lippert/frontrunner ok.
Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_AMD_GX2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_HAVE_HIGH_TABLES  = 0x0
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WRITE_HIGH_TABLES  = 0x1
+CONFIG_WRITE_HIGH_TABLES  = 0x0
[62/117] lippert/roadrunner-lx ok.
Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_AMD_LX  = 0x1
-CONFIG_DEBUG  = 0x1
+CONFIG_DEBUG  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[63/117] lippert/spacerunner-lx ok.
Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_AMD_LX  = 0x1
-CONFIG_DEBUG  = 0x1
+CONFIG_DEBUG  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[64/117] mitac/6513wu ok.
Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
+CONFIG_I810_VIDEO_MB_1MB  = 0x1
+CONFIG_I810_VIDEO_MB_512KB  = 0x0
+CONFIG_I810_VIDEO_MB_OFF  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[65/117] msi/ms6119 ok.
Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_SLOT_2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID  = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID  = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[66/117] msi/ms6147 ok.
Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_SLOT_2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID  = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID  = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[67/117] msi/ms6156 ok.
Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_SLOT_2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID  = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID  = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[68/117] msi/ms6178 ok.
Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
+CONFIG_I810_VIDEO_MB_1MB  = 0x1
+CONFIG_I810_VIDEO_MB_512KB  = 0x0
+CONFIG_I810_VIDEO_MB_OFF  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID  = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID  = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[69/117] msi/ms7135 ok.
Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/msi/ms7135/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_DCACHE_RAM_BASE  = 0xc8000
+CONFIG_DCACHE_RAM_BASE  = 0xcf000
-CONFIG_DCACHE_RAM_SIZE  = 0x8000
+CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[70/117] msi/ms7260 ok.
Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/msi/ms7260/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_HAVE_FALLBACK_BOOT  = 0x1
+CONFIG_HAVE_FALLBACK_BOOT  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY  = 0x0
-CONFIG_SERIAL_CPU_INIT  = 0x1
+CONFIG_SERIAL_CPU_INIT  = 0x0
-CONFIG_USE_FALLBACK_IMAGE  = 0x1
+CONFIG_USE_FALLBACK_IMAGE  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[71/117] msi/ms9185 ok.
Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/msi/ms9185/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID  = 0x1022
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID  = 0x1462
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_SERIAL_CPU_INIT  = 0x0
+CONFIG_SERIAL_CPU_INIT  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[72/117] msi/ms9282 ok.
Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/msi/ms9282/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_ENABLE_APIC_EXT_ID  = 0x1
+CONFIG_ENABLE_APIC_EXT_ID  = 0x0
-CONFIG_HAVE_FALLBACK_BOOT  = 0x1
+CONFIG_HAVE_FALLBACK_BOOT  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK  = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK  = 0x100000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY  = 0x0
-CONFIG_SERIAL_CPU_INIT  = 0x1
+CONFIG_SERIAL_CPU_INIT  = 0x0
-CONFIG_USE_FALLBACK_IMAGE  = 0x1
+CONFIG_USE_FALLBACK_IMAGE  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[73/117] nec/powermate2000 ok.
Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
+CONFIG_I810_VIDEO_MB_1MB  = 0x1
+CONFIG_I810_VIDEO_MB_512KB  = 0x0
+CONFIG_I810_VIDEO_MB_OFF  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[74/117] newisys/khepri ok.
Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x1000
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[75/117] nvidia/l1_2pvv ok.
Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/nvidia/l1_2pvv/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_HAVE_FALLBACK_BOOT  = 0x1
+CONFIG_HAVE_FALLBACK_BOOT  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY  = 0x0
-CONFIG_SERIAL_CPU_INIT  = 0x1
+CONFIG_SERIAL_CPU_INIT  = 0x0
-CONFIG_USE_FALLBACK_IMAGE  = 0x1
+CONFIG_USE_FALLBACK_IMAGE  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x0
[76/117] olpc/btest ok.
Processing mainboard/olpc/btest (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_AMD_GX2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_HAVE_HIGH_TABLES  = 0x0
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WRITE_HIGH_TABLES  = 0x1
+CONFIG_WRITE_HIGH_TABLES  = 0x0
[77/117] olpc/rev_a ok.
Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_AMD_GX2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_HAVE_HIGH_TABLES  = 0x0
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WRITE_HIGH_TABLES  = 0x1
+CONFIG_WRITE_HIGH_TABLES  = 0x0
[78/117] pcengines/alix1c ok.
Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_AMD_LX  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[79/117] rca/rm4100 ok.
Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/rca/rm4100/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
+CONFIG_I830_VIDEO_MB_1MB  = 0x0
+CONFIG_I830_VIDEO_MB_512KB  = 0x0
+CONFIG_I830_VIDEO_MB_8MB  = 0x1
+CONFIG_I830_VIDEO_MB_OFF  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[80/117] roda/rk886ex ok.
Processing mainboard/roda/rk886ex (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/roda/rk886ex/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_CORE  = 0x1
-CONFIG_GFXUMA  = 0x1
+CONFIG_GFXUMA  = 0x0
+CONFIG_HAVE_ACPI_TABLES  = 0x1
-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES  = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES  = 0x0
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_USE_DCACHE_RAM  = 0x1
+CONFIG_USE_DCACHE_RAM  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES  = 0x0
[81/117] soyo/sy-6ba-plus-iii ok.
Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_SLOT_2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[82/117] sunw/ultra40 ok.
Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID  = 0x1
+CONFIG_ENABLE_APIC_EXT_ID  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[83/117] supermicro/h8dme ok.
Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/supermicro/h8dme/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
-CONFIG_HAVE_LOW_TABLES  = 0x0
+CONFIG_HAVE_LOW_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_SERIAL_CPU_INIT  = 0x0
+CONFIG_SERIAL_CPU_INIT  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x0
[84/117] supermicro/h8dmr ok.
Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/supermicro/h8dmr/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_SERIAL_CPU_INIT  = 0x0
+CONFIG_SERIAL_CPU_INIT  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x0
[85/117] supermicro/h8dmr_fam10 ok.
Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[86/117] supermicro/x6dai_g ok.
Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[87/117] supermicro/x6dhe_g ok.
Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[88/117] supermicro/x6dhe_g2 ok.
Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[89/117] supermicro/x6dhr_ig ok.
Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[90/117] supermicro/x6dhr_ig2 ok.
Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[91/117] technexion/tim5690 ok.
Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/technexion/tim5690/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_HAVE_ACPI_TABLES  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
[92/117] technexion/tim8690 ok.
Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/technexion/tim8690/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_GFXUMA  = 0x1
+CONFIG_GFXUMA  = 0x0
+CONFIG_HAVE_ACPI_TABLES  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES  = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES  = 0x0
+CONFIG_HAVE_MP_TABLE  = 0x1
-CONFIG_HAVE_OPTION_TABLE  = 0x0
+CONFIG_HAVE_OPTION_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x1
[93/117] technologic/ts5300 ok.
Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/technologic/ts5300/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_CPU_AMD_SC520  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x0
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2  = 0x0
-CONFIG_TTYS0_BASE  = 0x2f8
+CONFIG_TTYS0_BASE  = 0x3f8
+CONFIG_UDELAY_LAPIC  = 0x0
+CONFIG_UDELAY_TSC  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[94/117] televideo/tc7020 ok.
Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_AMD_GX1  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x0
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WRITE_HIGH_TABLES  = 0x1
+CONFIG_WRITE_HIGH_TABLES  = 0x0
[95/117] thomson/ip1000 ok.
Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/thomson/ip1000/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
+CONFIG_I830_VIDEO_MB_1MB  = 0x0
+CONFIG_I830_VIDEO_MB_512KB  = 0x0
+CONFIG_I830_VIDEO_MB_8MB  = 0x1
+CONFIG_I830_VIDEO_MB_OFF  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[96/117] tyan/s1846 ok.
Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_INTEL_SLOT_2  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_HIGH_TABLES  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[97/117] tyan/s2735 ok.
Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_SERIAL_CPU_INIT  = 0x0
+CONFIG_SERIAL_CPU_INIT  = 0x1
-CONFIG_USE_PRINTK_IN_CAR  = 0x1
+CONFIG_USE_PRINTK_IN_CAR  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[98/117] tyan/s2850 ok.
Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
-CONFIG_DCACHE_RAM_BASE  = 0xcf000
+CONFIG_DCACHE_RAM_BASE  = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x1000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_DCACHE_RAM_SIZE  = 0x8000
-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[99/117] tyan/s2875 ok.
Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
-CONFIG_DCACHE_RAM_BASE  = 0xcf000
+CONFIG_DCACHE_RAM_BASE  = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x1000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_DCACHE_RAM_SIZE  = 0x8000
-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[100/117] tyan/s2880 ok.
Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
-CONFIG_DCACHE_RAM_BASE  = 0xcf000
+CONFIG_DCACHE_RAM_BASE  = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x1000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_DCACHE_RAM_SIZE  = 0x8000
-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x1
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[101/117] tyan/s2881 ok.
Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
-CONFIG_DCACHE_RAM_BASE  = 0xcf000
+CONFIG_DCACHE_RAM_BASE  = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x1000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_DCACHE_RAM_SIZE  = 0x8000
-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[102/117] tyan/s2882 ok.
Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
-CONFIG_DCACHE_RAM_BASE  = 0xcf000
+CONFIG_DCACHE_RAM_BASE  = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x1000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_DCACHE_RAM_SIZE  = 0x8000
-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[103/117] tyan/s2885 ok.
Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
-CONFIG_DCACHE_RAM_BASE  = 0xcf000
+CONFIG_DCACHE_RAM_BASE  = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x1000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_DCACHE_RAM_SIZE  = 0x8000
-CONFIG_ENABLE_APIC_EXT_ID  = 0x1
+CONFIG_ENABLE_APIC_EXT_ID  = 0x0
-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[104/117] tyan/s2891 ok.
Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/tyan/s2891/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
-CONFIG_DCACHE_RAM_BASE  = 0xcf000
+CONFIG_DCACHE_RAM_BASE  = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x1000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_DCACHE_RAM_SIZE  = 0x8000
+CONFIG_HAVE_ACPI_TABLES  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
[105/117] tyan/s2892 ok.
Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/tyan/s2892/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
-CONFIG_DCACHE_RAM_BASE  = 0xcf000
+CONFIG_DCACHE_RAM_BASE  = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x1000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_DCACHE_RAM_SIZE  = 0x8000
+CONFIG_HAVE_ACPI_TABLES  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
[106/117] tyan/s2895 ok.
Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/tyan/s2895/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
-CONFIG_DCACHE_RAM_BASE  = 0xcf000
+CONFIG_DCACHE_RAM_BASE  = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x1000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_DCACHE_RAM_SIZE  = 0x8000
+CONFIG_HAVE_ACPI_TABLES  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_SERIAL_CPU_INIT  = 0x0
+CONFIG_SERIAL_CPU_INIT  = 0x1
[107/117] tyan/s2912 ok.
Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/tyan/s2912/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_HAVE_FALLBACK_BOOT  = 0x1
+CONFIG_HAVE_FALLBACK_BOOT  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HEAP_SIZE  = 0x8000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY  = 0x0
-CONFIG_SERIAL_CPU_INIT  = 0x1
+CONFIG_SERIAL_CPU_INIT  = 0x0
-CONFIG_USE_FALLBACK_IMAGE  = 0x1
+CONFIG_USE_FALLBACK_IMAGE  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT  = 0x0
[108/117] tyan/s2912_fam10 ok.
Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/tyan/s2912_fam10/Config-abuild.lb ok
  Creating builddir...ok

-CONFIG_HAVE_FALLBACK_BOOT  = 0x1
+CONFIG_HAVE_FALLBACK_BOOT  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY  = 0x0
-CONFIG_SERIAL_CPU_INIT  = 0x1
+CONFIG_SERIAL_CPU_INIT  = 0x0
-CONFIG_USE_FALLBACK_IMAGE  = 0x1
+CONFIG_USE_FALLBACK_IMAGE  = 0x0
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[109/117] tyan/s4880 ok.
Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID  = 0x1
+CONFIG_ENABLE_APIC_EXT_ID  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
-CONFIG_RAMBASE  = 0x4000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[110/117] tyan/s4882 ok.
Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

-CONFIG_CPU_SOCKET_TYPE  = 0x10
+CONFIG_CPU_SOCKET_TYPE  = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE  = 0x1000
-CONFIG_ENABLE_APIC_EXT_ID  = 0x1
+CONFIG_ENABLE_APIC_EXT_ID  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_RAMBASE  = 0x2000
+CONFIG_RAMBASE  = 0x100000
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[111/117] via/epia-cn ok.
Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/via/epia-cn/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_CN700_VIDEO_MB_128MB  = 0x0
+CONFIG_CN700_VIDEO_MB_16MB  = 0x0
+CONFIG_CN700_VIDEO_MB_32MB  = 0x1
+CONFIG_CN700_VIDEO_MB_64MB  = 0x0
+CONFIG_CN700_VIDEO_MB_8MB  = 0x0
+CONFIG_CN700_VIDEO_MB_OFF  = 0x0
+CONFIG_CPU_VIA_C7  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_EPIA_VT8237R_INIT  = 0x0
+CONFIG_FALLBACK_SIZE  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
[112/117] via/epia-m ok.
Processing mainboard/via/epia-m (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/via/epia-m/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_CPU_VIA_C3  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
+CONFIG_FALLBACK_SIZE  = 0x0
+CONFIG_HAVE_ACPI_TABLES  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
[113/117] via/epia-m700 ok.
Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/via/epia-m700/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_CPU_VIA_C7  = 0x1
-CONFIG_DCACHE_RAM_SIZE  = 0x2000
+CONFIG_DCACHE_RAM_SIZE  = 0x8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_FALLBACK_SIZE  = 0x0
+CONFIG_HAVE_ACPI_TABLES  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x0
-CONFIG_HEAP_SIZE  = 0x5000
+CONFIG_HEAP_SIZE  = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID  = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID  = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_USE_DCACHE_RAM  = 0x1
+CONFIG_USE_DCACHE_RAM  = 0x0
[114/117] via/epia-n ok.
Processing mainboard/via/epia-n (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/via/epia-n/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_CN400_VIDEO_MB_128MB  = 0x0
+CONFIG_CN400_VIDEO_MB_16MB  = 0x0
+CONFIG_CN400_VIDEO_MB_32MB  = 0x1
+CONFIG_CN400_VIDEO_MB_64MB  = 0x0
+CONFIG_CN400_VIDEO_MB_8MB  = 0x0
+CONFIG_CN400_VIDEO_MB_OFF  = 0x0
+CONFIG_CPU_VIA_C3  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_FALLBACK_SIZE  = 0x0
+CONFIG_HAVE_ACPI_TABLES  = 0x1
+CONFIG_HAVE_HIGH_TABLES  = 0x0
-CONFIG_HAVE_MAINBOARD_RESOURCES  = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES  = 0x0
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_SMP  = 0x1
+CONFIG_SMP  = 0x0
-CONFIG_WRITE_HIGH_TABLES  = 0x1
+CONFIG_WRITE_HIGH_TABLES  = 0x0
[115/117] via/epia ok.
Processing mainboard/via/epia (i386: ok, we're amd64 with a  cross compiler)
  Creating config file... ok
  Creating builddir...ok

+CONFIG_CPU_VIA_C3  = 0x1
-CONFIG_DCACHE_RAM_BASE  = 0xc0000
-CONFIG_DCACHE_RAM_SIZE  = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_FALLBACK_SIZE  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
-CONFIG_HAVE_INIT_TIMER  = 0x0
+CONFIG_HAVE_INIT_TIMER  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE  = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU  = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL  = 0x0
-CONFIG_PCI_ROM_RUN  = 0x0
+CONFIG_PCI_ROM_RUN  = 0x1
-CONFIG_UDELAY_IO  = 0x1
+CONFIG_UDELAY_IO  = 0x0
-CONFIG_UDELAY_TSC  = 0x0
+CONFIG_UDELAY_TSC  = 0x1
-CONFIG_VGA_ROM_RUN  = 0x0
+CONFIG_VGA_ROM_RUN  = 0x1
[116/117] via/pc2500e ok.
Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/via/pc2500e/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_CN700_VIDEO_MB_128MB  = 0x0
+CONFIG_CN700_VIDEO_MB_16MB  = 0x0
+CONFIG_CN700_VIDEO_MB_32MB  = 0x1
+CONFIG_CN700_VIDEO_MB_64MB  = 0x0
+CONFIG_CN700_VIDEO_MB_8MB  = 0x0
+CONFIG_CN700_VIDEO_MB_OFF  = 0x0
+CONFIG_CPU_VIA_C7  = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_EPIA_VT8237R_INIT  = 0x0
+CONFIG_FALLBACK_SIZE  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x1
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_USE_OPTION_TABLE  = 0x1
+CONFIG_USE_OPTION_TABLE  = 0x0
[117/117] via/vt8454c ok.
Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a  cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5061/targets/via/vt8454c/Config-abuild.lb ok
  Creating builddir...ok

+CONFIG_CPU_VIA_C7  = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL  = 0x8
+CONFIG_HAVE_ACPI_TABLES  = 0x1
-CONFIG_HAVE_HARD_RESET  = 0x1
+CONFIG_HAVE_HARD_RESET  = 0x0
+CONFIG_HAVE_HIGH_TABLES  = 0x0
+CONFIG_HAVE_MP_TABLE  = 0x1
+CONFIG_HAVE_PIRQ_TABLE  = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT  = 0x0
-CONFIG_LOGICAL_CPUS  = 0x0
+CONFIG_LOGICAL_CPUS  = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID  = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID  = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL  = 0x8
-CONFIG_SMP  = 0x1
+CONFIG_SMP  = 0x0
-CONFIG_WRITE_HIGH_TABLES  = 0x1
+CONFIG_WRITE_HIGH_TABLES  = 0x0