Author: cozzie Date: 2008-10-15 08:41:16 +0200 (Wed, 15 Oct 2008) New Revision: 929
Modified: coreboot-v3/arch/x86/pci_ops_conf1.c coreboot-v3/include/device/pci_ids.h coreboot-v3/include/spd.h coreboot-v3/superio/winbond/w83627hf/stage1.c Log: Commit a few things I forgot with the vt8237 patch, and also a couple minor whitespace fixes I've stumbled accross.
Signed-off-by: Corey Osgood corey.osgood@gmail.com Acked-by: Corey Osgood corey.osgood@gmail.com
Modified: coreboot-v3/arch/x86/pci_ops_conf1.c =================================================================== --- coreboot-v3/arch/x86/pci_ops_conf1.c 2008-10-14 18:26:09 UTC (rev 928) +++ coreboot-v3/arch/x86/pci_ops_conf1.c 2008-10-15 06:41:16 UTC (rev 929) @@ -112,7 +112,6 @@ */
int pci_conf1_find_on_bus(u16 bus, u16 vid, u16 did, u32 *busdevfn) - { u16 devfn; u32 val;
Modified: coreboot-v3/include/device/pci_ids.h =================================================================== --- coreboot-v3/include/device/pci_ids.h 2008-10-14 18:26:09 UTC (rev 928) +++ coreboot-v3/include/device/pci_ids.h 2008-10-15 06:41:16 UTC (rev 929) @@ -263,4 +263,16 @@ #define PCI_DEVICE_ID_NVIDIA_MCP55_TRIM 0x036A #define PCI_DEVICE_ID_NVIDIA_MCP55_PMU 0x036B
+#define PCI_VENDOR_ID_VIA 0x1106 +#define PCI_DEVICE_ID_VIA_VT8237_EHCI 0x3104 +#define PCI_DEVICE_ID_VIA_VT8237_LAN 0x3065 +#define PCI_DEVICE_ID_VIA_VT8237R_LPC 0x3227 +#define PCI_DEVICE_ID_VIA_VT8237S_LPC 0x3372 +#define PCI_DEVICE_ID_VIA_VT8237_PATA 0x0571 +#define PCI_DEVICE_ID_VIA_VT8237R_SATA 0x3149 +#define PCI_DEVICE_ID_VIA_VT8237S_SATA 0x5372 +#define PCI_DEVICE_ID_VIA_VT8237_UHCI 0x3038 +#define PCI_DEVICE_ID_VIA_VT8237_VLINK 0x287e + + #endif /* DEVICE_PCI_IDS_H */
Modified: coreboot-v3/include/spd.h =================================================================== --- coreboot-v3/include/spd.h 2008-10-14 18:26:09 UTC (rev 928) +++ coreboot-v3/include/spd.h 2008-10-15 06:41:16 UTC (rev 929) @@ -105,10 +105,12 @@ #define SPD_tRAS SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY #define SPD_BANK_DENSITY SPD_DENSITY_OF_EACH_ROW_ON_MODULE #define SPD_ADDRESS_CMD_HOLD SPD_CMD_SIGNAL_INPUT_HOLD_TIME -#define SPD_tRC 41 /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */ -#define SPD_tRFC 42 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */ +#define SPD_tWR SPD_WRITE_RECOVERY_TIME +#define SPD_tWTR SPD_INT_WRITE_TO_READ_DELAY +#define SPD_tRTP SPD_INT_READ_TO_PRECHARGE_DELAY +#define SPD_tRC SPD_MIN_ACT_TO_ACT_AUTO_REFRESH +#define SPD_tRFC SPD_MIN_AUTO_REFRESH_TO_ACT
- /* SPD_MEMORY_TYPE values. */ #define SPD_MEMORY_TYPE_FPM_DRAM 1 #define SPD_MEMORY_TYPE_EDO 2
Modified: coreboot-v3/superio/winbond/w83627hf/stage1.c =================================================================== --- coreboot-v3/superio/winbond/w83627hf/stage1.c 2008-10-14 18:26:09 UTC (rev 928) +++ coreboot-v3/superio/winbond/w83627hf/stage1.c 2008-10-15 06:41:16 UTC (rev 929) @@ -25,7 +25,7 @@ void w83627hf_enable_serial(u8 dev, u8 serial, u16 iobase) { rawpnp_enter_ext_func_mode(dev); - rawpnp_set_logical_device(dev,serial); + rawpnp_set_logical_device(dev, serial); rawpnp_set_enable(dev, 0); rawpnp_set_iobase(dev, PNP_IDX_IO0, iobase); rawpnp_set_enable(dev, 1);