Author: hailfinger Date: 2008-02-11 02:30:24 +0100 (Mon, 11 Feb 2008) New Revision: 587
Modified: coreboot-v3/arch/x86/Kconfig coreboot-v3/arch/x86/stage0_i586.S coreboot-v3/include/arch/x86/amd_geodelx.h Log: CAR size and CAR base defines are scattered all over the place. Set them centrally from Kconfig, but keep the Kconfig variables hidden. That way, they are available everywhere, you don't have to try to guess where they are set, and they come with help text if you look at arch/x86/Kconfig. No semantic changes, although some of the settings really could use an overhaul.
This also is a requirement for my printk buffer patch.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net Acked-by: Peter Stuge peter@stuge.se
Modified: coreboot-v3/arch/x86/Kconfig =================================================================== --- coreboot-v3/arch/x86/Kconfig 2008-02-11 00:41:17 UTC (rev 586) +++ coreboot-v3/arch/x86/Kconfig 2008-02-11 01:30:24 UTC (rev 587) @@ -69,4 +69,17 @@ coreboot work correctly on symmetric multi processor systems. It is usually set in mainboard/*/Kconfig. - + +config CARBASE + hex + default 0x8f000 if CPU_I586 + default 0x80000 if CPU_AMD_GEODELX + help + This option sets the base address of the area used for CAR. + +config CARSIZE + hex + default 0x1000 if CPU_I586 + default 0x8000 if CPU_AMD_GEODELX + help + This option sets the size of the area used for CAR.
Modified: coreboot-v3/arch/x86/stage0_i586.S =================================================================== --- coreboot-v3/arch/x86/stage0_i586.S 2008-02-11 00:41:17 UTC (rev 586) +++ coreboot-v3/arch/x86/stage0_i586.S 2008-02-11 01:30:24 UTC (rev 587) @@ -183,18 +183,9 @@ * the other is very similar to the AMD CAR, except remove amd specific msr */
-#ifndef CONFIG_CARSIZE -#define CacheSize 4096 -#else #define CacheSize CONFIG_CARSIZE -#endif
-/* pick a safer value for default -- i.e. not the C segment! */ -#ifndef CONFIG_CARBASE -#define CacheBase (0x90000 - CacheSize) -#else #define CacheBase CONFIG_CARBASE -#endif
#define ASSEMBLY #include "mtrr.h"
Modified: coreboot-v3/include/arch/x86/amd_geodelx.h =================================================================== --- coreboot-v3/include/arch/x86/amd_geodelx.h 2008-02-11 00:41:17 UTC (rev 586) +++ coreboot-v3/include/arch/x86/amd_geodelx.h 2008-02-11 01:30:24 UTC (rev 587) @@ -565,8 +565,8 @@ #define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */
/* ------------------------ */ -#define DCACHE_RAM_SIZE 0x08000 -#define DCACHE_RAM_BASE 0x80000 +#define DCACHE_RAM_SIZE CONFIG_CARSIZE +#define DCACHE_RAM_BASE CONFIG_CARBASE /* This is where the DCache will be mapped and be used as stack. It would be * cool if it was the same base as coreboot normal stack. */