Hello,
On Mon, Apr 07, 2008 at 07:17:54PM +0530, malatesh kamatad wrote:
Hi... But in the data sheet they have mentioned like the SST49LF00xB detects whether it is being accessed via a FWH or LPC protocol by detecting the START field contents; a 1101b or 1110b indicates a Firmware Memory cycle and a 0000b indicates an LPC memory cycle.
Yes, that is correct.
but when i checked the content in the empty SST chip it shows like this
[root at localhost http://www.coreboot.org/mailman/listinfo/coreboot ~]# hexdump sst_after_erase.bin 0000000 ffff ffff ffff ffff ffff ffff ffff ffff
0080000
from this i came to know that SST chip is working in LPC mode as compared to data sheet ...is it right?
No, I am afraid not.
The LPC/FWH communication protocol will never be visible to flashrom and also never visible in files that flashrom reads or writes.
Those files simply contain the data that is or will be stored in flash chips.
All other technical details are dealt with either by the flashrom program, or by chips and circuits on the mainboard.
i am totally confusing....
The flash chip is connected to the southbridge via an LPC/FWH bus. Intel uses the FWH protocol, everyone else uses LPC. FWH and LPC are compatible electrically. (Almost the same signals.) Some flash chips support both LPC and FWH, but some only one of them.
When a program uses certain memory addresses the hardware on the mainboard doesn't send those reads or writes to RAM, but instead to the flash chip. A lot of translation goes on here, all in hardware and the program can not affect it very much. This is where the LPC/FWH details you mentioned from the data sheet happen, but again it is transparent to the program.
Each flash chip has some kind of algorithm that needs to be followed to write to the flash chip, special sequences of writing special data to special addresses in the flash chip with special timing - needed because there is no way for programs to communicate with the flash chip other than read and write.
flashrom has to implement this algorithm for every supported flash chip. My guess is that it is not working correctly for the SST flash chip type you are using.
But, it can also be an issue with how writes are translated on your mainboard. I am not sure that anyone has successfully used flashrom on the mainboard model that you are using.
In order to proceed debugging your mainboard you will at the very least need another working method to read, erase and write flash chips.
You may also need to learn those programming algorithms for the flash chip, and you may need to learn some details about the southbridge on your board, all depending on where the problem actually is.
If you can not wait for all this I recommend choosing another, known working, combination of mainboard and flash chip for your further work with coreboot.
What is the purpose of your work - maybe we can suggest a suitable combination?
please inform me how to find whether chip is in FWH or LPC mode.
Intel southbridge FWH Anything else LPC
..but, I don't think it matters.
//Peter